ARM OMAP AM33XX: create new ARCH for AM33xx
Created ARCH for AM33xx boards as second stage bootloader. This includes: - Added dmtimer0 - Created basic header files - Added MMC support for ARCH_AM33XX - Added reset function Signed-off-by: Teresa Gámez <t.gamez@phytec.de> Some header file cleanup by: Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -42,12 +42,23 @@ config ARCH_OMAP4
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help
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Say Y here if you are using Texas Instrument's OMAP4 based platform
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config ARCH_AM33XX
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bool "AM33xx"
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select CPU_V7
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select GENERIC_GPIO
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select OMAP_CLOCK_SOURCE_DMTIMER0
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help
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Say Y here if you are using Texas Instrument's AM33xx based platform
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endchoice
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# Blind enable all possible clocks.. think twice before you do this.
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config OMAP_CLOCK_SOURCE_S32K
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bool
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config OMAP_CLOCK_SOURCE_DMTIMER0
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bool
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config OMAP3_CLOCK_CONFIG
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prompt "Clock Configuration"
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bool
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@ -18,10 +18,12 @@
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obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o
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pbl-$(CONFIG_ARCH_OMAP) += syslib.o
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obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
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obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
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obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
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pbl-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o auxcr.o
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obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
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pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
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obj-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o
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obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
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pbl-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock.o
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obj-$(CONFIG_OMAP_GPMC) += gpmc.o devices-gpmc-nand.o
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@ -0,0 +1,29 @@
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/*
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* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <io.h>
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#include <mach/am33xx-silicon.h>
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#include <mach/am33xx-clock.h>
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void __noreturn reset_cpu(unsigned long addr)
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{
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writel(AM33XX_PRM_RSTCTRL_RESET, AM33XX_PRM_RSTCTRL);
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while (1);
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}
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@ -0,0 +1,89 @@
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/**
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* @file
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* @brief Support DMTimer0 counter
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*
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* FileName: arch/arm/mach-omap/dmtimer0.c
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*/
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/*
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* This File is based on arch/arm/mach-omap/s32k_clksource.c
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* (C) Copyright 2008
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* Texas Instruments, <www.ti.com>
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* Nishanth Menon <x0nishan@ti.com>
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*
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* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <clock.h>
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#include <init.h>
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#include <io.h>
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#include <mach/am33xx-silicon.h>
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#define CLK_RC32K 32768
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#define TIDR 0x0
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#define TIOCP_CFG 0x10
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#define IRQ_EOI 0x20
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#define IRQSTATUS_RAW 0x24
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#define IRQSTATUS 0x28
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#define IRQSTATUS_SET 0x2c
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#define IRQSTATUS_CLR 0x30
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#define IRQWAKEEN 0x34
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#define TCLR 0x38
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#define TCRR 0x3C
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#define TLDR 0x40
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#define TTGR 0x44
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#define TWPS 0x48
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#define TMAR 0x4C
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#define TCAR1 0x50
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#define TSICR 0x54
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#define TCAR2 0x58
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/**
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* @brief Provide a simple counter read
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*
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* @return DMTimer0 counter
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*/
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static uint64_t dmtimer0_read(void)
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{
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return readl(AM33XX_DMTIMER0_BASE + TCRR);
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}
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static struct clocksource dmtimer0_cs = {
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.read = dmtimer0_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 10,
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};
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/**
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* @brief Initialize the Clock
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*
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* Enable dmtimer0.
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*
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* @return result of @ref init_clock
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*/
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static int dmtimer0_init(void)
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{
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dmtimer0_cs.mult = clocksource_hz2mult(CLK_RC32K, dmtimer0_cs.shift);
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/* Enable counter */
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writel(0x3, AM33XX_DMTIMER0_BASE + TCLR);
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return init_clock(&dmtimer0_cs);
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}
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/* Run me at boot time */
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core_initcall(dmtimer0_init);
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@ -0,0 +1,23 @@
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/*
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* (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _AM33XX_CLOCKS_H_
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#define _AM33XX_CLOCKS_H_
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#endif /* endif _AM33XX_CLOCKS_H_ */
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@ -0,0 +1,49 @@
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/*
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* This file contains the address info for various AM33XX modules.
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*
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* Copyright (C) 2012 Teresa Gámez <t.gamez@phytec.de>,
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* Phytec Messtechnik GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __ASM_ARCH_AM33XX_H
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#define __ASM_ARCH_AM33XX_H
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/** AM335x Internal Bus Base addresses */
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#define AM33XX_L4_WKUP_BASE 0x44C00000
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#define AM33XX_L4_PER_BASE 0x48000000
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#define AM33XX_L4_FAST_BASE 0x4A000000
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/* UART */
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#define AM33XX_UART0_BASE (AM33XX_L4_WKUP_BASE + 0x209000)
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#define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000)
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#define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000)
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/* EMFI Registers */
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#define AM33XX_EMFI0_BASE 0x4C000000
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#define AM33XX_DRAM_ADDR_SPACE_START 0x80000000
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#define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000
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/* GPMC */
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#define AM33XX_GPMC_BASE 0x50000000
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/* MMC */
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#define AM33XX_MMCHS0_BASE (AM33XX_L4_PER_BASE + 0x60000)
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/* DTMTimer0 */
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#define AM33XX_DMTIMER0_BASE (AM33XX_L4_WKUP_BASE + 0x205000)
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/* PRM */
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#define AM33XX_PRM_BASE (AM33XX_L4_WKUP_BASE + 0x200000)
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#endif
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@ -67,7 +67,7 @@ config MCI_IMX_ESDHC_PIO
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config MCI_OMAP_HSMMC
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bool "OMAP HSMMC"
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depends on ARCH_OMAP4 || ARCH_OMAP3
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depends on ARCH_OMAP4 || ARCH_OMAP3 || ARCH_AM33XX
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help
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Enable this entry to add support to read and write SD cards on
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both OMAP3 and OMAP4 based systems.
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