ppc: cpu-85xx: upgrade MMU support to v2 pages sizes
TLB support for the 85xx CPUs has been upgraded to support the MMUv2 page size definitions. This has been imported from U-Boot version git-9407c3fc. This allows for future CPUs to make use of the new MMU support. Also the definition of MAX_MEM_MAPPED has been changed to avoid type casting with "min" macro. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
d95f27aaa8
commit
48b5b23286
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@ -123,21 +123,29 @@ static unsigned int e500_setup_ddr_tlbs_phys(phys_addr_t p_addr,
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unsigned int memsize_in_meg)
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{
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int i;
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unsigned int tlb_size;
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unsigned int wimge = 0;
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unsigned int tlb_size, max_cam, tsize_mask;
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unsigned int wimge = MAS2_M;
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unsigned int ram_tlb_address = (unsigned int)CFG_SDRAM_BASE;
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unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
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u64 size, memsize = (u64)memsize_in_meg << 20;
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size = min((u64)memsize, (u64)MAX_MEM_MAPPED);
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size = min(memsize, MAX_MEM_MAPPED);
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if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
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/* Convert (4^max) kB to (2^max) bytes */
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max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
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tsize_mask = ~1U;
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} else {
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/* Convert (2^max) kB to (2^max) bytes */
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max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
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tsize_mask = ~0U;
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}
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/* Convert (4^max) kB to (2^max) bytes */
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max_cam = (max_cam * 2) + 10;
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for (i = 0; size && (i < 8); i++) {
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for (i = 0; size && i < 8; i++) {
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int ram_tlb_index = e500_find_free_tlbcam();
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u32 camsize = __ilog2_u64(size) & ~1U;
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u32 align = __ilog2(ram_tlb_address) & ~1U;
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u32 camsize = __ilog2_u64(size) & tsize_mask;
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u32 align = __ilog2(ram_tlb_address) & tsize_mask;
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if (ram_tlb_index == -1)
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break;
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if (align == -2)
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align = max_cam;
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@ -147,7 +155,7 @@ static unsigned int e500_setup_ddr_tlbs_phys(phys_addr_t p_addr,
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if (camsize > max_cam)
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camsize = max_cam;
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tlb_size = (camsize - 10) / 2;
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tlb_size = camsize - 10;
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e500_set_tlb(1, ram_tlb_address, p_addr,
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MAS3_SX|MAS3_SW|MAS3_SR, wimge,
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@ -23,7 +23,7 @@
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#ifndef MAX_MEM_MAPPED
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#if defined(CONFIG_E500)
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#define MAX_MEM_MAPPED ((phys_size_t)(2 << 30))
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#define MAX_MEM_MAPPED (2ULL << 30)
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#endif
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#endif
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@ -382,7 +382,7 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID(x) (((x) << 16) & 0x3FFF0000)
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#define MAS1_TS 0x00001000
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#define MAS1_TSIZE(x) (((x) << 8) & 0x00000F00)
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#define MAS1_TSIZE(x) (((x) << 7) & 0x00000F80)
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#define MAS2_EPN 0xFFFFF000
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#define MAS2_SHAREN 0x00000200
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@ -438,18 +438,29 @@ extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
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#define FSL_BOOKE_MAS7(rpn) \
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(((u64)(rpn)) >> 32)
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#define BOOKE_PAGESZ_1K 0
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#define BOOKE_PAGESZ_4K 1
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#define BOOKE_PAGESZ_16K 2
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#define BOOKE_PAGESZ_64K 3
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#define BOOKE_PAGESZ_256K 4
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#define BOOKE_PAGESZ_1M 5
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#define BOOKE_PAGESZ_4M 6
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#define BOOKE_PAGESZ_16M 7
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#define BOOKE_PAGESZ_64M 8
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#define BOOKE_PAGESZ_256M 9
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#define BOOKE_PAGESZ_1GB 10
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#define BOOKE_PAGESZ_4GB 11
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#define BOOKE_PAGESZ_1K 0
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#define BOOKE_PAGESZ_2K 1
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#define BOOKE_PAGESZ_4K 2
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#define BOOKE_PAGESZ_8K 3
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#define BOOKE_PAGESZ_16K 4
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#define BOOKE_PAGESZ_32K 5
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#define BOOKE_PAGESZ_64K 6
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#define BOOKE_PAGESZ_128K 7
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#define BOOKE_PAGESZ_256K 8
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#define BOOKE_PAGESZ_512K 9
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#define BOOKE_PAGESZ_1M 10
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#define BOOKE_PAGESZ_2M 11
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#define BOOKE_PAGESZ_4M 12
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#define BOOKE_PAGESZ_8M 13
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#define BOOKE_PAGESZ_16M 14
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#define BOOKE_PAGESZ_32M 15
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#define BOOKE_PAGESZ_64M 16
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#define BOOKE_PAGESZ_128M 17
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#define BOOKE_PAGESZ_256M 18
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#define BOOKE_PAGESZ_512M 19
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#define BOOKE_PAGESZ_1G 20
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#define BOOKE_PAGESZ_2G 21
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#define BOOKE_PAGESZ_4G 22
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#if defined(CONFIG_MPC86xx)
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#define LAWBAR_BASE_ADDR 0x00FFFFFF
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@ -429,7 +429,12 @@
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
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#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
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#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
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#define SPRN_MMUCFG 0x3f7 /* MMU Configuration Register */
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#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
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#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
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#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
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#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
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#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
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#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
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