dts: update to v3.16-rc5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -9,6 +9,18 @@ Required Properties:
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- reg: physical base address of the controller and length of memory mapped
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region.
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Optional Properties:
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- clocks: List of clock handles. The parent clocks of the input clocks to the
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devices in this power domain are set to oscclk before power gating
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and restored back after powering on a domain. This is required for
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all domains which are powered on and off and not required for unused
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domains.
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- clock-names: The following clocks can be specified:
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- oscclk: Oscillator clock.
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- pclkN, clkN: Pairs of parent of input clock and input clock to the
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devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
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are supported currently.
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Node of a device using power domains must have a samsung,power-domain property
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defined with a phandle to respective power domain.
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@ -19,6 +31,14 @@ Example:
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reg = <0x10023C00 0x10>;
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};
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
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<&clock CLK_MOUT_USER_ACLK333>;
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clock-names = "oscclk", "pclk0", "clk0";
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};
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Example of the node using power domain:
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node {
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@ -4,6 +4,13 @@ Required properties:
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- compatible: Must contain one of the following:
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- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
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- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
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- "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
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- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
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- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
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- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
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- "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
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- "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
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- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
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- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
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@ -63,7 +63,6 @@
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#define CLK_SCLK_MPHY_IXTAL24 161
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/* gate clocks */
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#define CLK_ACLK66_PERIC 256
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#define CLK_UART0 257
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#define CLK_UART1 258
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#define CLK_UART2 259
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@ -203,6 +202,8 @@
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#define CLK_MOUT_G3D 641
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#define CLK_MOUT_VPLL 642
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#define CLK_MOUT_MAUDIO0 643
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#define CLK_MOUT_USER_ACLK333 644
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#define CLK_MOUT_SW_ACLK333 645
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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@ -529,8 +529,8 @@
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serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
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0 0 1 2
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>;
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tx-num-evt = <1>;
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rx-num-evt = <1>;
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tx-num-evt = <32>;
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rx-num-evt = <32>;
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};
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&tps {
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@ -560,8 +560,8 @@
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serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
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0 0 1 2
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>;
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tx-num-evt = <1>;
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rx-num-evt = <1>;
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tx-num-evt = <32>;
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rx-num-evt = <32>;
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};
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&tscadc {
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@ -105,10 +105,16 @@
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <0>;
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phy-mode = "rmii";
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <1>;
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phy-mode = "rmii";
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};
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&phy_sel {
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rmii-clock-ext;
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};
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&elm {
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@ -1045,6 +1045,8 @@
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reg = <0x00500000 0x80000
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0xf803c000 0x400>;
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interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&usb>, <&udphs_clk>;
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clock-names = "hclk", "pclk";
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status = "disabled";
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ep0 {
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@ -240,6 +240,7 @@
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regulator-name = "ldo3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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@ -673,10 +673,12 @@
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l3_iclk_div: l3_iclk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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compatible = "ti,divider-clock";
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ti,max-div = <2>;
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ti,bit-shift = <4>;
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reg = <0x0100>;
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clocks = <&dpll_core_h12x2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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ti,index-power-of-two;
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};
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l4_root_clk_div: l4_root_clk_div {
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@ -684,7 +686,7 @@
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compatible = "fixed-factor-clock";
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clocks = <&l3_iclk_div>;
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clock-mult = <1>;
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clock-div = <1>;
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clock-div = <2>;
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};
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video1_clk2_div: video1_clk2_div {
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@ -554,7 +554,7 @@
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interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
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clocks = <&clock CLK_PWM>;
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clock-names = "timers";
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#pwm-cells = <2>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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@ -167,7 +167,7 @@
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compatible = "samsung,exynos5420-audss-clock";
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reg = <0x03810000 0x0C>;
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#clock-cells = <1>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
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<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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};
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@ -260,6 +260,9 @@
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mfc_pd: power-domain@10044060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10044060 0x20>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
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<&clock CLK_MOUT_USER_ACLK333>;
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clock-names = "oscclk", "pclk0", "clk0";
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};
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disp_pd: power-domain@100440C0 {
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