video: ipufb: do not use bitfields
bitfields are not portable and one should make assumptions of the layout of bitfields. Replace them with the ipu_ch_param_write_field() which is already used in the mainline IPUv3 driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
68a6fedcd4
commit
497436eb58
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@ -281,110 +281,96 @@ static struct imx_ipu_fb_rgb def_rgb_32 = {
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.transp = {.offset = 24, .length = 8,},
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};
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struct chan_param_mem_planar {
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/* Word 0 */
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u32 xv:10;
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u32 yv:10;
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u32 xb:12;
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#define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
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u32 yb:12;
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u32 res1:2;
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u32 nsb:1;
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u32 lnpb:6;
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u32 ubo_l:11;
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#define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
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#define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 10)
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#define IPU_FIELD_XB IPU_CPMEM_WORD(0, 20, 12)
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u32 ubo_h:15;
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u32 vbo_l:17;
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#define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
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#define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 44, 1)
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#define IPU_FIELD_RES1 IPU_CPMEM_WORD(0, 45, 1)
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#define IPU_FIELD_NSB IPU_CPMEM_WORD(0, 46, 1)
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#define IPU_FIELD_LNPB IPU_CPMEM_WORD(0, 47, 6)
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#define IPU_FIELD_SX IPU_CPMEM_WORD(0, 53, 10)
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#define IPU_FIELD_SY_L IPU_CPMEM_WORD(0, 63, 1)
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u32 vbo_h:9;
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u32 res2:3;
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u32 fw:12;
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u32 fh_l:8;
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#define IPU_FIELD_SY_H IPU_CPMEM_WORD(0, 64, 9)
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#define IPU_FIELD_NS IPU_CPMEM_WORD(0, 73, 10)
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#define IPU_FIELD_SM IPU_CPMEM_WORD(0, 83, 10)
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#define IPU_FIELD_SDX_L IPU_CPMEM_WORD(0, 93, 3)
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u32 fh_h:4;
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u32 res3:28;
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#define IPU_FIELD_SDX_H IPU_CPMEM_WORD(0, 96, 2)
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#define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 5)
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#define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 103, 1)
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#define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 104, 1)
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#define IPU_FIELD_SDR1 IPU_CPMEM_WORD(0, 105, 1)
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#define IPU_FIELD_RES2 IPU_CPMEM_WORD(0, 106, 2)
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#define IPU_FIELD_FW IPU_CPMEM_WORD(0, 108, 12)
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#define IPU_FIELD_FH_L IPU_CPMEM_WORD(0, 120, 8)
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/* Word 1 */
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u32 eba0;
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#define IPU_FIELD_FH_H IPU_CPMEM_WORD(0, 128, 4)
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#define IPU_FIELD_RES3 IPU_CPMEM_WORD(0, 132, 28)
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u32 eba1;
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#define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 32)
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u32 bpp:3;
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u32 sl:14;
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u32 pfs:3;
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u32 bam:3;
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u32 res4:2;
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u32 npb:6;
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u32 res5:1;
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#define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 32, 32)
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u32 sat:2;
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u32 res6:30;
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} __attribute__ ((packed));
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#define IPU_FIELD_BPP IPU_CPMEM_WORD(1, 64, 3)
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#define IPU_FIELD_SL IPU_CPMEM_WORD(1, 67, 14)
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#define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 81, 3)
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#define IPU_FIELD_BAM IPU_CPMEM_WORD(1, 84, 3)
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#define IPU_FIELD_RES4 IPU_CPMEM_WORD(1, 87, 2)
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#define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 89, 6)
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#define IPU_FIELD_RES5 IPU_CPMEM_WORD(1, 95, 1)
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struct chan_param_mem_interleaved {
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/* Word 0 */
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u32 xv:10;
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u32 yv:10;
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u32 xb:12;
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#define IPU_FIELD_SAT IPU_CPMEM_WORD(1, 96, 2)
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#define IPU_FIELD_SCC IPU_CPMEM_WORD(1, 98, 1)
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#define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 99, 5)
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#define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 104, 5)
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#define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 109, 5)
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#define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 114, 5)
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#define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 119, 3)
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#define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 122, 3)
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#define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 125, 3)
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u32 yb:12;
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u32 sce:1;
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u32 res1:1;
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u32 nsb:1;
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u32 lnpb:6;
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u32 sx:10;
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u32 sy_l:1;
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#define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 128, 3)
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#define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(1, 131, 1)
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#define IPU_FIELD_RES6 IPU_CPMEM_WORD(1, 132, 28)
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u32 sy_h:9;
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u32 ns:10;
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u32 sm:10;
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u32 sdx_l:3;
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u32 sdx_h:2;
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u32 sdy:5;
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u32 sdrx:1;
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u32 sdry:1;
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u32 sdr1:1;
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u32 res2:2;
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u32 fw:12;
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u32 fh_l:8;
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u32 fh_h:4;
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u32 res3:28;
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/* Word 1 */
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u32 eba0;
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u32 eba1;
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u32 bpp:3;
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u32 sl:14;
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u32 pfs:3;
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u32 bam:3;
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u32 res4:2;
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u32 npb:6;
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u32 res5:1;
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u32 sat:2;
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u32 scc:1;
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u32 ofs0:5;
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u32 ofs1:5;
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u32 ofs2:5;
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u32 ofs3:5;
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u32 wid0:3;
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u32 wid1:3;
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u32 wid2:3;
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u32 wid3:3;
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u32 dec_sel:1;
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u32 res6:28;
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} __attribute__ ((packed));
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union chan_param_mem {
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struct chan_param_mem_planar pp;
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struct chan_param_mem_interleaved ip;
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struct ipu_cpmem_word {
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u32 data[5];
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};
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struct ipu_ch_param {
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struct ipu_cpmem_word word[2];
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};
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void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v)
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{
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u32 bit = (wbs >> 8) % 160;
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u32 size = wbs & 0xff;
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u32 word = (wbs >> 8) / 160;
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u32 i = bit / 32;
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u32 ofs = bit % 32;
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u32 mask = (1 << size) - 1;
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u32 val;
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pr_debug("%s %d %d %d\n", __func__, word, bit , size);
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val = readl(&base->word[word].data[i]);
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val &= ~(mask << ofs);
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val |= v << ofs;
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writel(val, &base->word[word].data[i]);
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if ((bit + size - 1) / 32 > i) {
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val = readl(&base->word[word].data[i + 1]);
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val &= ~(mask >> (ofs ? (32 - ofs) : 0));
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val |= v >> (ofs ? (32 - ofs) : 0);
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writel(val, &base->word[word].data[i + 1]);
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}
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}
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static inline u32 reg_read(struct ipu_fb_info *fbi, unsigned long reg)
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{
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u32 val;
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@ -500,60 +486,61 @@ static int sdc_init_panel(struct fb_info *info, enum disp_data_mapping fmt)
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return 0;
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}
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static void ipu_ch_param_set_size(union chan_param_mem *params,
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static void ipu_ch_param_set_size(struct ipu_ch_param *p,
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u32 pixel_fmt, uint16_t width,
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uint16_t height, uint16_t stride)
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{
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params->pp.fw = width - 1;
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params->pp.fh_l = height - 1;
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params->pp.fh_h = (height - 1) >> 8;
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params->pp.sl = stride - 1;
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ipu_ch_param_write_field(p, IPU_FIELD_FW, width - 1);
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ipu_ch_param_write_field(p, IPU_FIELD_FH_L, height - 1);
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ipu_ch_param_write_field(p, IPU_FIELD_FH_H, (height - 1) >> 8);
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ipu_ch_param_write_field(p, IPU_FIELD_SL, stride - 1);
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/* See above, for further formats see the Linux driver */
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switch (pixel_fmt) {
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case IPU_PIX_FMT_RGB565:
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params->ip.bpp = 2;
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params->ip.pfs = 4;
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params->ip.npb = 7;
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params->ip.sat = 2; /* SAT = 32-bit access */
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params->ip.ofs0 = 0; /* Red bit offset */
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params->ip.ofs1 = 5; /* Green bit offset */
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params->ip.ofs2 = 11; /* Blue bit offset */
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params->ip.ofs3 = 16; /* Alpha bit offset */
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params->ip.wid0 = 4; /* Red bit width - 1 */
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params->ip.wid1 = 5; /* Green bit width - 1 */
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params->ip.wid2 = 4; /* Blue bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_BPP, 2);
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ipu_ch_param_write_field(p, IPU_FIELD_PFS, 4);
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ipu_ch_param_write_field(p, IPU_FIELD_NPB, 7);
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ipu_ch_param_write_field(p, IPU_FIELD_SAT, 2); /* SAT = 32-bit access */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS0, 0); /* Red bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS1, 5); /* Green bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS2, 11); /* Blue bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS3, 16); /* Alpha bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_WID0, 4); /* Red bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_WID1, 5); /* Green bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_WID2, 4); /* Blue bit width - 1 */
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break;
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case IPU_PIX_FMT_RGB24:
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params->ip.bpp = 1; /* 24 BPP & RGB PFS */
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params->ip.pfs = 4;
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params->ip.npb = 7;
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params->ip.sat = 2; /* SAT = 32-bit access */
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params->ip.ofs0 = 16; /* Red bit offset */
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params->ip.ofs1 = 8; /* Green bit offset */
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params->ip.ofs2 = 0; /* Blue bit offset */
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params->ip.ofs3 = 24; /* Alpha bit offset */
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params->ip.wid0 = 7; /* Red bit width - 1 */
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params->ip.wid1 = 7; /* Green bit width - 1 */
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params->ip.wid2 = 7; /* Blue bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_BPP, 1); /* 24 BPP & RGB PFS */
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ipu_ch_param_write_field(p, IPU_FIELD_PFS, 4);
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ipu_ch_param_write_field(p, IPU_FIELD_NPB, 7);
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ipu_ch_param_write_field(p, IPU_FIELD_SAT, 2); /* SAT = 32-bit access */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS0, 16); /* Red bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS1, 8); /* Green bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS2, 0); /* Blue bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_OFS3, 24); /* Alpha bit offset */
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ipu_ch_param_write_field(p, IPU_FIELD_WID0, 7); /* Red bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_WID1, 7); /* Green bit width - 1 */
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ipu_ch_param_write_field(p, IPU_FIELD_WID2, 7); /* Blue bit width - 1 */
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break;
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default:
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break;
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}
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params->pp.nsb = 1;
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ipu_ch_param_write_field(p, IPU_FIELD_NSB, 1);
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}
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static void ipu_ch_param_set_buffer(union chan_param_mem *params,
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void *buf0, void *buf1)
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static void ipu_ch_param_set_buffer(struct ipu_ch_param *p, void *buf0, void *buf1)
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{
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params->pp.eba0 = (u32)buf0;
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params->pp.eba1 = (u32)buf1;
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ipu_ch_param_write_field(p, IPU_FIELD_EBA0, (u32)buf0);
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ipu_ch_param_write_field(p, IPU_FIELD_EBA1, (u32)buf1);
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}
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static void ipu_write_param_mem(struct ipu_fb_info *fbi, u32 addr,
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u32 *data, u32 num_words)
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struct ipu_ch_param *p, u32 num_words)
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{
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u32 *data = (void *)p;
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for (; num_words > 0; num_words--) {
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reg_write(fbi, addr, IPU_IMA_ADDR);
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reg_write(fbi, *data++, IPU_IMA_DATA);
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@ -586,7 +573,7 @@ static u32 dma_param_addr(enum ipu_channel channel)
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static void ipu_init_channel_buffer(struct ipu_fb_info *fbi,
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enum ipu_channel channel, void *fbmem)
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{
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union chan_param_mem params = {};
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struct ipu_ch_param p = {};
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u32 reg;
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u32 stride_bytes;
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@ -594,23 +581,23 @@ static void ipu_init_channel_buffer(struct ipu_fb_info *fbi,
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stride_bytes = (stride_bytes + 3) & ~3;
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/* Build parameter memory data for DMA channel */
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ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(fbi->info.bits_per_pixel),
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ipu_ch_param_set_size(&p, bpp_to_pixfmt(fbi->info.bits_per_pixel),
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fbi->info.xres, fbi->info.yres, stride_bytes);
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ipu_ch_param_set_buffer(¶ms, fbmem, NULL);
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params.pp.bam = 0;
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/* Some channels (rotation) have restriction on burst length */
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ipu_ch_param_set_buffer(&p, fbmem, NULL);
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/* Some channels (rotation) have restriction on burst length */
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switch (channel) {
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case IDMAC_SDC_0:
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case IDMAC_SDC_1:
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/* In original code only IPU_PIX_FMT_RGB565 was setting burst */
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params.pp.npb = 16 - 1;
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ipu_ch_param_write_field(&p, IPU_FIELD_NPB, 16 - 1);
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break;
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default:
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break;
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}
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ipu_write_param_mem(fbi, dma_param_addr(channel), (u32 *)¶ms, 10);
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ipu_write_param_mem(fbi, dma_param_addr(channel), &p, 10);
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/* Disable double-buffering */
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reg = reg_read(fbi, IPU_CHA_DB_MODE_SEL);
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