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at91: PIT: switch to platform_driver 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2012-12-28 20:16:09 +01:00 committed by Sascha Hauer
parent e7edecb87a
commit 49edc4c987
15 changed files with 57 additions and 19 deletions
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1
arch/arm/mach-at91/at91sam9260.c
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@ -239,6 +239,7 @@ static int at91sam9260_gpio_init(void)
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_pit(AT91SAM9260_BASE_PIT);
return 0;
}

1
arch/arm/mach-at91/at91sam9261.c
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@ -231,6 +231,7 @@ static int at91sam9261_gpio_init(void)
at91_add_rm9200_gpio(0, AT91_BASE_PIOA);
at91_add_rm9200_gpio(1, AT91_BASE_PIOB);
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_pit(AT91SAM9261_BASE_PIT);
return 0;
}

1
arch/arm/mach-at91/at91sam9263.c
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@ -250,6 +250,7 @@ static int at91sam9263_gpio_init(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_pit(AT91SAM9263_BASE_PIT);
return 0;
}

50
arch/arm/mach-at91/at91sam926x_time.c
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@ -30,15 +30,20 @@
#include <clock.h>
#include <asm/hardware.h>
#include <mach/at91_pit.h>
#include <mach/at91_rstc.h>
#include <mach/io.h>
#include <io.h>
#include <linux/clk.h>
#include <linux/err.h>
#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
#define pit_write(reg, val) __raw_writel(val, pit_base + reg)
#define pit_read(reg) __raw_readl(pit_base + reg)
static __iomem void *pit_base;
uint64_t at91sam9_clocksource_read(void)
{
return at91_sys_read(AT91_PIT_PIIR);
return pit_read(AT91_PIT_PIIR);
}
static struct clocksource cs = {
@ -47,30 +52,48 @@ static struct clocksource cs = {
.shift = 10,
};
static int clocksource_init (void)
static void at91_pit_stop(void)
{
/* Disable timer and irqs */
pit_write(AT91_PIT_MR, 0);
/* Clear any pending interrupts, wait for PIT to stop counting */
while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0);
}
static void at91sam926x_pit_reset(void)
{
at91_pit_stop();
/* Start PIT but don't enable IRQ */
pit_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
}
static int at91_pit_probe(struct device_d *dev)
{
struct clk *clk;
u32 pit_rate;
int ret;
clk = clk_get(NULL, "mck");
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
pr_err("clock not found: %d\n", ret);
dev_err(dev, "clock not found: %d\n", ret);
return ret;
}
ret = clk_enable(clk);
if (ret < 0) {
pr_err("clock failed to enable: %d\n", ret);
dev_err(dev, "clock failed to enable: %d\n", ret);
clk_put(clk);
return ret;
}
pit_base = dev_request_mem_region(dev, 0);
pit_rate = clk_get_rate(clk) / 16;
/* Enable PITC */
at91_sys_write(AT91_PIT_MR, 0xfffff | AT91_PIT_PITEN);
at91sam926x_pit_reset();
cs.mult = clocksource_hz2mult(pit_rate, cs.shift);
@ -79,4 +102,13 @@ static int clocksource_init (void)
return 0;
}
core_initcall(clocksource_init);
static struct driver_d at91_pit_driver = {
.name = "at91-pit",
.probe = at91_pit_probe,
};
static int at91_pit_init(void)
{
return platform_driver_register(&at91_pit_driver);
}
postcore_initcall(at91_pit_init);

1
arch/arm/mach-at91/at91sam9g45.c
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@ -263,6 +263,7 @@ static int at91sam9g45_gpio_init(void)
at91_add_rm9200_gpio(2, AT91_BASE_PIOC);
at91_add_rm9200_gpio(3, AT91_BASE_PIOD);
at91_add_rm9200_gpio(4, AT91_BASE_PIOE);
at91_add_pit(AT91SAM9G45_BASE_PIT);
return 0;
}

1
arch/arm/mach-at91/at91sam9n12.c
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@ -222,6 +222,7 @@ static int at91sam9n12_gpio_init(void)
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_pit(AT91SAM9N12_BASE_PIT);
return 0;
}

1
arch/arm/mach-at91/at91sam9x5.c
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@ -307,6 +307,7 @@ static int at91sam9x5_gpio_init(void)
at91_add_sam9x5_gpio(1, AT91_BASE_PIOB);
at91_add_sam9x5_gpio(2, AT91_BASE_PIOC);
at91_add_sam9x5_gpio(3, AT91_BASE_PIOD);
at91_add_pit(AT91SAM9X5_BASE_PIT);
return 0;
}

6
arch/arm/mach-at91/generic.h
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@ -22,3 +22,9 @@ static inline struct device_d *at91_add_sam9x5_gpio(int id, resource_size_t star
return add_generic_device("at91sam9x5-gpio", id, NULL, start, 512,
IORESOURCE_MEM, NULL);
}
static inline struct device_d *at91_add_pit(resource_size_t start)
{
return add_generic_device("at91-pit", DEVICE_ID_SINGLE, NULL, start, 16,
IORESOURCE_MEM, NULL);
}

8
arch/arm/mach-at91/include/mach/at91_pit.h
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@ -16,16 +16,16 @@
#ifndef AT91_PIT_H
#define AT91_PIT_H
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_MR 0x00 /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_SR 0x04 /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */

1
arch/arm/mach-at91/include/mach/at91sam9260.h
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@ -105,7 +105,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA

1
arch/arm/mach-at91/include/mach/at91sam9261.h
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@ -91,7 +91,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA

1
arch/arm/mach-at91/include/mach/at91sam9263.h
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@ -109,7 +109,6 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA

1
arch/arm/mach-at91/include/mach/at91sam9g45.h
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@ -120,7 +120,6 @@
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA

1
arch/arm/mach-at91/include/mach/at91sam9n12.h
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@ -116,7 +116,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA

1
arch/arm/mach-at91/include/mach/at91sam9x5.h
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@ -123,7 +123,6 @@
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA