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Merge branch 'master' of http://www.denx.de/git/u-boot

This commit is contained in:
Jon Loeliger 2006-08-22 10:17:59 -05:00
parent 5de62c47a8 5196a7a03b
commit 4b7576fb80
38 changed files with 1434 additions and 101 deletions
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49
CHANGELOG
View File

@ -2,6 +2,55 @@
Changes since U-Boot 1.1.4:
======================================================================
* Add support for WTK FO300 board (TQM5200 based).
* Fix TQM834x hang.
* Update for SC520 board.
Patch by David Updegraff, 02 Dec 2005
* Fixed common.h spelling error.
Patch by Cory Tusar, 30 Nov 2005
* Fix typo.
Patch by Andreas Engel, 28 Nov 2005
* Fix fatload command on FAT32 formatted partitions.
Patch by Joachim Jaeger, 18 Nov 2005
* Fix drivers/dm9000.c when configured in 32 bit mode.
Patch by Eric Benard, 17 Nov 2005
* Cleanup debug code for yucca board.
* MCC200: restrict addressable flash space to 32 MB
* Add debug console on COM12 for MCC200 board
* Fix control-c handing in CONFIG_CMDLINE_EDITING
Properly pass break code back from readline.
Patch by Roger Blofeld, 31 Jul 2006
* Add commandline history support to all AMCC eval boards
Patch by Stefan Roese, 07 Aug 2006
* Add Macronix MXLV320T flash support for AMCC Bamboo
Patch by Stefan Roese, 07 Aug 2006
* Change "mii info" to not print an error upon missing PHY at address
Patch by Stefan Roese, 07 Aug 2006
* Fix PCI-Express on PPC440SPe rev. A.
* Fix preboot message on TQM85xx after switching to hush parser.
* Adapt TQM85xx ramdisk address to Linux kernel memory map
* Add initial support for PCI-Express on PPC440SPe (Yucca board).
* Fix compiler warning for TRAB board.
Patch by Martin Krause, 07 Aug 2006
* Prevent USB commands from working when USB is stopped.
* Add rudimentary handling of alternate settings of USB interfaces.

10
MAKEALL
View File

@ -25,11 +25,11 @@ LIST_5xx=" \
#########################################################################
LIST_5xxx=" \
BC3450 cpci5200 EVAL5200 icecube_5100 \
icecube_5200 lite5200b mcc200 o2dnt \
pf5200 PM520 TB5200 Total5100 \
Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
TQM5200S \
BC3450 cpci5200 EVAL5200 fo300 \
icecube_5100 icecube_5200 lite5200b mcc200 \
o2dnt pf5200 PM520 TB5200 \
Total5100 Total5200 Total5200_Rev2 TQM5200 \
TQM5200_B TQM5200S \
"
#########################################################################

30
Makefile
View File

@ -328,6 +328,7 @@ lite5200b_LOWBOOT_config: unconfig
mcc200_config \
mcc200_SDRAM \
mcc200_highboot \
mcc200_COM12 \
mcc200_highboot_SDRAM: unconfig
@ >include/config.h
@[ -n "$(findstring highboot,$@)" ] || \
@ -344,6 +345,10 @@ mcc200_highboot_SDRAM: unconfig
{ echo "#define CONFIG_MCC200_SDRAM" >>include/config.h ; \
echo "... with SDRAM" ; \
}
@[ -z "$(findstring COM12,$@)" ] || \
{ echo "#define CONFIG_CONSOLE_COM12" >>include/config.h ; \
echo "... with console on COM12" ; \
}
@./mkconfig -a mcc200 ppc mpc5xxx mcc200
o2dnt_config:
@ -415,25 +420,30 @@ Total5200_Rev2_lowboot_config: unconfig
}
@./mkconfig -a Total5200 ppc mpc5xxx total5200
TQM5200_config \
TQM5200_B_config \
TQM5200_B_HIGHBOOT_config \
cam5200_config \
fo300_config \
MiniFAP_config \
TQM5200S_config \
TQM5200S_HIGHBOOT_config \
TQM5200_STK100_config \
cam5200_config \
MiniFAP_config: unconfig
TQM5200_B_config \
TQM5200_B_HIGHBOOT_config \
TQM5200_config \
TQM5200_STK100_config: unconfig
@ >include/config.h
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
@[ -z "$(findstring cam5200,$@)" ] || \
{ echo "#define CONFIG_CAM5200" >>include/config.h ; \
echo "#define CONFIG_TQM5200S" >>include/config.h ; \
echo "#define CONFIG_TQM5200_B" >>include/config.h ; \
echo "... TQM5200S on Cam5200" ; \
}
@[ -z "$(findstring fo300,$@)" ] || \
{ echo "#define CONFIG_FO300" >>include/config.h ; \
echo "... TQM5200 on FO300" ; \
}
@[ -z "$(findstring MiniFAP,$@)" ] || \
{ echo "#define CONFIG_MINIFAP" >>include/config.h ; \
echo "... TQM5200_AC on MiniFAP" ; \
}
@[ -z "$(findstring STK100,$@)" ] || \
{ echo "#define CONFIG_STK52XX_REV100" >>include/config.h ; \
echo "... on a STK52XX.100 base board" ; \

30
board/amcc/common/flash.c
View File

@ -76,6 +76,9 @@ void flash_print_info(flash_info_t * info)
case FLASH_MAN_SST:
printf("SST ");
break;
case FLASH_MAN_MX:
printf ("MACRONIX ");
break;
default:
printf("Unknown Vendor ");
break;
@ -124,6 +127,9 @@ void flash_print_info(flash_info_t * info)
case FLASH_STMW320DT:
printf ("M29W320DT (32 M, top sector)\n");
break;
case FLASH_MXLV320T:
printf ("MXLV320T (32 Mbit, top sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
@ -375,6 +381,7 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
return flash_erase_2(info, s_first, s_last);
} else {
@ -555,6 +562,7 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
{
if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT)) {
return write_word_2(info, dest, data);
} else {
@ -648,6 +656,9 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
info->flash_id = FLASH_MAN_MX;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
@ -676,6 +687,12 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
info->sector_count = 67;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
info->flash_id += FLASH_MXLV320T;
info->sector_count = 71;
info->size = 0x00400000;
break; /* => 4 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
@ -711,6 +728,19 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
--i;
info->start[i] = base;
}
} else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) {
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00002000;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000a000;
info->start[i--] = base + info->size - 0x0000c000;
info->start[i--] = base + info->size - 0x0000e000;
info->start[i--] = base + info->size - 0x00010000;
for (; i >= 0; i--)
info->start[i] = base + i * 0x00010000;
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */

56
board/amcc/yucca/init.S
View File

@ -82,9 +82,12 @@
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
/**************************************************************************
* TLB table for revA
*************************************************************************/
.globl tlbtabA
tlbtabA:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
@ -94,11 +97,56 @@ tlbtab:
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE,SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_OPER_FLASH,SZ_16M,0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
/**************************************************************************
* TLB table for revB
*
* Notice: revB of the 440SPe chip is very strict about PLB real addresses
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.
*************************************************************************/
.globl tlbtabB
tlbtabB:
tlbtab_start
tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbtab_end

130
board/amcc/yucca/yucca.c
View File

@ -21,12 +21,16 @@
* MA 02111-1307 USA
*
* Port to AMCC-440SPE Evaluation Board SOP - April 2005
*
* PCIe supporting routines derived from Linux 440SPe PCIe driver.
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
#include "yucca.h"
void fpga_init (void);
@ -39,6 +43,9 @@ int get_console_port(void);
unsigned long ppcMfcpr(unsigned long cpr_reg);
unsigned long ppcMfsdr(unsigned long sdr_reg);
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
#define DEBUG_ENV
#ifdef DEBUG_ENV
#define DEBUGF(fmt,args...) printf(fmt ,##args)
@ -908,6 +915,7 @@ void pci_target_init(struct pci_controller * hose )
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*************************************************************************
* is_pci_host
*
@ -923,12 +931,132 @@ void pci_target_init(struct pci_controller * hose )
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* The yucca board is always configured as host. */
return 1;
}
int yucca_pcie_card_present(int port)
{
u16 reg;
reg = in_be16((u16 *)FPGA_REG1C);
switch(port) {
case 0:
return !(reg & FPGA_REG1C_PE0_PRSNT);
case 1:
return !(reg & FPGA_REG1C_PE1_PRSNT);
case 2:
return !(reg & FPGA_REG1C_PE2_PRSNT);
default:
return 0;
}
}
/*
* For the given slot, set rootpoint mode, send power to the slot,
* turn on the green LED and turn off the yellow LED, enable the clock
* and turn off reset.
*/
void yucca_setup_pcie_fpga_rootpoint(int port)
{
u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
switch(port) {
case 0:
rootpoint = FPGA_REG1C_PE0_ROOTPOINT;
endpoint = 0;
power = FPGA_REG1A_PE0_PWRON;
green_led = FPGA_REG1A_PE0_GLED;
clock = FPGA_REG1A_PE0_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE0_YLED;
reset_off = FPGA_REG1C_PE0_PERST;
break;
case 1:
rootpoint = 0;
endpoint = FPGA_REG1C_PE1_ENDPOINT;
power = FPGA_REG1A_PE1_PWRON;
green_led = FPGA_REG1A_PE1_GLED;
clock = FPGA_REG1A_PE1_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE1_YLED;
reset_off = FPGA_REG1C_PE1_PERST;
break;
case 2:
rootpoint = 0;
endpoint = FPGA_REG1C_PE2_ENDPOINT;
power = FPGA_REG1A_PE2_PWRON;
green_led = FPGA_REG1A_PE2_GLED;
clock = FPGA_REG1A_PE2_REFCLK_ENABLE;
yellow_led = FPGA_REG1A_PE2_YLED;
reset_off = FPGA_REG1C_PE2_PERST;
break;
default:
return;
}
out_be16((u16 *)FPGA_REG1A,
~(power | clock | green_led) &
(yellow_led | in_be16((u16 *)FPGA_REG1A)));
out_be16((u16 *)FPGA_REG1C,
~(endpoint | reset_off) &
(rootpoint | in_be16((u16 *)FPGA_REG1C)));
/*
* Leave device in reset for a while after powering on the
* slot to give it a chance to initialize.
*/
udelay(250 * 1000);
out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
}
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
{
struct pci_controller *hose;
int i, bus;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = 1;
for (i = 0; i <= 2; i++) {
/* Check for yucca card presence */
if (!yucca_pcie_card_present(i))
continue;
yucca_setup_pcie_fpga_rootpoint(i);
if (ppc440spe_init_pcie_rootport(i)) {
printf("PCIE%d: initialization failed\n", i);
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
bus++;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
PCI_REGION_MEM
);
hose->region_count = 1;
pci_register_hose(hose);
ppc440spe_setup_pcie(hose, i);
hose->last_busno = pci_hose_scan(hose);
}
}
#endif /* defined(CONFIG_PCI) */
int misc_init_f (void)

8
board/mcc200/mcc200.c
View File

@ -203,6 +203,8 @@ int checkboard (void)
int misc_init_r (void)
{
ulong flash_sup_end, snum;
/*
* Adjust flash start and offset to detected values
*/
@ -257,6 +259,12 @@ int misc_init_r (void)
(flash_info[0].start[0] - 1) + flash_info[0].size,
&flash_info[0]);
*(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
flash_info[0].size = 32 << 20;
for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
flash_info[0].start[snum] < flash_sup_end;
snum++);
flash_info[0].sector_count = snum;
}
return (0);

27
board/tqm5200/cmd_stk52xx.c
View File

@ -30,8 +30,8 @@
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
#if defined (CONFIG_STK52XX)
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define DEFAULT_VOL 45
#define DEFAULT_FREQ 500
#define DEFAULT_DURATION 200
@ -537,7 +537,9 @@ static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return rcode;
}
#endif
#if defined(CONFIG_STK52XX)
void led_init(void)
{
struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
@ -736,7 +738,9 @@ int do_led(char *argv[])
return 0;
}
#endif
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
/*
* return 1 on CAN initialization failure
* return 0 if no failure
@ -1106,6 +1110,7 @@ int do_rs232(char *argv[])
return error_status;
}
#ifndef CONFIG_FO300
static void sm501_backlight (unsigned int state)
{
if (state == BL_ON) {
@ -1115,6 +1120,7 @@ static void sm501_backlight (unsigned int state)
*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
~((1 << 26) | (1 << 27));
}
#endif
int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
@ -1124,7 +1130,9 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf ("Revision 100 of STK52XX not supported!\n");
return 1;
#endif
#if defined(CONFIG_STK52XX)
led_init();
#endif
can_init();
switch (argc) {
@ -1152,6 +1160,7 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
printf ("Error\n");
return rcode;
#ifndef CONFIG_FO300
} else if (strncmp (argv[1], "backlight", 4) == 0) {
if (strncmp (argv[2], "on", 2) == 0) {
sm501_backlight (BL_ON);
@ -1161,14 +1170,17 @@ int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
sm501_backlight (BL_OFF);
return 0;
}
#endif
}
break;
#if defined(CONFIG_STK52XX)
case 4:
if (strcmp (argv[1], "led") == 0) {
return (do_led (argv));
}
break;
#endif
default:
break;
@ -1204,7 +1216,9 @@ U_BOOT_CMD(
"[channel]\n"
" - play short beep on \"l\"eft or \"r\"ight channel\n"
);
#endif /* CONFIG_STK52XX || CONFIG_FO300 */
#if defined(CONFIG_STK52XX)
U_BOOT_CMD(
fkt , 4, 1, cmd_fkt,
"fkt - Function test routines\n",
@ -1217,5 +1231,14 @@ U_BOOT_CMD(
"fkt backlight on/off\n"
" - switch backlight on or off\n"
);
#endif /* CONFIG_STK52XX */
#elif defined(CONFIG_FO300)
U_BOOT_CMD(
fkt , 3, 1, cmd_fkt,
"fkt - Function test routines\n",
"fkt can\n"
" - loopback plug for X16/X29 required\n"
"fkt rs232 number\n"
" - loopback plug(s) for X21/X22 required\n"
);
#endif
#endif /* CFG_CMD_BSP */

66
board/tqm5200/tqm5200.c
View File

@ -290,8 +290,10 @@ int checkboard (void)
# define CARRIER_NAME "TB5200"
#elif defined(CONFIG_CAM5200)
# define CARRIER_NAME "Cam5200"
#elif defined(CONFIG_FO300)
# define CARRIER_NAME "FO300"
#else
# error "Unknown carrier board"
# error "UNKNOWN"
#endif
puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
@ -541,7 +543,11 @@ int last_stage_init (void)
#ifdef CONFIG_VIDEO_SM501
#ifdef CONFIG_FO300
#define DISPLAY_WIDTH 800
#else
#define DISPLAY_WIDTH 640
#endif
#define DISPLAY_HEIGHT 480
#ifdef CONFIG_VIDEO_SM501_8BPP
@ -571,6 +577,28 @@ static const SMI_REGS init_regs [] =
{0x80218, 0x000201e9},
{0x80200, 0x00013306},
#else /* panel + CRT */
#ifdef CONFIG_FO300
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x301a0a01},
{0x00054, 0x1},
{0x00040, 0x00021807},
{0x00044, 0x091a0a01},
{0x00054, 0x0},
{0x80000, 0x0f013106},
{0x80004, 0xc428bb17},
{0x8000C, 0x00000000},
{0x80010, 0x0C800C80},
{0x80014, 0x03200000},
{0x80018, 0x01e00000},
{0x8001C, 0x00000000},
{0x80020, 0x01e00320},
{0x80024, 0x042a031f},
{0x80028, 0x0086034a},
{0x8002C, 0x020c01df},
{0x80030, 0x000201ea},
{0x80200, 0x00010000},
#else
{0x00004, 0x0},
{0x00048, 0x00021807},
{0x0004C, 0x091a0a01},
@ -591,6 +619,7 @@ static const SMI_REGS init_regs [] =
{0x8002C, 0x020c01df},
{0x80030, 0x000201e9},
{0x80200, 0x00010000},
#endif /* #ifdef CONFIG_FO300 */
#endif
{0, 0}
};
@ -604,7 +633,7 @@ void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
} else if (line_number == 2) {
#if defined (CONFIG_STK52XX)
strcpy (info, " on a STK52xx carrier board");
@ -612,6 +641,9 @@ void video_get_info_str (int line_number, char *info)
#if defined (CONFIG_TB5200)
strcpy (info, " on a TB5200 carrier board");
#endif
#if defined (CONFIG_FO300)
strcpy (info, " on a FO300 carrier board");
#endif
#endif
}
else {
@ -697,3 +729,33 @@ int board_get_height (void)
}
#endif /* CONFIG_VIDEO_SM501 */
#ifdef CONFIG_BOARD_EARLY_INIT_F
#ifdef CONFIG_FO300
int board_early_init_f (void)
{
vu_long timer3_status;
DECLARE_GLOBAL_DATA_PTR;
/* Configure GPT3 as GPIO input */
*(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
/* Read in TIMER_3 pin status */
timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
/* Force silent console mode if S1 switch
* is in closed position (TIMER_3 pin status is LOW). */
if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
#else
/* Force silent console mode if S1 switch
* is in open position (TIMER_3 pin status is HIGH). */
if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
#endif
gd->flags |= GD_FLG_SILENT;
return 0;
}
#endif
#endif

8
board/trab/trab.c
View File

@ -175,9 +175,11 @@ int misc_init_r (void)
#endif /* CONFIG_VERSION_VARIABLE */
#ifdef CONFIG_AUTO_UPDATE
extern int do_auto_update(void);
/* this has priority over all else */
do_auto_update();
{
extern int do_auto_update(void);
/* this has priority over all else */
do_auto_update();
}
#endif
for (i = 0; i < KEYBD_KEY_NUM; ++i) {

4
common/cmd_mii.c
View File

@ -117,8 +117,6 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
} else {
puts ("Error reading info from the PHY\n");
}
}
} else if (op == 'r') {
@ -503,8 +501,6 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
miiphy_speed (devname, j),
(miiphy_duplex (devname, j) == FULL)
? "FDX" : "HDX");
} else {
puts ("Error reading info from the PHY\n");
}
}
} else if (op[0] == 'r') {

5
common/main.c
View File

@ -937,6 +937,7 @@ int readline (const char *const prompt)
#ifdef CONFIG_CMDLINE_EDITING
char *p = console_buffer;
unsigned int len=MAX_CMDBUF_SIZE;
int rc;
static int initted = 0;
if (!initted) {
@ -946,8 +947,8 @@ int readline (const char *const prompt)
puts (prompt);
cread_line(p, &len);
return len;
rc = cread_line(p, &len);
return rc < 0 ? rc : len;
#else
char *p = console_buffer;
int n = 0; /* buffer index */

18
cpu/i386/sc520.c
View File

@ -31,7 +31,9 @@
#include <common.h>
#include <config.h>
#include <pci.h>
#ifdef CONFIG_SC520_SSI
#include <ssi.h>
#endif
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/ic/sc520.h>
@ -143,7 +145,15 @@ unsigned long init_sc520_dram(void)
u32 dram_present=0;
u32 dram_ctrl;
#ifdef CFG_SDRAM_DRCTMCTL
/* these memory control registers are set up in the assember part,
* in sc520_asm.S, during 'mem_init'. If we muck with them here,
* after we are running a stack in RAM, we have troubles. Besides,
* these refresh and delay values are better ? simply specified
* outright in the include/configs/{cfg} file since the HW designer
* simply dictates it.
*/
#else
int val;
int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
@ -162,6 +172,7 @@ unsigned long init_sc520_dram(void)
} else {
val = 3; /* 62.4us */
}
write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
val = read_mmcr_byte(SC520_DRCTMCTL);
@ -181,13 +192,12 @@ unsigned long init_sc520_dram(void)
val |= 1;
}
write_mmcr_byte(SC520_DRCTMCTL, val);
#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
/* bank 0 enabled */
@ -274,7 +284,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
{
int i;
# if 0
# if 1
printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
#endif
if (irq < 0 || irq > 15) {

54
cpu/i386/sc520_asm.S
View File

@ -113,6 +113,7 @@
.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
@ -459,6 +460,12 @@ emptybank:
incl %edi
loop cleanuplp
#if defined CFG_SDRAM_DRCTMCTL
/* just have your hardware desinger _GIVE_ you what you need here! */
movl $DRCTMCTL, %edi
movb $CFG_SDRAM_DRCTMCTL,%al
movb (%edi), %al
#else
#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
/* set the CAS latency now since it is hard to do
* when we run from the RAM */
@ -470,7 +477,8 @@ emptybank:
#ifdef CFG_SDRAM_CAS_LATENCY_3T
orb $0x10, %al
#endif
movb %al, (%edi)
movb %al, (%edi)
#endif
#endif
movl $DRCCTL, %edi /* DRAM Control register */
movb $0x3,%al /* Load mode register cmd */
@ -528,9 +536,49 @@ bank0: movl (%edi), %eax
shll $22, %eax
movl %eax, %ebx
done: movl %ebx, %eax
done:
movl %ebx, %eax
#if CFG_SDRAM_ECC_ENABLE
/* A nominal memory test: just a byte at each address line */
movl %eax, %ecx
shrl $0x1, %ecx
movl $0x1, %edi
memtest0:
movb $0xa5, (%edi)
cmpb $0xa5, (%edi)
jne out
shrl $1, %ecx
andl %ecx,%ecx
jz set_ecc
shll $1, %edi
jmp memtest0
set_ecc:
/* clear all ram with a memset */
movl %eax, %ecx
xorl %esi, %esi
xorl %edi, %edi
xorl %eax, %eax
shrl $2, %ecx
cld
rep stosl
/* enable read, write buffers */
movb $0x11, %al
movl $DBCTL, %edi
movb %al, (%edi)
/* enable NMI mapping for ECC */
movl $ECCINT, %edi
mov $0x10, %al
movb %al, (%edi)
/* Turn on ECC */
movl $ECCCTL, %edi
mov $0x05, %al
movb %al, (%edi)
#endif
out:
movl %ebx, %eax
jmp *%ebp
#endif /* CONFIG_SC520 */

5
cpu/ppc4xx/405gp_pci.c
View File

@ -315,7 +315,6 @@ void pci_405gp_init(struct pci_controller *hose)
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI_PNP */
@ -563,10 +562,12 @@ void pci_440_init (struct pci_controller *hose)
}
}
void pci_init_board(void)
{
pci_440_init (&ppc440_hose);
#if defined(CONFIG_440SPE)
pcie_setup_hoses();
#endif
}
#endif /* CONFIG_440 & CONFIG_PCI */

592
cpu/ppc4xx/440spe_pcie.c Normal file
View File

@ -0,0 +1,592 @@
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <asm/processor.h>
#include <asm-ppc/io.h>
#include <ppc4xx.h>
#include <common.h>
#include <pci.h>
#include "440spe_pcie.h"
#if defined(CONFIG_440SPE)
#if defined(CONFIG_PCI)
enum {
PTYPE_ENDPOINT = 0x0,
PTYPE_LEGACY_ENDPOINT = 0x1,
PTYPE_ROOT_PORT = 0x4,
LNKW_X1 = 0x1,
LNKW_X4 = 0x4,
LNKW_X8 = 0x8
};
static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 *val) {
*val = 0;
/*
* 440SPE implements only one function per port
*/
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
return 0;
devfn = PCI_BDF(0,0,0);
offset += devfn << 4;
switch (len) {
case 1:
*val = in_8(hose->cfg_data + offset);
break;
case 2:
*val = in_le16((u16 *)(hose->cfg_data + offset));
break;
default:
*val = in_le32((u32 *)(hose->cfg_data + offset));
break;
}
return 0;
}
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
int offset, int len, u32 val) {
/*
* 440SPE implements only one function per port
*/
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
return 0;
devfn = PCI_BDF(0,0,0);
offset += devfn << 4;
switch (len) {
case 1:
out_8(hose->cfg_data + offset, val);
break;
case 2:
out_le16((u16 *)(hose->cfg_data + offset), val);
break;
default:
out_le32((u32 *)(hose->cfg_data + offset), val);
break;
}
return 0;
}
int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val)
{
u32 v;
int rv;
rv = pcie_read_config(hose, dev, offset, 1, &v);
*val = (u8)v;
return rv;
}
int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val)
{
u32 v;
int rv;
rv = pcie_read_config(hose, dev, offset, 2, &v);
*val = (u16)v;
return rv;
}
int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val)
{
u32 v;
int rv;
rv = pcie_read_config(hose, dev, offset, 3, &v);
*val = (u32)v;
return rv;
}
int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val)
{
return pcie_write_config(hose,(u32)dev,offset,1,val);
}
int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val)
{
return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val);
}
int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val)
{
return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val);
}
static void ppc440spe_setup_utl(u32 port) {
volatile void *utl_base = NULL;
/*
* Map UTL registers
*/
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
break;
case 1:
mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
break;
case 2:
mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
break;
}
utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
/*
* Set buffer allocations and then assert VRB and TXE.
*/
out_be32(utl_base + PEUTL_OUTTR, 0x08000000);
out_be32(utl_base + PEUTL_INTR, 0x02000000);
out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_PBBSZ, 0x53000000);
out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
out_be32(utl_base + PEUTL_PCTL, 0x80800066);
}
static int check_error(void)
{
u32 valPE0, valPE1, valPE2;
int err = 0;
/* SDR0_PEGPLLLCT1 reset */
if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) {
printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0);
}
valPE0 = SDR_READ(PESDR0_RCSSET);
valPE1 = SDR_READ(PESDR1_RCSSET);
valPE2 = SDR_READ(PESDR2_RCSSET);
/* SDR0_PExRCSSET rstgu */
if (!(valPE0 & 0x01000000) ||
!(valPE1 & 0x01000000) ||
!(valPE2 & 0x01000000)) {
printf("PCIE: SDR0_PExRCSSET rstgu error\n");
err = -1;
}
/* SDR0_PExRCSSET rstdl */
if (!(valPE0 & 0x00010000) ||
!(valPE1 & 0x00010000) ||
!(valPE2 & 0x00010000)) {
printf("PCIE: SDR0_PExRCSSET rstdl error\n");
err = -1;
}
/* SDR0_PExRCSSET rstpyn */
if ((valPE0 & 0x00001000) ||
(valPE1 & 0x00001000) ||
(valPE2 & 0x00001000)) {
printf("PCIE: SDR0_PExRCSSET rstpyn error\n");
err = -1;
}
/* SDR0_PExRCSSET hldplb */
if ((valPE0 & 0x10000000) ||
(valPE1 & 0x10000000) ||
(valPE2 & 0x10000000)) {
printf("PCIE: SDR0_PExRCSSET hldplb error\n");
err = -1;
}
/* SDR0_PExRCSSET rdy */
if ((valPE0 & 0x00100000) ||
(valPE1 & 0x00100000) ||
(valPE2 & 0x00100000)) {
printf("PCIE: SDR0_PExRCSSET rdy error\n");
err = -1;
}
/* SDR0_PExRCSSET shutdown */
if ((valPE0 & 0x00000100) ||
(valPE1 & 0x00000100) ||
(valPE2 & 0x00000100)) {
printf("PCIE: SDR0_PExRCSSET shutdown error\n");
err = -1;
}
return err;
}
/*
* Initialize PCI Express core
*/
int ppc440spe_init_pcie(void)
{
int time_out = 20;
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
if (check_error())
return -1;
if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
{
printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
SDR_READ(PESDR0_PLLLCT2));
return -1;
}
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
udelay(3);
while(time_out) {
if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
time_out--;
udelay(1);
} else
break;
}
if (!time_out) {
printf("PCIE: VCO output not locked\n");
return -1;
}
return 0;
}
int ppc440spe_init_pcie_rootport(int port)
{
static int core_init;
volatile u32 val = 0;
int attempts;
if (!core_init) {
++core_init;
if (ppc440spe_init_pcie())
return -1;
}
/*
* Initialize various parts of the PCI Express core for our port:
*
* - Set as a root port and enable max width
* (PXIE0 -> X8, PCIE1 and PCIE2 -> X4).
* - Set up UTL configuration.
* - Increase SERDES drive strength to levels suggested by AMCC.
* - De-assert RSTPYN, RSTDL and RSTGU.
*
* NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with
* default setting 0x11310000. The register has new fields,
* PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core
* hang.
*/
switch (port) {
case 0:
SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12);
SDR_WRITE(PESDR0_UTLSET1, 0x21222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR0_UTLSET2, 0x11000000);
SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000);
SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000);
SDR_WRITE(PESDR0_RCSSET,
(SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 1:
SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR1_UTLSET1, 0x21222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR1_UTLSET2, 0x11000000);
SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR1_RCSSET,
(SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
case 2:
SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12);
SDR_WRITE(PESDR2_UTLSET1, 0x21222222);
if (!ppc440spe_revB())
SDR_WRITE(PESDR2_UTLSET2, 0x11000000);
SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000);
SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000);
SDR_WRITE(PESDR2_RCSSET,
(SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12);
break;
}
/*
* Notice: the following delay has critical impact on device
* initialization - if too short (<50ms) the link doesn't get up.
*/
mdelay(100);
switch (port) {
case 0: val = SDR_READ(PESDR0_RCSSTS); break;
case 1: val = SDR_READ(PESDR1_RCSSTS); break;
case 2: val = SDR_READ(PESDR2_RCSSTS); break;
}
if (val & (1 << 20)) {
printf("PCIE%d: PGRST failed %08x\n", port, val);
return -1;
}
/*
* Verify link is up
*/
val = 0;
switch (port)
{
case 0:
val = SDR_READ(PESDR0_LOOP);
break;
case 1:
val = SDR_READ(PESDR1_LOOP);
break;
case 2:
val = SDR_READ(PESDR2_LOOP);
break;
}
if (!(val & 0x00001000)) {
printf("PCIE%d: link is not up.\n", port);
return -1;
}
/*
* Setup UTL registers - but only on revA!
* We use default settings for revB chip.
*/
if (!ppc440spe_revB())
ppc440spe_setup_utl(port);
/*
* We map PCI Express configuration access into the 512MB regions
*
* NOTICE: revB is very strict about PLB real addressess and ranges to
* be mapped for config space; it seems to only work with d_nnnn_nnnn
* range (hangs the core upon config transaction attempts when set
* otherwise) while revA uses c_nnnn_nnnn.
*
* For revA:
* PCIE0: 0xc_4000_0000
* PCIE1: 0xc_8000_0000
* PCIE2: 0xc_c000_0000
*
* For revB:
* PCIE0: 0xd_0000_0000
* PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000
*/
switch (port) {
case 0:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000);
} else {
/* revA */
mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */
break;
case 1:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000);
} else {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */
break;
case 2:
if (ppc440spe_revB()) {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000);
} else {
mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c);
mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000);
}
mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */
break;
}
/*
* Check for VC0 active and assert RDY.
*/
attempts = 10;
switch (port) {
case 0:
while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE0: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20);
break;
case 1:
while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE1: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20);
break;
case 2:
while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) {
if (!(attempts--)) {
printf("PCIE2: VC0 not active\n");
return -1;
}
mdelay(1000);
}
SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20);
break;
}
mdelay(100);
return 0;
}
void ppc440spe_setup_pcie(struct pci_controller *hose, int port)
{
volatile void *mbase = NULL;
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
switch(port) {
case 0:
mbase = (u32 *)CFG_PCIE0_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE0_CFGBASE;
break;
case 1:
mbase = (u32 *)CFG_PCIE1_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE;
break;
case 2:
mbase = (u32 *)CFG_PCIE2_XCFGBASE;
hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE;
break;
}
/*
* Set bus numbers on our root port
*/
if (ppc440spe_revB()) {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
} else {
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
}
/*
* Set up outbound translation to hose->mem_space from PLB
* addresses at an offset of 0xd_0000_0000. We set the low
* bits of the mask to 11 to turn off splitting into 8
* subregions and to enable the outbound translation.
*/
out_le32(mbase + PECFG_POM0LAH, 0x00000000);
out_le32(mbase + PECFG_POM0LAL, (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
switch (port) {
case 0:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE);
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 1:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
case 2:
mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d);
mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE +
port * CFG_PCIE_MEMSIZE));
mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff);
mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2),
~(CFG_PCIE_MEMSIZE - 1) | 3);
break;
}
/* Set up 16GB inbound memory window at 0 */
out_le32(mbase + PCI_BASE_ADDRESS_0, 0);
out_le32(mbase + PCI_BASE_ADDRESS_1, 0);
out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc);
out_le32(mbase + PECFG_BAR0LMPA, 0);
out_le32(mbase + PECFG_PIM0LAL, 0);
out_le32(mbase + PECFG_PIM0LAH, 0);
out_le32(mbase + PECFG_PIMEN, 0x1);
/* Enable I/O, Mem, and Busmaster cycles */
out_le16((u16 *)(mbase + PCI_COMMAND),
in_le16((u16 *)(mbase + PCI_COMMAND)) |
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
#endif /* CONFIG_PCI */
#endif /* CONFIG_440SPE */

162
cpu/ppc4xx/440spe_pcie.h Normal file
View File

@ -0,0 +1,162 @@
/*
* Copyright (c) 2005 Cisco Systems. All rights reserved.
* Roland Dreier <rolandd@cisco.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <ppc4xx.h>
#ifndef __440SPE_PCIE_H
#define __440SPE_PCIE_H
#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);})
#define DCRN_SDR0_CFGADDR 0x00e
#define DCRN_SDR0_CFGDATA 0x00f
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
#define DCRN_PCIE2_BASE 0x140
#define PCIE0 DCRN_PCIE0_BASE
#define PCIE1 DCRN_PCIE1_BASE
#define PCIE2 DCRN_PCIE2_BASE
#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
/*
* System DCRs (SDRs)
*/
#define PESDR0_PLLLCT1 0x03a0
#define PESDR0_PLLLCT2 0x03a1
#define PESDR0_PLLLCT3 0x03a2
#define PESDR0_UTLSET1 0x0300
#define PESDR0_UTLSET2 0x0301
#define PESDR0_DLPSET 0x0302
#define PESDR0_LOOP 0x0303
#define PESDR0_RCSSET 0x0304
#define PESDR0_RCSSTS 0x0305
#define PESDR0_HSSL0SET1 0x0306
#define PESDR0_HSSL0SET2 0x0307
#define PESDR0_HSSL0STS 0x0308
#define PESDR0_HSSL1SET1 0x0309
#define PESDR0_HSSL1SET2 0x030a
#define PESDR0_HSSL1STS 0x030b
#define PESDR0_HSSL2SET1 0x030c
#define PESDR0_HSSL2SET2 0x030d
#define PESDR0_HSSL2STS 0x030e
#define PESDR0_HSSL3SET1 0x030f
#define PESDR0_HSSL3SET2 0x0310
#define PESDR0_HSSL3STS 0x0311
#define PESDR0_HSSL4SET1 0x0312
#define PESDR0_HSSL4SET2 0x0313
#define PESDR0_HSSL4STS 0x0314
#define PESDR0_HSSL5SET1 0x0315
#define PESDR0_HSSL5SET2 0x0316
#define PESDR0_HSSL5STS 0x0317
#define PESDR0_HSSL6SET1 0x0318
#define PESDR0_HSSL6SET2 0x0319
#define PESDR0_HSSL6STS 0x031a
#define PESDR0_HSSL7SET1 0x031b
#define PESDR0_HSSL7SET2 0x031c
#define PESDR0_HSSL7STS 0x031d
#define PESDR0_HSSCTLSET 0x031e
#define PESDR0_LANE_ABCD 0x031f
#define PESDR0_LANE_EFGH 0x0320
#define PESDR1_UTLSET1 0x0340
#define PESDR1_UTLSET2 0x0341
#define PESDR1_DLPSET 0x0342
#define PESDR1_LOOP 0x0343
#define PESDR1_RCSSET 0x0344
#define PESDR1_RCSSTS 0x0345
#define PESDR1_HSSL0SET1 0x0346
#define PESDR1_HSSL0SET2 0x0347
#define PESDR1_HSSL0STS 0x0348
#define PESDR1_HSSL1SET1 0x0349
#define PESDR1_HSSL1SET2 0x034a
#define PESDR1_HSSL1STS 0x034b
#define PESDR1_HSSL2SET1 0x034c
#define PESDR1_HSSL2SET2 0x034d
#define PESDR1_HSSL2STS 0x034e
#define PESDR1_HSSL3SET1 0x034f
#define PESDR1_HSSL3SET2 0x0350
#define PESDR1_HSSL3STS 0x0351
#define PESDR1_HSSCTLSET 0x0352
#define PESDR1_LANE_ABCD 0x0353
#define PESDR2_UTLSET1 0x0370
#define PESDR2_UTLSET2 0x0371
#define PESDR2_DLPSET 0x0372
#define PESDR2_LOOP 0x0373
#define PESDR2_RCSSET 0x0374
#define PESDR2_RCSSTS 0x0375
#define PESDR2_HSSL0SET1 0x0376
#define PESDR2_HSSL0SET2 0x0377
#define PESDR2_HSSL0STS 0x0378
#define PESDR2_HSSL1SET1 0x0379
#define PESDR2_HSSL1SET2 0x037a
#define PESDR2_HSSL1STS 0x037b
#define PESDR2_HSSL2SET1 0x037c
#define PESDR2_HSSL2SET2 0x037d
#define PESDR2_HSSL2STS 0x037e
#define PESDR2_HSSL3SET1 0x037f
#define PESDR2_HSSL3SET2 0x0380
#define PESDR2_HSSL3STS 0x0381
#define PESDR2_HSSCTLSET 0x0382
#define PESDR2_LANE_ABCD 0x0383
/*
* UTL register offsets
*/
#define PEUTL_PBBSZ 0x20
#define PEUTL_OPDBSZ 0x68
#define PEUTL_IPHBSZ 0x70
#define PEUTL_IPDBSZ 0x78
#define PEUTL_OUTTR 0x90
#define PEUTL_INTR 0x98
#define PEUTL_PCTL 0xa0
#define PEUTL_RCIRQEN 0xb8
/*
* Config space register offsets
*/
#define PECFG_BAR0LMPA 0x210
#define PECFG_BAR0HMPA 0x214
#define PECFG_PIMEN 0x33c
#define PECFG_PIM0LAL 0x340
#define PECFG_PIM0LAH 0x344
#define PECFG_POM0LAL 0x380
#define PECFG_POM0LAH 0x384
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mfdcr(DCRN_SDR0_CFGDATA);})
#define SDR_WRITE(offset, data) ({\
mtdcr(DCRN_SDR0_CFGADDR, offset); \
mtdcr(DCRN_SDR0_CFGDATA,data);})
int ppc440spe_init_pcie(void);
int ppc440spe_init_pcie_rootport(int port);
void yucca_setup_pcie_fpga_rootpoint(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
int yucca_pcie_card_present(int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);
#endif /* __440SPE_PCIE_H */

3
cpu/ppc4xx/Makefile
View File

@ -31,7 +31,8 @@ COBJS = 405gp_pci.o 4xx_enet.o \
bedbug_405.o commproc.o \
cpu.o cpu_init.o i2c.o interrupts.o \
miiphy.o sdram.o serial.o \
spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o
spd_sdram.o speed.o traps.o usb_ohci.o usbdev.o \
440spe_pcie.o
OBJS = $(AOBJS) $(COBJS)

11
cpu/ppc4xx/cpu.c
View File

@ -315,6 +315,17 @@ int checkcpu (void)
return 0;
}
#if defined (CONFIG_440SPE)
int ppc440spe_revB() {
unsigned int pvr;
pvr = get_pvr();
if (pvr == PVR_440SPe_RB)
return 1;
else
return 0;
}
#endif
/* ------------------------------------------------------------------------- */

16
cpu/ppc4xx/start.S
View File

@ -315,7 +315,23 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
/*----------------------------------------------------------------*/
/* TLB entry setup -- step thru tlbtab */
/*----------------------------------------------------------------*/
#if defined(CONFIG_440SPE)
/*----------------------------------------------------------------*/
/* We have different TLB tables for revA and rev B of 440SPe */
/*----------------------------------------------------------------*/
mfspr r1, PVR
lis r0,0x5342
ori r0,r0,0x1891
cmpw r7,r1,r0
bne r7,..revA
bl tlbtabB
b ..goon
..revA:
bl tlbtabA
..goon:
#else
bl tlbtab /* Get tlbtab pointer */
#endif
mr r5,r0
li r1,0x003f /* 64 TLB entries max */
mtctr r1

3
drivers/dm9000x.c
View File

@ -436,6 +436,9 @@ eth_rx(void)
u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
u16 RxStatus, RxLen = 0;
u32 tmplen, i;
#ifdef CONFIG_DM9000_USE_32BIT
u32 tmpdata;
#endif
/* Check packet ready or not */
DM9000_ior(DM9000_MRCMDX); /* Dummy read */

6
include/common.h
View File

@ -252,6 +252,9 @@ void pciinfo (int, int);
void pci_master_init (struct pci_controller *);
# endif
int is_pci_host (struct pci_controller *);
#if defined(CONFIG_440SPE)
void pcie_setup_hoses(void);
#endif
#endif
int misc_init_f (void);
@ -474,6 +477,7 @@ void get_sys_info ( sys_info_t * );
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
unsigned long determine_pci_clock_per(void);
int ppc440spe_revB(void);
# endif
# else
typedef PPC405_SYS_INFO sys_info_t;
@ -611,7 +615,7 @@ void show_boot_progress (int status);
#endif
#ifdef CONFIG_INIT_CRITICAL
#error CONFIG_INIT_CRITICAL is depracted!
#error CONFIG_INIT_CRITICAL is deprecated!
#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
#endif

55
include/configs/TQM5200.h
View File

@ -37,7 +37,8 @@
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
#ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
/* On a Cameron or on a FO300 board or ... */
#if !defined(CONFIG_CAM5200) && !defined(CONFIG_FO300)
#define CONFIG_STK52XX 1 /* ... on a STK52XX board */
#endif
@ -58,6 +59,20 @@
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#ifdef CONFIG_FO300
#define CFG_DEVICE_NULLDEV 1 /* enable null device */
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* used to detect S1 switch position */
#if 0
#define FO300_SILENT_CONSOLE_WHEN_S1_CLOSED 1 /* silent console on PSC1 when S1 */
/* switch is closed */
#endif
#undef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED /* silent console on PSC1 when S1 */
/* switch is open */
#endif /* CONFIG_FO300 */
#ifdef CONFIG_STK52XX
#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
@ -105,12 +120,18 @@
#define CONFIG_VIDEO_SM501_32BPP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#ifndef CONFIG_FO300
#define CONFIG_CONSOLE_EXTRA_INFO
#else
#define CONFIG_VIDEO_BMP_LOGO
#endif
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN
#define CFG_CONSOLE_IS_IN_ENV
#endif
#endif /* #ifndef CONFIG_TQM5200S */
#ifdef CONFIG_VIDEO
#define ADD_BMP_CMD CFG_CMD_BMP
@ -124,7 +145,7 @@
#define CONFIG_ISO_PARTITION
/* USB */
#ifdef CONFIG_STK52XX
#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
#define CONFIG_USB_OHCI
#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
#define CONFIG_USB_STORAGE
@ -148,7 +169,7 @@
#endif
/* IDE */
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300)
#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
#else
#define ADD_IDE_CMD 0
@ -224,6 +245,12 @@
"erase FC000000 FC03FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC03FFFF\0"
#elif defined (CONFIG_FO300)
# define ENV_UPDT \
"update=protect off FC000000 FC05FFFF;" \
"erase FC000000 FC05FFFF;" \
"cp.b 200000 FC000000 ${filesize};" \
"protect on FC000000 FC05FFFF\0"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
@ -378,6 +405,13 @@
"2m(initrd)," \
"8m(misc)," \
"16m(big-fs)"
#elif defined (CONFIG_FO300)
# define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
"1408k(kernel)," \
"2m(initrd)," \
"4m(small-fs)," \
"8m(misc)," \
"16m(big-fs)"
#else
# error "Unknown Carrier Board"
#endif /* CONFIG_STK52XX */
@ -450,15 +484,18 @@
* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
* Use for REV200 STK52XX boards. Do not use with REV100 modules
* (because, there I2C1 is used as I2C bus)
* Use for REV200 STK52XX boards and FO300 boards. Do not use
* with REV100 modules (because, there I2C1 is used as I2C bus)
* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
* 000 -> All PSC2 pins are GIOPs
* 001 -> CAN1/2 on PSC2 pins
* Use for REV100 STK52xx boards
* 01x -> Use AC97
* use PSC3: Bits 20-23 (mask: 0x00000f00)
* 1100 -> UART/SPI (on FO300 board)
* use PSC6:
* on STK52xx:
* on STK52xx and FO300:
* use as UART. Pins PSC6_0 to PSC6_3 are used.
* Bits 9:11 (mask: 0x00700000):
* 101 -> PSC6 : Extended POST test is not available
@ -480,6 +517,8 @@
# define CFG_GPS_PORT_CONFIG 0x91500004
# endif
# endif
#elif defined (CONFIG_FO300)
# define CFG_GPS_PORT_CONFIG 0x91502c24
#else /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG 0x81000004
#endif

19
include/configs/TQM834x.h
View File

@ -422,9 +422,9 @@ extern int tqm834x_num_flash_banks;
#define CFG_SICRL SICRL_LDP_A
/* i-cache and d-cache disabled */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 0x000000000
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
/* DDR 0 - 512M */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@ -437,12 +437,21 @@ extern int tqm834x_num_flash_banks;
#define CFG_IBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
/* PCI */
#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#ifdef CONFIG_PCI
#define CFG_IBAT3L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT3U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT4L (CFG_PCI1_MEM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CFG_IBAT4U (CFG_PCI1_MEM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT5L (CFG_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U (CFG_PCI1_IO_BASE + 0x10000000 | BATU_BL_16M | BATU_VS | BATU_VP)
#else
#define CFG_IBAT3L (0)
#define CFG_IBAT3U (0)
#define CFG_IBAT4L (0)
#define CFG_IBAT4U (0)
#define CFG_IBAT5L (0)
#define CFG_IBAT5U (0)
#endif
/* IMMRBAR */
#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)

4
include/configs/TQM85xx.h
View File

@ -424,7 +424,7 @@
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
@ -449,7 +449,7 @@
"run nfsargs addip addcons;bootm\0" \
"rootpath=/opt/eldk/ppc_85xx\0" \
"kernel_addr=FE000000\0" \
"ramdisk_addr=FE100000\0" \
"ramdisk_addr=FE180000\0" \
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \

14
include/configs/bamboo.h
View File

@ -310,11 +310,11 @@
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
CFG_CMD_EEPROM | \
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -358,13 +358,11 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING
#ifdef CONFIG_CMDLINE_EDITING
#undef CONFIG_AUTO_COMPLETE
#else
#define CONFIG_AUTO_COMPLETE
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff

3
include/configs/bubinga.h
View File

@ -200,8 +200,9 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */

12
include/configs/ebony.h
View File

@ -143,7 +143,13 @@
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@ -205,6 +211,7 @@
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -243,8 +250,9 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */

14
include/configs/luan.h
View File

@ -145,6 +145,13 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo"
@ -215,6 +222,7 @@
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -253,6 +261,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

9
include/configs/mcc200.h
View File

@ -51,15 +51,20 @@
* To select console on the one of 8 external UARTs,
* define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
* or as 5, 6, 7, or 8 for the second Quad UART.
* COM11, COM12, COM13, COM14 are located on the second Quad UART.
*
* CONFIG_PSC_CONSOLE must be undefined in this case.
*/
/* #define CONFIG_QUART_CONSOLE 1 */ /* console is on UART1 of QUART1 */
#ifdef CONFIG_CONSOLE_COM12
#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
#else
#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
#endif
/*
* To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
* and undefine CONFIG_QUART_CONSOLE.
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
/*#define CONFIG_PSC_CONSOLE 1 */ /* console is on PSC1 */
#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
#error "Select only one console device!"
#endif

19
include/configs/ocotea.h
View File

@ -158,7 +158,13 @@
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@ -219,6 +225,9 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
#define CONFIG_PHY_RESET_DELAY 1000
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_ASKENV | \
@ -226,6 +235,7 @@
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -264,15 +274,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

21
include/configs/walnut.h
View File

@ -90,6 +90,11 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 1 /* PHY address */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* needed for NetConsole */
#define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
@ -97,6 +102,7 @@
CFG_CMD_DATE | \
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
@ -156,16 +162,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* needed for NetConsole */
/*-----------------------------------------------------------------------
* I2C stuff
*-----------------------------------------------------------------------
@ -175,6 +177,13 @@
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

7
include/configs/yellowstone.h
View File

@ -229,6 +229,7 @@
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -265,6 +266,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

7
include/configs/yosemite.h
View File

@ -231,6 +231,7 @@
CFG_CMD_DHCP | \
CFG_CMD_DIAG | \
CFG_CMD_ELF | \
CFG_CMD_EEPROM | \
CFG_CMD_I2C | \
CFG_CMD_IRQ | \
CFG_CMD_MII | \
@ -272,6 +273,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------

38
include/configs/yucca.h
View File

@ -31,9 +31,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
/*-----------------------------------------------------------------------
* High Level Configuration Options
*----------------------------------------------------------------------*/
@ -63,17 +60,20 @@
#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 0x90000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE2 0xa0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE3 0xb0000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
#define CFG_PCI_TARGBASE 0x80000000 /*PCIaddr mapped to CFG_PCI_MEMBASE*/
#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
/* #define CFG_PCI_BASE_IO 0xB8000000 */ /* internal PCI I-O */
/* #define CFG_PCI_BASE_REGS 0xBEC00000 */ /* internal PCI regs */
/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */ /* internal PCI regs */
#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
#define CFG_PCIE_MEMSIZE 0x01000000
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
#define CFG_PCIE0_CFGBASE 0xc0000000
#define CFG_PCIE0_XCFGBASE 0xc0000400
#define CFG_PCIE1_CFGBASE 0xc0001000
#define CFG_PCIE1_XCFGBASE 0xc0001400
#define CFG_PCIE2_CFGBASE 0xc0002000
#define CFG_PCIE2_XCFGBASE 0xc0002400
/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
@ -220,6 +220,9 @@
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* needed for NetConsole */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
@ -245,6 +248,12 @@
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
@ -292,6 +301,7 @@
*/
/* Support for Intel 82557/82559/82559ER chips. */
#define CONFIG_EEPRO100
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
@ -506,8 +516,8 @@
#define FPGA_REG1C_PE1_WAKE 0x0040
#define FPGA_REG1C_PE2_WAKE 0x0020
#define FPGA_REG1C_PE0_PERST 0x0010
#define FPGA_REG1C_PE1_PERST 0x0080
#define FPGA_REG1C_PE2_PERST 0x0040
#define FPGA_REG1C_PE1_PERST 0x0008
#define FPGA_REG1C_PE2_PERST 0x0004
/*----------------------------------------------------------------------------+
| Defines

8
include/fat.h
View File

@ -175,15 +175,19 @@ typedef struct dir_slot {
__u8 name11_12[4]; /* Last 2 characters in name */
} dir_slot;
/* Private filesystem parameters */
/* Private filesystem parameters
*
* Note: FAT buffer has to be 32 bit aligned
* (see FAT32 accesses)
*/
typedef struct {
__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatsize; /* Size of FAT in bits */
__u16 fatlength; /* Length of FAT in sectors */
__u16 fat_sect; /* Starting sector of the FAT */
__u16 rootdir_sect; /* Start sector of root directory */
__u16 clust_size; /* Size of clusters in sectors */
short data_begin; /* The sector of the first cluster, can be negative */
__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
int fatbufnum; /* Used by get_fatent, init to -1 */
} fsdata;

10
include/mpc5xxx.h
View File

@ -235,20 +235,30 @@
/* General Purpose Timers registers */
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C)
#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10)
#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14)
#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C)
#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20)
#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24)
#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C)
#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30)
#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34)
#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C)
#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40)
#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44)
#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C)
#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50)
#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C)
#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54)
#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60)
#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64)
#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C)
#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70)
#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74)
#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C)
#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8)
#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78)

2
net/tftp.c
View File

@ -225,7 +225,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
if (TftpBlock == 0) {
TftpBlockWrap++;
TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20);
printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
} else {
if (((TftpBlock - 1) % 10) == 0) {
putc ('#');