Merge with git+ssh://fifi/home/wd/git/u-boot/master
This commit is contained in:
Wolfgang Denk
commit
4bfb632077
15
CHANGELOG
15
CHANGELOG
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@ -2,6 +2,21 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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* Update for SC520 board.
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Patch by David Updegraff, 02 Dec 2005
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* Fixed common.h spelling error.
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Patch by Cory Tusar, 30 Nov 2005
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* Fix typo.
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Patch by Andreas Engel, 28 Nov 2005
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* Fix fatload command on FAT32 formatted partitions.
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Patch by Joachim Jaeger, 18 Nov 2005
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* Fix drivers/dm9000.c when configured in 32 bit mode.
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Patch by Eric Benard, 17 Nov 2005
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* Cleanup debug code for yucca board.
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* MCC200: restrict addressable flash space to 32 MB
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@ -31,7 +31,9 @@
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#include <common.h>
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#include <config.h>
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#include <pci.h>
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#ifdef CONFIG_SC520_SSI
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#include <ssi.h>
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#endif
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/ic/sc520.h>
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@ -143,7 +145,15 @@ unsigned long init_sc520_dram(void)
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u32 dram_present=0;
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u32 dram_ctrl;
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#ifdef CFG_SDRAM_DRCTMCTL
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/* these memory control registers are set up in the assember part,
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* in sc520_asm.S, during 'mem_init'. If we muck with them here,
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* after we are running a stack in RAM, we have troubles. Besides,
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* these refresh and delay values are better ? simply specified
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* outright in the include/configs/{cfg} file since the HW designer
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* simply dictates it.
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*/
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#else
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int val;
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int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
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@ -162,6 +172,7 @@ unsigned long init_sc520_dram(void)
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} else {
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val = 3; /* 62.4us */
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}
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write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
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val = read_mmcr_byte(SC520_DRCTMCTL);
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@ -181,13 +192,12 @@ unsigned long init_sc520_dram(void)
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val |= 1;
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}
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write_mmcr_byte(SC520_DRCTMCTL, val);
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#endif
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/* We read-back the configuration of the dram
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* controller that the assembly code wrote */
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dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
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bd->bi_dram[0].start = 0;
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if (dram_ctrl & 0x80) {
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/* bank 0 enabled */
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@ -274,7 +284,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
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{
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int i;
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# if 0
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# if 1
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printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
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#endif
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if (irq < 0 || irq > 15) {
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@ -113,6 +113,7 @@
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.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
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.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
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.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
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.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
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.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
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.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
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@ -459,6 +460,12 @@ emptybank:
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incl %edi
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loop cleanuplp
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#if defined CFG_SDRAM_DRCTMCTL
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/* just have your hardware desinger _GIVE_ you what you need here! */
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movl $DRCTMCTL, %edi
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movb $CFG_SDRAM_DRCTMCTL,%al
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movb (%edi), %al
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#else
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#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
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/* set the CAS latency now since it is hard to do
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* when we run from the RAM */
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@ -470,7 +477,8 @@ emptybank:
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#ifdef CFG_SDRAM_CAS_LATENCY_3T
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orb $0x10, %al
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#endif
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movb %al, (%edi)
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movb %al, (%edi)
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#endif
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#endif
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movl $DRCCTL, %edi /* DRAM Control register */
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movb $0x3,%al /* Load mode register cmd */
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@ -528,9 +536,49 @@ bank0: movl (%edi), %eax
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shll $22, %eax
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movl %eax, %ebx
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done: movl %ebx, %eax
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done:
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movl %ebx, %eax
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#if CFG_SDRAM_ECC_ENABLE
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/* A nominal memory test: just a byte at each address line */
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movl %eax, %ecx
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shrl $0x1, %ecx
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movl $0x1, %edi
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memtest0:
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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jne out
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shrl $1, %ecx
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andl %ecx,%ecx
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jz set_ecc
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shll $1, %edi
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jmp memtest0
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set_ecc:
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/* clear all ram with a memset */
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movl %eax, %ecx
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xorl %esi, %esi
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xorl %edi, %edi
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xorl %eax, %eax
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shrl $2, %ecx
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cld
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rep stosl
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/* enable read, write buffers */
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movb $0x11, %al
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movl $DBCTL, %edi
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movb %al, (%edi)
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/* enable NMI mapping for ECC */
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movl $ECCINT, %edi
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mov $0x10, %al
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movb %al, (%edi)
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/* Turn on ECC */
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movl $ECCCTL, %edi
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mov $0x05, %al
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movb %al, (%edi)
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#endif
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out:
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movl %ebx, %eax
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jmp *%ebp
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#endif /* CONFIG_SC520 */
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@ -436,6 +436,9 @@ eth_rx(void)
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u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
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u16 RxStatus, RxLen = 0;
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u32 tmplen, i;
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#ifdef CONFIG_DM9000_USE_32BIT
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u32 tmpdata;
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#endif
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/* Check packet ready or not */
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DM9000_ior(DM9000_MRCMDX); /* Dummy read */
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@ -603,7 +603,7 @@ void show_boot_progress (int status);
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#endif
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#ifdef CONFIG_INIT_CRITICAL
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#error CONFIG_INIT_CRITICAL is depracted!
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#error CONFIG_INIT_CRITICAL is deprecated!
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#error Read section CONFIG_SKIP_LOWLEVEL_INIT in README.
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#endif
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@ -175,15 +175,19 @@ typedef struct dir_slot {
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__u8 name11_12[4]; /* Last 2 characters in name */
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} dir_slot;
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/* Private filesystem parameters */
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/* Private filesystem parameters
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*
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* Note: FAT buffer has to be 32 bit aligned
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* (see FAT32 accesses)
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*/
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typedef struct {
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__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
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int fatsize; /* Size of FAT in bits */
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__u16 fatlength; /* Length of FAT in sectors */
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__u16 fat_sect; /* Starting sector of the FAT */
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__u16 rootdir_sect; /* Start sector of root directory */
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__u16 clust_size; /* Size of clusters in sectors */
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short data_begin; /* The sector of the first cluster, can be negative */
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__u8 fatbuf[FATBUFSIZE]; /* Current FAT buffer */
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int fatbufnum; /* Used by get_fatent, init to -1 */
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} fsdata;
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@ -225,7 +225,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
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if (TftpBlock == 0) {
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TftpBlockWrap++;
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TftpBlockWrapOffset += TFTP_BLOCK_SIZE * TFTP_SEQUENCE_SIZE;
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printf ("\n\t %lu MB reveived\n\t ", TftpBlockWrapOffset>>20);
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printf ("\n\t %lu MB received\n\t ", TftpBlockWrapOffset>>20);
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} else {
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if (((TftpBlock - 1) % 10) == 0) {
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putc ('#');
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