ARM: initial support for TI DaVinci SoCs
This commit adds minimal support for the DaVinci DM365 SoCs from Texas Instruments. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Antony Pavlov
Sascha Hauer
parent
74f0803993
commit
4c1aa10d0f
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@ -54,6 +54,10 @@ config ARCH_CLPS711X
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select GPIOLIB
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select MFD_SYSCON
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config ARCH_DAVINCI
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bool "TI Davinci"
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select CPU_ARM926T
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config ARCH_EP93XX
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bool "Cirrus Logic EP93xx"
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select CPU_ARM920T
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@ -188,6 +192,7 @@ source arch/arm/cpu/Kconfig
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source arch/arm/mach-at91/Kconfig
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source arch/arm/mach-bcm2835/Kconfig
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source arch/arm/mach-clps711x/Kconfig
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source arch/arm/mach-davinci/Kconfig
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source arch/arm/mach-ep93xx/Kconfig
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source arch/arm/mach-highbank/Kconfig
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source arch/arm/mach-imx/Kconfig
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@ -54,6 +54,7 @@ AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2)
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machine-$(CONFIG_ARCH_AT91) := at91
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machine-$(CONFIG_ARCH_BCM2835) := bcm2835
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machine-$(CONFIG_ARCH_CLPS711X) := clps711x
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machine-$(CONFIG_ARCH_DAVINCI) := davinci
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machine-$(CONFIG_ARCH_EP93XX) := ep93xx
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machine-$(CONFIG_ARCH_HIGHBANK) := highbank
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machine-$(CONFIG_ARCH_IMX) := imx
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@ -0,0 +1,7 @@
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if ARCH_DAVINCI
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config ARCH_TEXT_BASE
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hex
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default 0x82000000
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endif
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@ -0,0 +1 @@
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obj-y += time.o
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@ -0,0 +1,29 @@
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/*
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* Hardware definitions common to all DaVinci family processors
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*
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* Author: Kevin Hilman, Deep Root Systems, LLC
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*
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* 2007 (c) Deep Root Systems, LLC. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/memory.h>
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/*
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* Before you add anything to this file:
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*
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* This header is for defines common to ALL DaVinci family chips.
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* Anything that is chip specific should go in <chipname>.h,
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* and the chip/board init code should then explicitly include
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* <chipname>.h
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*/
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/*
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* I/O mapping
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*/
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#define IO_PHYS UL(0x01c00000)
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#endif /* __ASM_ARCH_HARDWARE_H */
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@ -0,0 +1,20 @@
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/*
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* DaVinci serial device definitions
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_SERIAL_H
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#define __ASM_ARCH_SERIAL_H
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#include <mach/hardware.h>
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#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
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#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
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#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
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#endif /* __ASM_ARCH_SERIAL_H */
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@ -0,0 +1,18 @@
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/*
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* Local header file for DaVinci time code.
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ARCH_ARM_MACH_DAVINCI_TIME_H
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#define __ARCH_ARM_MACH_DAVINCI_TIME_H
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#include <mach/hardware.h>
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#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
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#endif /* __ARCH_ARM_MACH_DAVINCI_TIME_H */
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@ -0,0 +1,95 @@
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/*
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* DaVinci timer subsystem
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <common.h>
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#include <io.h>
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#include <mach/time.h>
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/* Timer register offsets */
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#define PID12 0x0
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#define TIM12 0x10
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#define TIM34 0x14
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#define PRD12 0x18
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#define PRD34 0x1c
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#define TCR 0x20
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#define TGCR 0x24
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#define WDTCR 0x28
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/* Timer register bitfields */
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#define TCR_ENAMODE_DISABLE 0x0
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#define TCR_ENAMODE_ONESHOT 0x1
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#define TCR_ENAMODE_PERIODIC 0x2
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#define TCR_ENAMODE_MASK 0x3
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#define TGCR_TIMMODE_SHIFT 2
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#define TGCR_TIMMODE_64BIT_GP 0x0
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#define TGCR_TIMMODE_32BIT_UNCHAINED 0x1
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#define TGCR_TIMMODE_64BIT_WDOG 0x2
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#define TGCR_TIMMODE_32BIT_CHAINED 0x3
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#define TGCR_TIM12RS_SHIFT 0
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#define TGCR_TIM34RS_SHIFT 1
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#define TGCR_RESET 0x0
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#define TGCR_UNRESET 0x1
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#define TGCR_RESET_MASK 0x3
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#define WDTCR_WDEN_SHIFT 14
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#define WDTCR_WDEN_DISABLE 0x0
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#define WDTCR_WDEN_ENABLE 0x1
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#define WDTCR_WDKEY_SHIFT 16
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#define WDTCR_WDKEY_SEQ0 0xa5c6
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#define WDTCR_WDKEY_SEQ1 0xda7e
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/* reset board using watchdog timer */
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void __noreturn reset_cpu(ulong addr)
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{
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u32 tgcr, wdtcr;
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void __iomem *base;
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base = IOMEM(DAVINCI_WDOG_BASE);
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/* disable, internal clock source */
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__raw_writel(0, base + TCR);
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/* reset timer, set mode to 64-bit watchdog, and unreset */
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tgcr = 0;
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__raw_writel(tgcr, base + TGCR);
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tgcr = TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT;
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tgcr |= (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
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(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
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__raw_writel(tgcr, base + TGCR);
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/* clear counter and period regs */
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__raw_writel(0, base + TIM12);
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__raw_writel(0, base + TIM34);
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__raw_writel(0, base + PRD12);
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__raw_writel(0, base + PRD34);
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/* put watchdog in pre-active state */
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wdtcr = __raw_readl(base + WDTCR);
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wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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__raw_writel(wdtcr, base + WDTCR);
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/* put watchdog in active state */
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wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
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(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
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__raw_writel(wdtcr, base + WDTCR);
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/* write an invalid value to the WDKEY field to trigger
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* a watchdog reset */
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wdtcr = 0x00004000;
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__raw_writel(wdtcr, base + WDTCR);
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unreachable();
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}
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EXPORT_SYMBOL(reset_cpu);
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