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saving added docu

This commit is contained in:
Juergen Beisert 2007-11-05 14:39:07 +01:00
parent a26f5e995e
commit 4cd877a840
14 changed files with 397 additions and 101 deletions
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2
Documentation/developers_manual.dox
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@ -16,5 +16,7 @@ Hints and tips for simply adapting UBootv2
Various themes:
- @subpage how_mount_works
- @subpage boot_preparation
- @subpage uboot_simul
*/

15
Documentation/users_manual.dox
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@ -1,7 +1,20 @@
/** @page users_manual User's Manual
FIXME: Hints and tips for simply using UBootv2
<!--
This manual should help the user to manage his target with the new U-Boot
look and fell. Many things are new in v2, but some old fashion feelings
are still present.
First of all, you will recognise the U-Boot v2 is much faster than its
precedessor. Booting up your target needs less time, as U-Boot's v2 core is
shrinked down.
-->
Who should read this part?
Mostly everyone. The user needs it to find help for his daily work to manage
his targets. The developer to find out all the new features that make his
work easier.
- @subpage shell_notes
- @subpage readline_parser

2
Doxyfile
View File

@ -418,7 +418,7 @@ WARNINGS = YES
# for undocumented members. If EXTRACT_ALL is set to YES then this flag will
# automatically be disabled.
WARN_IF_UNDOCUMENTED = YES
WARN_IF_UNDOCUMENTED = NO
# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for
# potential errors in the documentation, such as not documenting some

29
arch/architecture.dox
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@ -1,6 +1,33 @@
/** @page dev_architecture Integrate a new architecture (ARCH)
Friesel
@section linker_scripts Rules for the generic Linker Script File
Never include an object file by name directly! Linker Script Files defines the
layout, not the content. Content is defined in objecfiles instead.
Don't rely on the given object file order to create your binary U-Boot v2! This
may work, but is not relyable in all cases (and its a very bad style)!
For the special case some layout contraints exists, use specific section
naming instead. Refer @ref reset_code how to define this specific section.
@section reset_code Bring it up: The Reset Code
The way a CPU wakes up after reset is very specific to its architecture.
For example the ARM architecture starts its reset code at address 0x0000000,
the x86 architecture at 0x000FFFF0, PowerPC at 0x00000100 or 0xFFFFF100.
So for the special reset code on all architectures it must be located at
architecture specific locations within the binary U-Boot image.
All reset code uses section ".text_entry" for its localisation within the
binary U-Boot image. Its up to the linker script file to use this section name
to find the right place in whatever environment and U-Boot sizes.
@code
.section ".text_entry","ax"
@endcode
*/

110
arch/arm/cpu/cpu.c
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@ -1,7 +1,37 @@
/*
* cpu.c - A few helper functions for ARM
*
* Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/**
* @file
* @brief A few helper functions for ARM
*/
#include <common.h>
#include <command.h>
/* read co-processor 15, register #1 (control register) */
/**
* Read special processor register
* @return co-processor 15, register #1 (control register)
*/
static unsigned long read_p15_c1 (void)
{
unsigned long value;
@ -18,7 +48,12 @@ static unsigned long read_p15_c1 (void)
return value;
}
/* write to co-processor 15, register #1 (control register) */
/**
*
* Write special processor register
* @param[in] value to write
* @return to co-processor 15, register #1 (control register)
*/
static void write_p15_c1 (unsigned long value)
{
#ifdef MMU_DEBUG
@ -33,23 +68,38 @@ static void write_p15_c1 (unsigned long value)
read_p15_c1 ();
}
/**
* Wait for co prozessor (waste time)
* Co processor seems to need some delay between accesses
*/
static void cp_delay (void)
{
volatile int i;
/* copro seems to need some delay between reading and writing */
for (i = 0; i < 100; i++);
for (i = 0; i < 100; i++) /* FIXME does it work as expected?? */
;
}
#define C1_MMU (1<<0) /* mmu off/on */
#define C1_ALIGN (1<<1) /* alignment faults off/on */
#define C1_DC (1<<2) /* dcache off/on */
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
#define C1_SYS_PROT (1<<8) /* system protection */
#define C1_ROM_PROT (1<<9) /* ROM protection */
#define C1_IC (1<<12) /* icache off/on */
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
/** mmu off/on */
#define C1_MMU (1<<0)
/** alignment faults off/on */
#define C1_ALIGN (1<<1)
/** dcache off/on */
#define C1_DC (1<<2)
/** big endian off/on */
#define C1_BIG_ENDIAN (1<<7)
/** system protection */
#define C1_SYS_PROT (1<<8)
/** ROM protection */
#define C1_ROM_PROT (1<<9)
/** icache off/on */
#define C1_IC (1<<12)
/** location of vectors: low/high addresses */
#define C1_HIGH_VECTORS (1<<13)
/**
* Enable processor's instruction cache
*/
void icache_enable (void)
{
ulong reg;
@ -59,6 +109,9 @@ void icache_enable (void)
write_p15_c1 (reg | C1_IC);
}
/**
* Disable processor's instruction cache
*/
void icache_disable (void)
{
ulong reg;
@ -68,30 +121,39 @@ void icache_disable (void)
write_p15_c1 (reg & ~C1_IC);
}
/**
* Detect processor's current instruction cache status
* @return 0=disabled, 1=enabled
*/
int icache_status (void)
{
return (read_p15_c1 () & C1_IC) != 0;
}
/*
* this function is called just before we call linux
* it prepares the processor for linux
/**
* Prepare a "clean" CPU for Linux to run
* @return 0 (always)
*
* This function is called by the generic U-Boot part just before we call
* Linux. It prepares the processor for Linux.
*/
int cleanup_before_linux (void)
{
int i;
/*
* we never enable dcache so we do not need to disable
* it. Linux can be called with icache enabled, so just
* do nothing here
*/
/* flush I/D-cache */
i = 0;
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
return (0);
}
/**
* @page arm_boot_preparation Linux Preparation on ARM
*
* For ARM we never enable data cache so we do not need to disable it again.
* Linux can be called with instruction cache enabled. As this is the
* default setting we are running in U-Boot, there's no special preparation
* required.
*/
#ifdef CONFIG_USE_IRQ
static int cpu_init (void)
@ -106,3 +168,9 @@ static int cpu_init (void)
core_initcall(cpu_init);
#endif
/**
* @page arm_for_linux Preparing for Linux to run
*
* What's to do on ARM to run Linux after U-Boot did its job?
*/

81
arch/arm/cpu/interrupts.c
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@ -1,3 +1,30 @@
/*
* interrupts.c - Interrupt Support Routines
*
* Copyright (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/**
* @file
* @brief Interrupt Support Routines
*/
#include <common.h>
#include <asm/ptrace.h>
@ -32,12 +59,19 @@ int disable_interrupts (void)
}
#endif
/**
* FIXME
*/
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
reset_cpu (0);
}
/**
* Display current register set content
* @param[in] regs Guess what
*/
void show_regs (struct pt_regs *regs)
{
unsigned long flags;
@ -75,6 +109,10 @@ void show_regs (struct pt_regs *regs)
thumb_mode (regs) ? " (T)" : "");
}
/**
* The CPU runs into an undefined instruction. That really should not happen!
* @param[in] pt_regs Register set content when the accident happens
*/
void do_undefined_instruction (struct pt_regs *pt_regs)
{
printf ("undefined instruction\n");
@ -82,6 +120,13 @@ void do_undefined_instruction (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a software interrupt
* @param[in] pt_regs Register set content when the interrupt happens
*
* There is not functione behind this feature. So what to do else than
* a reset?
*/
void do_software_interrupt (struct pt_regs *pt_regs)
{
printf ("software interrupt\n");
@ -89,6 +134,12 @@ void do_software_interrupt (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a prefetch abort. That really should not happen!
* @param[in] pt_regs Register set content when the accident happens
*
* FIXME: What does it mean, why is reset the only solution?
*/
void do_prefetch_abort (struct pt_regs *pt_regs)
{
printf ("prefetch abort\n");
@ -96,6 +147,12 @@ void do_prefetch_abort (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a data abort. That really should not happen!
* @param[in] pt_regs Register set content when the accident happens
*
* FIXME: What does it mean, why is reset the only solution?
*/
void do_data_abort (struct pt_regs *pt_regs)
{
printf ("data abort\n");
@ -103,6 +160,12 @@ void do_data_abort (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a not-used(?) abort.
* @param[in] pt_regs Register set content when the accident happens
*
* FIXME: What does it mean, why is reset the only solution?
*/
void do_not_used (struct pt_regs *pt_regs)
{
printf ("not used\n");
@ -110,6 +173,12 @@ void do_not_used (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a fast interrupt request.
* @param[in] pt_regs Register set content when the interrupt happens
*
* FIXME: What does it mean, why is reset the only solution?
*/
void do_fiq (struct pt_regs *pt_regs)
{
printf ("fast interrupt request\n");
@ -117,9 +186,21 @@ void do_fiq (struct pt_regs *pt_regs)
bad_mode ();
}
/**
* The CPU catches a regular interrupt.
* @param[in] pt_regs Register set content when the interrupt happens
*
* FIXME: What does it mean, why is reset the only solution?
*/
void do_irq (struct pt_regs *pt_regs)
{
printf ("interrupt request\n");
show_regs (pt_regs);
bad_mode ();
}
/**
* @page arm_interrupts Interrupt handling on ARM
*
* Why U-boot doesn't use interrupts?
*/

19
arch/arm/cpu/start-arm920t.S
View File

@ -24,13 +24,18 @@
* MA 02111-1307 USA
*/
/*
* Note:
* This file can be used for at least:
* - ARM920T
* - i.MX1
* - i.MX27
* - i.MX31
/**
* @file
* @brief The very basic beginning of each CPU after reset
*
* @note
* This reset code can be used at least for:
* - ARM920T
* - i.MX1
* - i.MX27
* - i.MX31
*
* FIXME: Stop doxygen from parsing the text below
*/
.section ".text_entry","ax"

5
arch/sandbox/lib/tap.c
View File

@ -61,3 +61,8 @@ int tap_alloc(char *dev)
strcpy(dev, ifr.ifr_name);
return fd;
}
/**
* @file
* @brief Host side functions for tap driver
*/

80
board/board.dox
View File

@ -1,5 +1,81 @@
/** @page dev_board Integrating a new Board
/** @page dev_board Adapting a new Board
Blablubb
To add a new board to U-Boot a few steps must be done, to extend and modify
the U-Boot source tree.
@section board_add_files Files/Directories to be added
- board/<boardname>
- board/<boardname>/<boardname>.c
- board/<boardname>/<boardname>.dox
- board/<boardname>/Makefile
- include/configs/<boardname>.h
- arch/<architecture>/configs/<boardname>_defconfig
Makefile
obj-y += all files that builds the BSP (Assembler and/or C files)
@subsection board_doxygen board/<boardname>/<boardname>.dox
This file should describe in short words your new board, what CPU
it uses, what resources are provided and features it supports.
Use the doxygen style for this kind of documentation. Below you find a
template for this kind of file
@code
</>** <@>page <boardname> <Manufacturer> <Board's Name>
This board uses an <architecture> based CPU. The board is shipped with:
- many MiB NOR type Flash Memory
- many MiB SDRAM
- a very special network controller
and so on.
*</>
@endcode
To make your new shiny file visible in the automatically generated
documentation you must sort in the used page lable ("<boardname>" in the
template above) into Documentation/boards.dox as
@code
...
<@>subpage <boardname>
...
@endcode
at the right architecture.
@note Consider to use an unique page lable.
@subsection board_lscript board/<boardname>/u-boot.ld.S
If your board needs a special binary U-Boot layout, you can provide a local
board linker script file. This will replace the generic one provided by your
architecture or CPU support.
Add this file with
@code
extra-y += <board_linker_script>
@endcode
in your local Makefile to the list of files, forwarded to the last linking step.
@section board_mod_files These files needs to be modified:
- modify board/board.doc
- modify arch/<architecture>/Kconfig
- add your board (MACH_*) to the list
- add your default text base address for this architecture (ARCH_TEXT_BASE)
- add BOARDINFO with valueable info for your board
- modify arch/<architecture>/Makefile:
- add board-$(MACH_*) = <your board_dir>
First, the new board should be visible in the menu.
*/

17
commands/bootm.c
View File

@ -853,3 +853,20 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp,
}
#endif /* CONFIG_LYNXKDI */
/**
* @file
* @brief Boot support for Linux
*/
/**
* @page boot_preparation Preparing for Boot
*
* This chapter describes what's to be done to forward the control from
* U-Boot to Linux. This part describes the generic part, below you can find
* the architecture specific part.
*
* - @subpage arm_boot_preparation
* - @subpage ppc_boot_preparation
* - @subpage x86_boot_preparation
*/

2
common/env.c
View File

@ -61,7 +61,7 @@ static struct env_context *context;
/**
* Remove a list of environment variables
* @param[inout] v Variable anchor to remove
* @param[in] v Variable anchor to remove
*/
static void free_variables(struct variable_d *v)
{

46
drivers/cfi_flash.c
View File

@ -31,8 +31,9 @@
*
*/
/* The DEBUG define must be before common to enable debugging */
/* #define DEBUG */
#ifdef CONFIG_ENABLE_FLASH_NOISE
# define DEBUG
#endif
#include <common.h>
#include <asm/byteorder.h>
@ -42,22 +43,6 @@
#include <malloc.h>
#include <cfi_flash.h>
/*
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
* These widths are used to calculate the address for access CFI data structures.
*
* References
* JEDEC Standard JESD68 - Common Flash Interface (CFI)
* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
* AMD CFI Specification, Release 2.0 December 1, 2001
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
*/
#define FLASH_CMD_CFI 0x98
#define FLASH_CMD_READ_ID 0x90
#define FLASH_CMD_RESET 0xff
@ -326,16 +311,14 @@ static int cfi_probe (struct device_d *dev)
dev->priv = (void *)info;
printf("cfi_probe: %s base: 0x%08x size: 0x%08x\n", dev->name, dev->map_base, dev->size);
debug ("cfi_probe: %s base: 0x%08x size: 0x%08x\n", dev->name, dev->map_base, dev->size);
/* Init: no FLASHes known */
info->flash_id = FLASH_UNKNOWN;
size += info->size = flash_get_size(info, dev->map_base);
if (info->flash_id == FLASH_UNKNOWN) {
#ifndef CFG_FLASH_QUIET_TEST
printf ("## Unknown FLASH on Bank at 0x%08x - Size = 0x%08lx = %ld MB\n",
debug ("## Unknown FLASH on Bank at 0x%08x - Size = 0x%08lx = %ld MB\n",
dev->map_base, info->size, info->size << 20);
#endif /* CFG_FLASH_QUIET_TEST */
}
return 0;
@ -1495,3 +1478,22 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, const uchar *
}
#endif /* CONFIG_CFI_BUFFER_WRITE */
/**
* @file
* @brief This file implements a Common Flash Interface (CFI) driver for U-Boot.
*
* This file implements a Common Flash Interface (CFI) driver for U-Boot.
* The width of the port and the width of the chips are determined at initialization.
* These widths are used to calculate the address for access CFI data structures.
*
* References
*
* - JEDEC Standard JESD68 - Common Flash Interface (CFI)
* - JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
* - Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
* - Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
* - AMD CFI Specification, Release 2.0 December 1, 2001
* - AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
*/

88
drivers/nand/nand_base.c
View File

@ -504,10 +504,10 @@ static int nand_check_wp (struct mtd_info *mtd)
/**
* nand_block_checkbad - [GENERIC] Check if a block is marked bad
* @mtd: MTD device structure
* @ofs: offset from device start
* @getchip: 0, if the chip is already selected
* @allowbbt: 1, if its allowed to access the bbt area
* @param[in] mtd: MTD device structure
* @param[in] ofs: offset from device start
* @param[in] getchip: 0, if the chip is already selected
* @param[in] allowbbt: 1, if its allowed to access the bbt area
*
* Check, if the block is bad. Either by reading the bad block table or
* calling of the scan function.
@ -525,10 +525,10 @@ static int nand_block_checkbad (struct mtd_info *mtd, loff_t ofs, int getchip, i
/**
* nand_command - [DEFAULT] Send command to NAND device
* @mtd: MTD device structure
* @command: the command to be sent
* @column: the column address for this command, -1 if none
* @page_addr: the page address for this command, -1 if none
* @param[in] mtd: MTD device structure
* @param[in] command: the command to be sent
* @param[in] column: the column address for this command, -1 if none
* @param[in] page_addr: the page address for this command, -1 if none
*
* Send command to NAND device. This function is used for small page
* devices (256/512 Bytes per page)
@ -628,10 +628,10 @@ static void nand_command (struct mtd_info *mtd, unsigned command, int column, in
/**
* nand_command_lp - [DEFAULT] Send command to NAND large page device
* @mtd: MTD device structure
* @command: the command to be sent
* @column: the column address for this command, -1 if none
* @page_addr: the page address for this command, -1 if none
* @param[in] mtd: MTD device structure
* @param[in] command: the command to be sent
* @param[in] column: the column address for this command, -1 if none
* @param[in] page_addr: the page address for this command, -1 if none
*
* Send command to NAND device. This is the version for the new large page devices
* We dont have the seperate regions as we have in the small page devices.
@ -733,9 +733,9 @@ static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column,
/**
* nand_get_device - [GENERIC] Get chip for selected access
* @this: the nand chip descriptor
* @mtd: MTD device structure
* @new_state: the state which is requested
* @param[in] this: the nand chip descriptor
* @param[in] mtd: MTD device structure
* @param[in] new_state: the state which is requested
*
* Get the device and lock it for exclusive access
*/
@ -782,9 +782,9 @@ static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int n
/**
* nand_wait - [DEFAULT] wait until the command is done
* @mtd: MTD device structure
* @this: NAND chip structure
* @state: state to select the max. timeout value
* @param[in] mtd: MTD device structure
* @param[in] this: NAND chip structure
* @param[in] state: state to select the max. timeout value
*
* Wait for command done. This applies to erase and program only
* Erase can take up to 400ms and program up to 20ms according to
@ -873,12 +873,12 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
/**
* nand_write_page - [GENERIC] write one page
* @mtd: MTD device structure
* @this: NAND chip structure
* @page: startpage inside the chip, must be called with (page & this->pagemask)
* @oob_buf: out of band data buffer
* @oobsel: out of band selecttion structre
* @cached: 1 = enable cached programming if supported by chip
* @param[in] mtd: MTD device structure
* @param[in] this: NAND chip structure
* @param[in] page: startpage inside the chip, must be called with (page & this->pagemask)
* @param[in] oob_buf: out of band data buffer
* @param[in] oobsel: out of band selecttion structre
* @param[in] cached: 1 = enable cached programming if supported by chip
*
* Nand_page_program function is used for write and writev !
* This function will always program a full page of data
@ -967,14 +967,14 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa
#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
/**
* nand_verify_pages - [GENERIC] verify the chip contents after a write
* @mtd: MTD device structure
* @this: NAND chip structure
* @page: startpage inside the chip, must be called with (page & this->pagemask)
* @numpages: number of pages to verify
* @oob_buf: out of band data buffer
* @oobsel: out of band selecttion structre
* @chipnr: number of the current chip
* @oobmode: 1 = full buffer verify, 0 = ecc only
* @param[in] mtd: MTD device structure
* @param[in] this: NAND chip structure
* @param[in] page: startpage inside the chip, must be called with (page & this->pagemask)
* @param[in] numpages: number of pages to verify
* @param[in] oob_buf: out of band data buffer
* @param[in] oobsel: out of band selecttion structre
* @param[in] chipnr: number of the current chip
* @param[in] oobmode: 1 = full buffer verify, 0 = ecc only
*
* The NAND device assumes that it is always writing to a cleanly erased page.
* Hence, it performs its internal write verification only on bits that
@ -1078,11 +1078,11 @@ out:
/**
* nand_read - [MTD Interface] MTD compability function for nand_read_ecc
* @mtd: MTD device structure
* @from: offset to read from
* @len: number of bytes to read
* @retlen: pointer to variable to store the number of read bytes
* @buf: the databuffer to put data
* @param[in] mtd: MTD device structure
* @param[in] from: offset to read from
* @param[in] len: number of bytes to read
* @param[in] retlen: pointer to variable to store the number of read bytes
* @param[in] buf: the databuffer to put data
*
* This function simply calls nand_read_ecc with oob buffer and oobsel = NULL
*/
@ -1094,11 +1094,11 @@ static int nand_read (struct mtd_info *mtd, loff_t from, size_t len, size_t * re
/**
* nand_read_ecc - [MTD Interface] Read data with ECC
* @mtd: MTD device structure
* @from: offset to read from
* @len: number of bytes to read
* @retlen: pointer to variable to store the number of read bytes
* @buf: the databuffer to put data
* @param[in] mtd: MTD device structure
* @param[in] from: offset to read from
* @param[in] len: number of bytes to read
* @param[in] retlen: pointer to variable to store the number of read bytes
* @param[in] buf: the databuffer to put data
* @oob_buf: filesystem supplied oob data buffer
* @oobsel: oob selection structure
*
@ -2041,7 +2041,7 @@ out:
/**
* single_erease_cmd - [GENERIC] NAND standard block erase command function
* @mtd: MTD device structure
* @page: the page address of the block which will be erased
* @param[in] page: the page address of the block which will be erased
*
* Standard erase command for NAND chips
*/
@ -2056,7 +2056,7 @@ static void single_erase_cmd (struct mtd_info *mtd, int page)
/**
* multi_erease_cmd - [GENERIC] AND specific block erase command function
* @mtd: MTD device structure
* @page: the page address of the block which will be erased
* @param[in] page: the page address of the block which will be erased
*
* AND multi block erase command function
* Erase 4 consecutive blocks

2
drivers/nand/nand_bbt.c
View File

@ -108,7 +108,7 @@ static int check_pattern (uint8_t *buf, int len, int paglen, struct nand_bbt_des
* read_bbt - [GENERIC] Read the bad block table starting from page
* @mtd: MTD device structure
* @buf: temporary buffer
* @page: the starting page
* @param[in] page: the starting page
* @num: the number of bbt descriptors to read
* @bits: number of bits per block
* @offs: offset in the memory table