spi: i.MX: move register defines to include/
The register defines will be used by the SPI xload code, so move them to a place where the xload code can include them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -18,6 +18,7 @@
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#include <init.h>
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#include <driver.h>
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#include <spi/spi.h>
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#include <spi/imx-spi.h>
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#include <xfuncs.h>
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#include <io.h>
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#include <of.h>
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@ -31,85 +32,6 @@
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#include <linux/err.h>
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#include <clock.h>
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#define CSPI_0_0_RXDATA 0x00
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#define CSPI_0_0_TXDATA 0x04
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#define CSPI_0_0_CTRL 0x08
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#define CSPI_0_0_INT 0x0C
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#define CSPI_0_0_DMA 0x18
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#define CSPI_0_0_STAT 0x0C
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#define CSPI_0_0_PERIOD 0x14
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#define CSPI_0_0_TEST 0x10
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#define CSPI_0_0_RESET 0x1C
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#define CSPI_0_0_CTRL_ENABLE (1 << 10)
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#define CSPI_0_0_CTRL_MASTER (1 << 11)
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#define CSPI_0_0_CTRL_XCH (1 << 9)
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#define CSPI_0_0_CTRL_LOWPOL (1 << 5)
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#define CSPI_0_0_CTRL_PHA (1 << 6)
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#define CSPI_0_0_CTRL_SSCTL (1 << 7)
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#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8)
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#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19)
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#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0)
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#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14)
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#define CSPI_0_0_CTRL_MAXDATRATE 0x10
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#define CSPI_0_0_CTRL_DATAMASK 0x1F
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#define CSPI_0_0_CTRL_DATASHIFT 14
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#define CSPI_0_0_STAT_TE (1 << 0)
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#define CSPI_0_0_STAT_TH (1 << 1)
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#define CSPI_0_0_STAT_TF (1 << 2)
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#define CSPI_0_0_STAT_RR (1 << 4)
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#define CSPI_0_0_STAT_RH (1 << 5)
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#define CSPI_0_0_STAT_RF (1 << 6)
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#define CSPI_0_0_STAT_RO (1 << 7)
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#define CSPI_0_0_PERIOD_32KHZ (1 << 15)
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#define CSPI_0_0_TEST_LBC (1 << 14)
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#define CSPI_0_0_RESET_START (1 << 0)
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#define CSPI_0_7_RXDATA 0x00
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#define CSPI_0_7_TXDATA 0x04
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#define CSPI_0_7_CTRL 0x08
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#define CSPI_0_7_CTRL_ENABLE (1 << 0)
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#define CSPI_0_7_CTRL_MASTER (1 << 1)
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#define CSPI_0_7_CTRL_XCH (1 << 2)
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#define CSPI_0_7_CTRL_POL (1 << 4)
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#define CSPI_0_7_CTRL_PHA (1 << 5)
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#define CSPI_0_7_CTRL_SSCTL (1 << 6)
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#define CSPI_0_7_CTRL_SSPOL (1 << 7)
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#define CSPI_0_7_CTRL_CS_SHIFT 12
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#define CSPI_0_7_CTRL_DR_SHIFT 16
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#define CSPI_0_7_CTRL_BL_SHIFT 20
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#define CSPI_0_7_STAT 0x14
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#define CSPI_0_7_STAT_RR (1 << 3)
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#define CSPI_2_3_RXDATA 0x00
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#define CSPI_2_3_TXDATA 0x04
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#define CSPI_2_3_CTRL 0x08
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#define CSPI_2_3_CTRL_ENABLE (1 << 0)
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#define CSPI_2_3_CTRL_XCH (1 << 2)
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#define CSPI_2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CTRL_POSTDIV_OFFSET 8
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#define CSPI_2_3_CTRL_PREDIV_OFFSET 12
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#define CSPI_2_3_CTRL_CS(cs) ((cs) << 18)
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#define CSPI_2_3_CTRL_BL_OFFSET 20
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#define CSPI_2_3_CONFIG 0x0c
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#define CSPI_2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define CSPI_2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define CSPI_2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define CSPI_2_3_INT 0x10
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#define CSPI_2_3_INT_TEEN (1 << 0)
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#define CSPI_2_3_INT_RREN (1 << 3)
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#define CSPI_2_3_STAT 0x18
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#define CSPI_2_3_STAT_RR (1 << 3)
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struct imx_spi {
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struct spi_master master;
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int *cs_array;
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@ -0,0 +1,83 @@
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#ifndef __SPI_IMX_SPI_H
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#define __SPI_IMX_SPI_H
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#define CSPI_0_0_RXDATA 0x00
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#define CSPI_0_0_TXDATA 0x04
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#define CSPI_0_0_CTRL 0x08
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#define CSPI_0_0_INT 0x0C
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#define CSPI_0_0_DMA 0x18
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#define CSPI_0_0_STAT 0x0C
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#define CSPI_0_0_PERIOD 0x14
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#define CSPI_0_0_TEST 0x10
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#define CSPI_0_0_RESET 0x1C
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#define CSPI_0_0_CTRL_ENABLE (1 << 10)
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#define CSPI_0_0_CTRL_MASTER (1 << 11)
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#define CSPI_0_0_CTRL_XCH (1 << 9)
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#define CSPI_0_0_CTRL_LOWPOL (1 << 5)
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#define CSPI_0_0_CTRL_PHA (1 << 6)
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#define CSPI_0_0_CTRL_SSCTL (1 << 7)
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#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8)
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#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19)
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#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0)
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#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14)
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#define CSPI_0_0_CTRL_MAXDATRATE 0x10
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#define CSPI_0_0_CTRL_DATAMASK 0x1F
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#define CSPI_0_0_CTRL_DATASHIFT 14
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#define CSPI_0_0_STAT_TE (1 << 0)
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#define CSPI_0_0_STAT_TH (1 << 1)
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#define CSPI_0_0_STAT_TF (1 << 2)
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#define CSPI_0_0_STAT_RR (1 << 4)
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#define CSPI_0_0_STAT_RH (1 << 5)
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#define CSPI_0_0_STAT_RF (1 << 6)
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#define CSPI_0_0_STAT_RO (1 << 7)
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#define CSPI_0_0_PERIOD_32KHZ (1 << 15)
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#define CSPI_0_0_TEST_LBC (1 << 14)
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#define CSPI_0_0_RESET_START (1 << 0)
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#define CSPI_0_7_RXDATA 0x00
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#define CSPI_0_7_TXDATA 0x04
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#define CSPI_0_7_CTRL 0x08
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#define CSPI_0_7_CTRL_ENABLE (1 << 0)
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#define CSPI_0_7_CTRL_MASTER (1 << 1)
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#define CSPI_0_7_CTRL_XCH (1 << 2)
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#define CSPI_0_7_CTRL_POL (1 << 4)
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#define CSPI_0_7_CTRL_PHA (1 << 5)
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#define CSPI_0_7_CTRL_SSCTL (1 << 6)
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#define CSPI_0_7_CTRL_SSPOL (1 << 7)
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#define CSPI_0_7_CTRL_CS_SHIFT 12
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#define CSPI_0_7_CTRL_DR_SHIFT 16
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#define CSPI_0_7_CTRL_BL_SHIFT 20
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#define CSPI_0_7_STAT 0x14
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#define CSPI_0_7_STAT_RR (1 << 3)
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#define CSPI_2_3_RXDATA 0x00
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#define CSPI_2_3_TXDATA 0x04
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#define CSPI_2_3_CTRL 0x08
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#define CSPI_2_3_CTRL_ENABLE (1 << 0)
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#define CSPI_2_3_CTRL_XCH (1 << 2)
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#define CSPI_2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CTRL_POSTDIV_OFFSET 8
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#define CSPI_2_3_CTRL_PREDIV_OFFSET 12
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#define CSPI_2_3_CTRL_CS(cs) ((cs) << 18)
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#define CSPI_2_3_CTRL_BL_OFFSET 20
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#define CSPI_2_3_CONFIG 0x0c
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#define CSPI_2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
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#define CSPI_2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
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#define CSPI_2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
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#define CSPI_2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
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#define CSPI_2_3_INT 0x10
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#define CSPI_2_3_INT_TEEN (1 << 0)
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#define CSPI_2_3_INT_RREN (1 << 3)
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#define CSPI_2_3_STAT 0x18
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#define CSPI_2_3_STAT_RR (1 << 3)
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#endif /* __SPI_IMX_SPI_H */
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