Merge branch 'pu/omap' into for-next/omap
This commit is contained in:
commit
4db0a48aec
11
Makefile
11
Makefile
|
@ -547,17 +547,6 @@ quiet_cmd_barebox_version = GEN .version
|
|||
fi; \
|
||||
$(MAKE) $(build)=common
|
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|
||||
# Check size of a file
|
||||
quiet_cmd_check_file_size = CHKSIZE $@
|
||||
cmd_check_file_size = set -e; \
|
||||
size=`stat -c%s $@`; \
|
||||
max_size=`printf "%d" $2`; \
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||||
if [ $$size -gt $$max_size ] ; \
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then \
|
||||
echo "$@ size $$size > of the maximum size $$max_size" >&2; \
|
||||
exit 1 ; \
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||||
fi;
|
||||
|
||||
# Generate System.map
|
||||
quiet_cmd_sysmap = SYSMAP
|
||||
cmd_sysmap = $(CONFIG_SHELL) $(srctree)/scripts/mksysmap
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|
|
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@ -39,7 +39,7 @@ static struct at91_ether_platform_data ether_pdata = {
|
|||
|
||||
static int at91rm9200ek_mem_init(void)
|
||||
{
|
||||
at91_add_device_sdram(64 * 1024 * 1024);
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||||
at91_add_device_sdram(32 * 1024 * 1024);
|
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|
||||
return 0;
|
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}
|
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|
|
|
@ -113,7 +113,6 @@ static struct at91_ether_platform_data macb_pdata = {
|
|||
#if defined(CONFIG_MCI_ATMEL)
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||||
static struct atmel_mci_platform_data ek_mci_data = {
|
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.bus_width = 4,
|
||||
.host_caps = MMC_MODE_HS,
|
||||
.detect_pin = AT91_PIN_PD10,
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||||
};
|
||||
|
||||
|
|
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@ -131,7 +131,7 @@ static void __init ek_add_device_ks8851(void) {}
|
|||
static struct atmel_mci_platform_data mci0_data = {
|
||||
.bus_width = 4,
|
||||
.detect_pin = AT91_PIN_PA7,
|
||||
.wp_pin = 0,
|
||||
.wp_pin = -EINVAL,
|
||||
};
|
||||
|
||||
static void ek_add_device_mci(void)
|
||||
|
|
|
@ -46,6 +46,7 @@
|
|||
|
||||
struct w1_gpio_platform_data w1_pdata = {
|
||||
.pin = AT91_PIN_PB18,
|
||||
.ext_pullup_enable_pin = -EINVAL,
|
||||
.is_open_drain = 0,
|
||||
};
|
||||
|
||||
|
@ -124,13 +125,13 @@ static void ek_add_device_eth(void)
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|||
static struct atmel_mci_platform_data mci0_data = {
|
||||
.bus_width = 4,
|
||||
.detect_pin = AT91_PIN_PD15,
|
||||
.wp_pin = 0,
|
||||
.wp_pin = -EINVAL,
|
||||
};
|
||||
|
||||
static void ek_add_device_mci(void)
|
||||
{
|
||||
if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT))
|
||||
mci0_data.detect_pin = 0;
|
||||
mci0_data.detect_pin = -EINVAL;
|
||||
|
||||
/* MMC0 */
|
||||
at91_add_device_mci(0, &mci0_data);
|
||||
|
|
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@ -1 +1,3 @@
|
|||
obj-y += board.o
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||||
obj-y += lowlevel.o
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||||
pbl-y += lowlevel.o
|
||||
|
|
|
@ -55,12 +55,6 @@
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|||
#include <ns16550.h>
|
||||
#include <asm/armlinux.h>
|
||||
#include <generated/mach-types.h>
|
||||
#include <mach/omap3-silicon.h>
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||||
#include <mach/sdrc.h>
|
||||
#include <mach/sys_info.h>
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||||
#include <mach/syslib.h>
|
||||
#include <mach/control.h>
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#include <mach/omap3-mux.h>
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#include <mach/gpmc.h>
|
||||
#include <mach/gpmc_nand.h>
|
||||
#include <mach/ehci.h>
|
||||
|
@ -70,169 +64,6 @@
|
|||
#include <usb/ehci.h>
|
||||
#include <mach/xload.h>
|
||||
|
||||
/******************** Board Boot Time *******************/
|
||||
|
||||
/**
|
||||
* @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* SDRAM software reset */
|
||||
/* No idle ack and RESET enable */
|
||||
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
sdelay(100);
|
||||
/* No idle ack and RESET disable */
|
||||
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC Registers Configuration --------- */
|
||||
/* SDRC_MCFG0 register */
|
||||
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_RFR_CTRL0 register */
|
||||
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLA0 register */
|
||||
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLB0 register */
|
||||
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE due to 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_MANUAL command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register Burst length=4 */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the pin muxing required for Board operation.
|
||||
* We enable ONLY the pins we require to set. OMAP provides pins which do not
|
||||
* have alternate modes. Such pins done need to be set.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
|
||||
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
|
||||
|
||||
/* D0-D7 default mux mode is mode0 */
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
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||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
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||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
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||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
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||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
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||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
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||||
/* GPMC_NADV_ALE default mux mode is mode0 */
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||||
/* GPMC_NOE default mux mode is mode0 */
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||||
/* GPMC_NWE default mux mode is mode0 */
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||||
/* GPMC_NBE0_CLE default mux mode is mode0 */
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||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
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/* GPMC_WAIT0 default mux mode is mode0 */
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MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
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|
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/* SERIAL INTERFACE */
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
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MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
|
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MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
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MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
|
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MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
|
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MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
|
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MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
|
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MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
|
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/* I2C1_SCL default mux mode is mode0 */
|
||||
/* I2C1_SDA default mux mode is mode0 */
|
||||
/* USB EHCI (port 2) */
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
|
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MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int beagle_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(beagle_board_init);
|
||||
|
||||
/******************** Board Run Time *******************/
|
||||
|
||||
#ifdef CONFIG_DRIVER_SERIAL_NS16550
|
||||
|
||||
/**
|
||||
|
|
|
@ -0,0 +1,167 @@
|
|||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/sys_info.h>
|
||||
|
||||
/**
|
||||
* @brief Do the pin muxing required for Board operation.
|
||||
* We enable ONLY the pins we require to set. OMAP provides pins which do not
|
||||
* have alternate modes. Such pins done need to be set.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/* SDRC_D0 - SDRC_D31 default mux mode is mode0 */
|
||||
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
|
||||
|
||||
/* D0-D7 default mux mode is mode0 */
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
|
||||
/* GPMC_NADV_ALE default mux mode is mode0 */
|
||||
/* GPMC_NOE default mux mode is mode0 */
|
||||
/* GPMC_NWE default mux mode is mode0 */
|
||||
/* GPMC_NBE0_CLE default mux mode is mode0 */
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
/* GPMC_WAIT0 default mux mode is mode0 */
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
|
||||
|
||||
/* SERIAL INTERFACE */
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
|
||||
/* I2C1_SCL default mux mode is mode0 */
|
||||
/* I2C1_SDA default mux mode is mode0 */
|
||||
/* USB EHCI (port 2) */
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the SDRC initialization for 128Meg Micron DDR for CS0
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* SDRAM software reset */
|
||||
/* No idle ack and RESET enable */
|
||||
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
sdelay(100);
|
||||
/* No idle ack and RESET disable */
|
||||
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC Registers Configuration --------- */
|
||||
/* SDRC_MCFG0 register */
|
||||
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_RFR_CTRL0 register */
|
||||
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLA0 register */
|
||||
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLB0 register */
|
||||
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE due to 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_MANUAL command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register Burst length=4 */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int beagle_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(beagle_board_init);
|
|
@ -1 +1,3 @@
|
|||
obj-y += board.o
|
||||
obj-y += lowlevel.o
|
||||
pbl-y += lowlevel.o
|
||||
|
|
|
@ -52,246 +52,6 @@
|
|||
#include <mach/am33xx-generic.h>
|
||||
#include <mach/cpsw.h>
|
||||
|
||||
/* UART Defines */
|
||||
#define UART_SYSCFG_OFFSET (0x54)
|
||||
#define UART_SYSSTS_OFFSET (0x58)
|
||||
|
||||
#define UART_RESET (0x1 << 1)
|
||||
#define UART_CLK_RUNNING_MASK 0x1
|
||||
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define EMIF_SDMGT 0x80000000
|
||||
#define EMIF_SDRAM 0x00004650
|
||||
#define EMIF_PHYCFG 0x2
|
||||
#define DDR_PHY_RESET (0x1 << 10)
|
||||
#define DDR_FUNCTIONAL_MODE_EN 0x1
|
||||
#define DDR_PHY_READY (0x1 << 2)
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_LOCK_EN (0x1 << 4)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
#define DDR2_RATIO 0x80 /* for mDDR */
|
||||
#define CMD_FORCE 0x00 /* common #def */
|
||||
#define CMD_DELAY 0x00
|
||||
|
||||
#define EMIF_READ_LATENCY 0x05
|
||||
#define EMIF_TIM1 0x0666B3D6
|
||||
#define EMIF_TIM2 0x143731DA
|
||||
#define EMIF_TIM3 0x00000347
|
||||
#define EMIF_SDCFG 0x43805332
|
||||
#define EMIF_SDREF 0x0000081a
|
||||
#define DDR2_DLL_LOCK_DIFF 0x0
|
||||
#define DDR2_RD_DQS 0x12
|
||||
#define DDR2_PHY_FIFO_WE 0x80
|
||||
|
||||
#define DDR2_INVERT_CLKOUT 0x00
|
||||
#define DDR2_WR_DQS 0x00
|
||||
#define DDR2_PHY_WRLVL 0x00
|
||||
#define DDR2_PHY_GATELVL 0x00
|
||||
#define DDR2_PHY_WR_DATA 0x40
|
||||
#define PHY_RANK0_DELAY 0x01
|
||||
#define PHY_DLL_LOCK_DIFF 0x0
|
||||
#define DDR_IOCTRL_VALUE 0x18B
|
||||
|
||||
static void beaglebone_data_macro_config(int dataMacroNum)
|
||||
{
|
||||
u32 BaseAddrOffset = 0x00;;
|
||||
|
||||
if (dataMacroNum == 1)
|
||||
BaseAddrOffset = 0xA4;
|
||||
|
||||
__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|
||||
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
|
||||
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_RD_DQS>>2,
|
||||
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|
||||
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
|
||||
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_WR_DQS>>2,
|
||||
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|
||||
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
|
||||
(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_WRLVL>>2,
|
||||
(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|
||||
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
|
||||
(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_GATELVL>>2,
|
||||
(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|
||||
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
|
||||
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_FIFO_WE>>2,
|
||||
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|
||||
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
|
||||
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_WR_DATA>>2,
|
||||
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(PHY_DLL_LOCK_DIFF,
|
||||
(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
|
||||
}
|
||||
|
||||
static void beaglebone_cmd_macro_config(void)
|
||||
{
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
|
||||
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
|
||||
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
|
||||
}
|
||||
|
||||
static void beaglebone_config_vtp(void)
|
||||
{
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
|
||||
/* Poll for READY */
|
||||
while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
|
||||
}
|
||||
|
||||
static void beaglebone_config_emif_ddr2(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/*Program EMIF0 CFG Registers*/
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
|
||||
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
|
||||
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
|
||||
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
|
||||
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
|
||||
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
|
||||
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
|
||||
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
|
||||
|
||||
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
|
||||
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
|
||||
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
|
||||
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
|
||||
|
||||
for (i = 0; i < 5000; i++) {
|
||||
|
||||
}
|
||||
|
||||
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
|
||||
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
|
||||
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
|
||||
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
|
||||
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
|
||||
}
|
||||
|
||||
static void beaglebone_config_ddr(void)
|
||||
{
|
||||
enable_ddr_clocks();
|
||||
|
||||
beaglebone_config_vtp();
|
||||
|
||||
beaglebone_cmd_macro_config();
|
||||
beaglebone_data_macro_config(0);
|
||||
beaglebone_data_macro_config(1);
|
||||
|
||||
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
|
||||
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
|
||||
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
|
||||
|
||||
__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
|
||||
__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
|
||||
|
||||
beaglebone_config_emif_ddr2();
|
||||
}
|
||||
|
||||
/*
|
||||
* early system init of muxing and clocks.
|
||||
*/
|
||||
void beaglebone_sram_init(void)
|
||||
{
|
||||
u32 regVal, uart_base;
|
||||
|
||||
/* Setup the PLLs and the clocks for the peripherals */
|
||||
pll_init();
|
||||
|
||||
beaglebone_config_ddr();
|
||||
|
||||
/* UART softreset */
|
||||
uart_base = AM33XX_UART0_BASE;
|
||||
|
||||
regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
|
||||
regVal |= UART_RESET;
|
||||
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
|
||||
while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
|
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
|
||||
|
||||
/* Disable smart idle */
|
||||
regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
|
||||
regVal |= UART_SMART_IDLE_EN;
|
||||
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int beaglebone_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
/* WDT1 is already running when the bootloader gets control
|
||||
* Disable it to avoid "random" resets
|
||||
*/
|
||||
__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
|
||||
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
|
||||
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
|
||||
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
|
||||
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
beaglebone_sram_init();
|
||||
|
||||
/* Enable pin mux */
|
||||
enable_uart0_pin_mux();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(beaglebone_board_init);
|
||||
|
||||
/******************** Board Run Time *******************/
|
||||
|
||||
#ifdef CONFIG_DRIVER_SERIAL_NS16550
|
||||
|
||||
/**
|
||||
|
|
|
@ -0,0 +1,248 @@
|
|||
#include <init.h>
|
||||
#include <sizes.h>
|
||||
#include <io.h>
|
||||
#include <mach/am33xx-silicon.h>
|
||||
#include <mach/am33xx-clock.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/sys_info.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/am33xx-mux.h>
|
||||
#include <mach/wdt.h>
|
||||
|
||||
/* UART Defines */
|
||||
#define UART_SYSCFG_OFFSET (0x54)
|
||||
#define UART_SYSSTS_OFFSET (0x58)
|
||||
|
||||
#define UART_RESET (0x1 << 1)
|
||||
#define UART_CLK_RUNNING_MASK 0x1
|
||||
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||
|
||||
/* AM335X EMIF Register values */
|
||||
#define EMIF_SDMGT 0x80000000
|
||||
#define EMIF_SDRAM 0x00004650
|
||||
#define EMIF_PHYCFG 0x2
|
||||
#define DDR_PHY_RESET (0x1 << 10)
|
||||
#define DDR_FUNCTIONAL_MODE_EN 0x1
|
||||
#define DDR_PHY_READY (0x1 << 2)
|
||||
#define VTP_CTRL_READY (0x1 << 5)
|
||||
#define VTP_CTRL_ENABLE (0x1 << 6)
|
||||
#define VTP_CTRL_LOCK_EN (0x1 << 4)
|
||||
#define VTP_CTRL_START_EN (0x1)
|
||||
#define DDR2_RATIO 0x80 /* for mDDR */
|
||||
#define CMD_FORCE 0x00 /* common #def */
|
||||
#define CMD_DELAY 0x00
|
||||
|
||||
#define EMIF_READ_LATENCY 0x05
|
||||
#define EMIF_TIM1 0x0666B3D6
|
||||
#define EMIF_TIM2 0x143731DA
|
||||
#define EMIF_TIM3 0x00000347
|
||||
#define EMIF_SDCFG 0x43805332
|
||||
#define EMIF_SDREF 0x0000081a
|
||||
#define DDR2_DLL_LOCK_DIFF 0x0
|
||||
#define DDR2_RD_DQS 0x12
|
||||
#define DDR2_PHY_FIFO_WE 0x80
|
||||
|
||||
#define DDR2_INVERT_CLKOUT 0x00
|
||||
#define DDR2_WR_DQS 0x00
|
||||
#define DDR2_PHY_WRLVL 0x00
|
||||
#define DDR2_PHY_GATELVL 0x00
|
||||
#define DDR2_PHY_WR_DATA 0x40
|
||||
#define PHY_RANK0_DELAY 0x01
|
||||
#define PHY_DLL_LOCK_DIFF 0x0
|
||||
#define DDR_IOCTRL_VALUE 0x18B
|
||||
|
||||
static void beaglebone_data_macro_config(int dataMacroNum)
|
||||
{
|
||||
u32 BaseAddrOffset = 0x00;;
|
||||
|
||||
if (dataMacroNum == 1)
|
||||
BaseAddrOffset = 0xA4;
|
||||
|
||||
__raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
|
||||
|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
|
||||
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_RD_DQS>>2,
|
||||
(AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
|
||||
|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
|
||||
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_WR_DQS>>2,
|
||||
(AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
|
||||
|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
|
||||
(AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_WRLVL>>2,
|
||||
(AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
|
||||
|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
|
||||
(AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_GATELVL>>2,
|
||||
(AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
|
||||
|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
|
||||
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_FIFO_WE>>2,
|
||||
(AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
|
||||
|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
|
||||
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset));
|
||||
__raw_writel(DDR2_PHY_WR_DATA>>2,
|
||||
(AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset));
|
||||
__raw_writel(PHY_DLL_LOCK_DIFF,
|
||||
(AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset));
|
||||
}
|
||||
|
||||
static void beaglebone_cmd_macro_config(void)
|
||||
{
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
|
||||
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
|
||||
|
||||
__raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
|
||||
__raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
|
||||
__raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
|
||||
__raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
|
||||
__raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
|
||||
}
|
||||
|
||||
static void beaglebone_config_vtp(void)
|
||||
{
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
__raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
|
||||
AM33XX_VTP0_CTRL_REG);
|
||||
|
||||
/* Poll for READY */
|
||||
while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY);
|
||||
}
|
||||
|
||||
static void beaglebone_config_emif_ddr2(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/*Program EMIF0 CFG Registers*/
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
|
||||
__raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
|
||||
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
|
||||
__raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
|
||||
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
|
||||
__raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
|
||||
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
|
||||
__raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
|
||||
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
|
||||
|
||||
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
|
||||
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
|
||||
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
|
||||
__raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
|
||||
|
||||
for (i = 0; i < 5000; i++) {
|
||||
|
||||
}
|
||||
|
||||
/* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL);
|
||||
__raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */
|
||||
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
|
||||
__raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
|
||||
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
|
||||
__raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2));
|
||||
}
|
||||
|
||||
static void beaglebone_config_ddr(void)
|
||||
{
|
||||
enable_ddr_clocks();
|
||||
|
||||
beaglebone_config_vtp();
|
||||
|
||||
beaglebone_cmd_macro_config();
|
||||
beaglebone_data_macro_config(0);
|
||||
beaglebone_data_macro_config(1);
|
||||
|
||||
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
|
||||
__raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
|
||||
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
|
||||
__raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
|
||||
|
||||
__raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL);
|
||||
__raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL);
|
||||
|
||||
beaglebone_config_emif_ddr2();
|
||||
}
|
||||
|
||||
/*
|
||||
* early system init of muxing and clocks.
|
||||
*/
|
||||
void beaglebone_sram_init(void)
|
||||
{
|
||||
u32 regVal, uart_base;
|
||||
|
||||
/* Setup the PLLs and the clocks for the peripherals */
|
||||
pll_init();
|
||||
|
||||
beaglebone_config_ddr();
|
||||
|
||||
/* UART softreset */
|
||||
uart_base = AM33XX_UART0_BASE;
|
||||
|
||||
regVal = __raw_readl(uart_base + UART_SYSCFG_OFFSET);
|
||||
regVal |= UART_RESET;
|
||||
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET) );
|
||||
while ((__raw_readl(uart_base + UART_SYSSTS_OFFSET) &
|
||||
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
|
||||
|
||||
/* Disable smart idle */
|
||||
regVal = __raw_readl((uart_base + UART_SYSCFG_OFFSET));
|
||||
regVal |= UART_SMART_IDLE_EN;
|
||||
__raw_writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int beaglebone_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
/* WDT1 is already running when the bootloader gets control
|
||||
* Disable it to avoid "random" resets
|
||||
*/
|
||||
__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
|
||||
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
|
||||
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
|
||||
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
|
||||
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
beaglebone_sram_init();
|
||||
|
||||
/* Enable pin mux */
|
||||
enable_uart0_pin_mux();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(beaglebone_board_init);
|
|
@ -113,7 +113,6 @@ static void dss11_phy_reset(void)
|
|||
static struct atmel_mci_platform_data dss11_mci_data = {
|
||||
.slot_b = 1,
|
||||
.bus_width = 4,
|
||||
.host_caps = MMC_MODE_HS,
|
||||
};
|
||||
|
||||
static struct at91_usbh_data dss11_usbh_data = {
|
||||
|
|
|
@ -31,8 +31,6 @@
|
|||
#ifdef CONFIG_NAND_IMX_BOOT
|
||||
static void __bare_init __naked insdram(void)
|
||||
{
|
||||
uint32_t r;
|
||||
|
||||
/* setup a stack to be able to call imx_nand_load_image() */
|
||||
arm_setup_stack(STACK_BASE + STACK_SIZE - 12);
|
||||
|
||||
|
@ -71,6 +69,7 @@ void __bare_init __naked reset(void)
|
|||
uint32_t r;
|
||||
#ifdef CONFIG_NAND_IMX_BOOT
|
||||
unsigned int *trg, *src;
|
||||
int i;
|
||||
#endif
|
||||
|
||||
common_reset();
|
||||
|
@ -130,7 +129,7 @@ void __bare_init __naked reset(void)
|
|||
|
||||
/* Skip SDRAM initialization if we run from RAM */
|
||||
r = get_pc();
|
||||
if (r > 0x80000000 && r < 0x90000000)
|
||||
if (r > 0x80000000 && r < 0xa0000000)
|
||||
board_init_lowlevel_return();
|
||||
|
||||
/* set to 3.3v SDRAM */
|
||||
|
|
|
@ -1 +1,3 @@
|
|||
obj-y += board.o
|
||||
obj-y += lowlevel.o
|
||||
pbl-y += lowlevel.o
|
||||
|
|
|
@ -50,556 +50,9 @@
|
|||
#include <asm/armlinux.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/omap3-devices.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/sys_info.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/gpmc.h>
|
||||
#include <errno.h>
|
||||
|
||||
/******************** Board Boot Time *******************/
|
||||
static void sdrc_init(void);
|
||||
static void mux_config(void);
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int sdp343x_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(sdp343x_board_init);
|
||||
|
||||
/**
|
||||
* @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* Issue SDRC Soft reset */
|
||||
writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
/* Wait until Reset complete */
|
||||
while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
|
||||
/* SDRC to normal mode */
|
||||
writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC_REG(CS0 Configuration --------- */
|
||||
/* SDRC_REG(MCFG0 register */
|
||||
writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_REG(RFR_CTRL0 register */
|
||||
writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLA0 register */
|
||||
writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLB0 register */
|
||||
writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE cuz of 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_REG(Manual command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register */
|
||||
/* CAS latency = 3 */
|
||||
/* Write Burst = Read Burst */
|
||||
/* Serial Mode */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
/* Enable DLL A */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
/* wait until DLL is locked */
|
||||
while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the pin muxing required for Board operation.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode. Since some versions
|
||||
* of Linux depend on all pin muxing being done at barebox level, we may need to
|
||||
* enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/* Essential MUX Settings */
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */
|
||||
/* GPIO_55 - FLASH_DIS */
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
|
||||
/* GPIO_56 - TORCH_EN */
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
|
||||
/* GPIO_57 - AGPS SLP */
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
|
||||
/* GPMC_58 - WLAN_IRQ */
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */
|
||||
/* GPMC_NADV_ALE */
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */
|
||||
/* GPMC_NBE0_CLE */
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */
|
||||
|
||||
/* SERIAL INTERFACE */
|
||||
/* UART3_CTS_RCTX */
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
/* UART3_RTS_SD */
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
/* UART3_RX_IRRX */
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
/* UART3_TX_IRTX */
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
/* HSUSB0_CLK */
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_STP */
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
|
||||
/* HSUSB0_DIR */
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_NXT */
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA0 */
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA1 */
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA2 */
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA3 */
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA4 */
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA5 */
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA6 */
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA7 */
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */
|
||||
#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
|
||||
/* DSS */
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */
|
||||
/* CAMERA */
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */
|
||||
/* GPIO_98 - CAM_RESET */
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */
|
||||
/* AUDIO INTERFACE */
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */
|
||||
/* MCBSP2_CLKX */
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */
|
||||
/* EXPANSION CARD */
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */
|
||||
/* WIRELESS LAN */
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */
|
||||
/* MMC2_DIR_DAT0 */
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_DIR_DAT1 */
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_DIR_CMD */
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_CLKIN */
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
|
||||
/* BLUETOOTH */
|
||||
/* MCBSP3_DX */
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
|
||||
/* MCBSP3_DR */
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP3_CLKX */
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP3_FSX */
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */
|
||||
/* MODEM INTERFACE */
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */
|
||||
/* SSI1_DAT_RX */
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */
|
||||
/* MCBSP1_CLKR */
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
|
||||
/* GPIO_157 - BT_WKUP */
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
|
||||
/* MCBSP1_DX */
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */
|
||||
/* MCBSP_CLKS */
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
|
||||
/* MCBSP1_FSX */
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP1_CLKX */
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
|
||||
/* SERIAL INTERFACE */
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */
|
||||
/* MCSPI1_CLK */
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_SIMO */
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_SOMI */
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_CS0 */
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
|
||||
/* MCSPI1_CS1 */
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
|
||||
/* GPIO_176-NOR_DPD */
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
|
||||
/* MCSPI1_CS3 */
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
|
||||
/* MCSPI2_CLK */
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_SIMO */
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_SOMI */
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_CS0 */
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
|
||||
/* MCSPI2_CS1 */
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
|
||||
|
||||
/* CONTROL AND DEBUG */
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */
|
||||
/* GPIO_8-LCD_ENBKL */
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
|
||||
/* SYS_OFF_MODE */
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
|
||||
/* SYS_CLKOUT1 */
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */
|
||||
/* HSUSB1_TLL_STP */
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
|
||||
/* HSUSB1_TLL_CLK */
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA0 */
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
|
||||
/* MCSPI3_CS0 */
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
|
||||
/* HSUSB1_TLL_DATA2 */
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
|
||||
/* HSUSB1_TLL_DATA7 */
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
|
||||
/* HSUSB1_TLL_DATA4 */
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA5 */
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA6 */
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA3 */
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DIR */
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_NXT */
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_CLK */
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_STP */
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DIR */
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_NXT */
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DATA0 */
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DATA1 */
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
|
||||
|
||||
/* DIE TO DIE */
|
||||
MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */
|
||||
/* D2D_CLK26MI */
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
|
||||
/* D2D_NRESPWRON */
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
|
||||
/* D2D_NRESWARM */
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
|
||||
/* D2D_ARM9NIRQ */
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_UMA2P6FIQ */
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SPINT */
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
|
||||
/* D2D_FRINT */
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
|
||||
/* D2D_DMAREQ0 */
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ1 */
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ2 */
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ3 */
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTRST */
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTDI */
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTDO */
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTMS */
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTCK */
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GRTCK */
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MSTDBY */
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
|
||||
/* D2D_SWAKEUP */
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
|
||||
/* D2D_IDLEREQ */
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_IDLEACK */
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
|
||||
/* D2D_MWRITE */
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SWRITE */
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MREAD */
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SREAD */
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MBUSFLAG */
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SBUSFLAG */
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
|
||||
/* SDRC_CKE0 */
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
|
||||
/* SDRC_CKE1 NOT USED */
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
|
||||
#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */
|
||||
}
|
||||
|
||||
/******************** Board Run Time *******************/
|
||||
|
||||
/*-----------------------CONSOLE Devices -----------------------------------*/
|
||||
|
||||
#ifdef CONFIG_DRIVER_SERIAL_NS16550
|
||||
|
|
|
@ -0,0 +1,546 @@
|
|||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <sizes.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/sys_info.h>
|
||||
|
||||
/**
|
||||
* @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* Issue SDRC Soft reset */
|
||||
writel(0x12, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* Wait until Reset complete */
|
||||
while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0);
|
||||
/* SDRC to normal mode */
|
||||
writel(0x10, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC_REG(CS0 Configuration --------- */
|
||||
/* SDRC_REG(MCFG0 register */
|
||||
writel(0x02584019, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_REG(RFR_CTRL0 register */
|
||||
writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLA0 register */
|
||||
writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_REG(ACTIM_CTRLB0 register */
|
||||
writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE cuz of 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_REG(Manual command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register */
|
||||
/* CAS latency = 3 */
|
||||
/* Write Burst = Read Burst */
|
||||
/* Serial Mode */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
/* Enable DLL A */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
/* wait until DLL is locked */
|
||||
while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the pin muxing required for Board operation.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode. Since some versions
|
||||
* of Linux depend on all pin muxing being done at barebox level, we may need to
|
||||
* enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/* Essential MUX Settings */
|
||||
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */
|
||||
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */
|
||||
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */
|
||||
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */
|
||||
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */
|
||||
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */
|
||||
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */
|
||||
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */
|
||||
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */
|
||||
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */
|
||||
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */
|
||||
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */
|
||||
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */
|
||||
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */
|
||||
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */
|
||||
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */
|
||||
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */
|
||||
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */
|
||||
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */
|
||||
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */
|
||||
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */
|
||||
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */
|
||||
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */
|
||||
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */
|
||||
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */
|
||||
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */
|
||||
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */
|
||||
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */
|
||||
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */
|
||||
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */
|
||||
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */
|
||||
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */
|
||||
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */
|
||||
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */
|
||||
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */
|
||||
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */
|
||||
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */
|
||||
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */
|
||||
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */
|
||||
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */
|
||||
/* GPIO_55 - FLASH_DIS */
|
||||
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4));
|
||||
/* GPIO_56 - TORCH_EN */
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4));
|
||||
/* GPIO_57 - AGPS SLP */
|
||||
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4));
|
||||
/* GPMC_58 - WLAN_IRQ */
|
||||
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4));
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */
|
||||
/* GPMC_NADV_ALE */
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */
|
||||
/* GPMC_NBE0_CLE */
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */
|
||||
|
||||
/* SERIAL INTERFACE */
|
||||
/* UART3_CTS_RCTX */
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
/* UART3_RTS_SD */
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
/* UART3_RX_IRRX */
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
/* UART3_TX_IRTX */
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
/* HSUSB0_CLK */
|
||||
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_STP */
|
||||
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0));
|
||||
/* HSUSB0_DIR */
|
||||
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_NXT */
|
||||
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA0 */
|
||||
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA1 */
|
||||
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA2 */
|
||||
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA3 */
|
||||
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA4 */
|
||||
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA5 */
|
||||
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA6 */
|
||||
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB0_DATA7 */
|
||||
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */
|
||||
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */
|
||||
#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX
|
||||
/* DSS */
|
||||
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */
|
||||
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */
|
||||
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */
|
||||
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */
|
||||
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */
|
||||
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */
|
||||
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */
|
||||
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */
|
||||
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */
|
||||
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */
|
||||
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */
|
||||
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */
|
||||
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */
|
||||
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */
|
||||
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */
|
||||
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */
|
||||
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */
|
||||
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */
|
||||
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */
|
||||
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */
|
||||
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */
|
||||
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */
|
||||
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */
|
||||
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */
|
||||
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */
|
||||
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */
|
||||
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */
|
||||
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */
|
||||
/* CAMERA */
|
||||
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */
|
||||
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */
|
||||
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */
|
||||
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */
|
||||
/* GPIO_98 - CAM_RESET */
|
||||
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4));
|
||||
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */
|
||||
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */
|
||||
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */
|
||||
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */
|
||||
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */
|
||||
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */
|
||||
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */
|
||||
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */
|
||||
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */
|
||||
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */
|
||||
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */
|
||||
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */
|
||||
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */
|
||||
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */
|
||||
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */
|
||||
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */
|
||||
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */
|
||||
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */
|
||||
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */
|
||||
/* AUDIO INTERFACE */
|
||||
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */
|
||||
/* MCBSP2_CLKX */
|
||||
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */
|
||||
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */
|
||||
/* EXPANSION CARD */
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */
|
||||
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */
|
||||
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */
|
||||
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */
|
||||
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */
|
||||
/* WIRELESS LAN */
|
||||
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */
|
||||
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */
|
||||
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */
|
||||
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */
|
||||
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */
|
||||
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */
|
||||
/* MMC2_DIR_DAT0 */
|
||||
MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_DIR_DAT1 */
|
||||
MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_DIR_CMD */
|
||||
MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1));
|
||||
/* MMC2_CLKIN */
|
||||
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1));
|
||||
/* BLUETOOTH */
|
||||
/* MCBSP3_DX */
|
||||
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0));
|
||||
/* MCBSP3_DR */
|
||||
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP3_CLKX */
|
||||
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP3_FSX */
|
||||
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */
|
||||
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */
|
||||
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */
|
||||
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */
|
||||
/* MODEM INTERFACE */
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */
|
||||
/* SSI1_DAT_RX */
|
||||
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1));
|
||||
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */
|
||||
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */
|
||||
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */
|
||||
/* MCBSP1_CLKR */
|
||||
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0));
|
||||
/* GPIO_157 - BT_WKUP */
|
||||
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4));
|
||||
/* MCBSP1_DX */
|
||||
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */
|
||||
/* MCBSP_CLKS */
|
||||
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0));
|
||||
/* MCBSP1_FSX */
|
||||
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0));
|
||||
/* MCBSP1_CLKX */
|
||||
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0));
|
||||
/* SERIAL INTERFACE */
|
||||
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */
|
||||
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */
|
||||
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */
|
||||
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */
|
||||
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */
|
||||
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */
|
||||
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */
|
||||
/* MCSPI1_CLK */
|
||||
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_SIMO */
|
||||
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_SOMI */
|
||||
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI1_CS0 */
|
||||
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0));
|
||||
/* MCSPI1_CS1 */
|
||||
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0));
|
||||
/* GPIO_176-NOR_DPD */
|
||||
MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4));
|
||||
/* MCSPI1_CS3 */
|
||||
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0));
|
||||
/* MCSPI2_CLK */
|
||||
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_SIMO */
|
||||
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_SOMI */
|
||||
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0));
|
||||
/* MCSPI2_CS0 */
|
||||
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0));
|
||||
/* MCSPI2_CS1 */
|
||||
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0));
|
||||
|
||||
/* CONTROL AND DEBUG */
|
||||
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */
|
||||
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */
|
||||
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */
|
||||
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */
|
||||
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */
|
||||
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */
|
||||
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */
|
||||
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */
|
||||
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */
|
||||
/* GPIO_8-LCD_ENBKL */
|
||||
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4));
|
||||
/* SYS_OFF_MODE */
|
||||
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0));
|
||||
/* SYS_CLKOUT1 */
|
||||
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */
|
||||
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */
|
||||
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */
|
||||
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */
|
||||
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */
|
||||
MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */
|
||||
MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */
|
||||
/* HSUSB1_TLL_STP */
|
||||
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0));
|
||||
/* HSUSB1_TLL_CLK */
|
||||
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA0 */
|
||||
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1));
|
||||
/* MCSPI3_CS0 */
|
||||
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1));
|
||||
/* HSUSB1_TLL_DATA2 */
|
||||
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1));
|
||||
/* HSUSB1_TLL_DATA7 */
|
||||
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1));
|
||||
/* HSUSB1_TLL_DATA4 */
|
||||
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA5 */
|
||||
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA6 */
|
||||
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DATA3 */
|
||||
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_DIR */
|
||||
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB1_TLL_NXT */
|
||||
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_CLK */
|
||||
MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_STP */
|
||||
MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DIR */
|
||||
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_NXT */
|
||||
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DATA0 */
|
||||
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0));
|
||||
/* HSUSB2_TLL_DATA1 */
|
||||
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0));
|
||||
|
||||
/* DIE TO DIE */
|
||||
MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */
|
||||
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */
|
||||
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */
|
||||
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */
|
||||
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */
|
||||
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */
|
||||
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */
|
||||
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */
|
||||
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */
|
||||
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */
|
||||
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */
|
||||
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */
|
||||
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */
|
||||
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */
|
||||
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */
|
||||
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */
|
||||
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */
|
||||
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */
|
||||
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */
|
||||
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */
|
||||
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */
|
||||
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */
|
||||
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */
|
||||
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */
|
||||
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */
|
||||
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */
|
||||
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */
|
||||
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */
|
||||
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */
|
||||
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */
|
||||
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */
|
||||
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */
|
||||
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */
|
||||
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */
|
||||
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */
|
||||
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */
|
||||
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */
|
||||
/* D2D_CLK26MI */
|
||||
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0));
|
||||
/* D2D_NRESPWRON */
|
||||
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0));
|
||||
/* D2D_NRESWARM */
|
||||
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0));
|
||||
/* D2D_ARM9NIRQ */
|
||||
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_UMA2P6FIQ */
|
||||
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SPINT */
|
||||
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0));
|
||||
/* D2D_FRINT */
|
||||
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0));
|
||||
/* D2D_DMAREQ0 */
|
||||
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ1 */
|
||||
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ2 */
|
||||
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0));
|
||||
/* D2D_DMAREQ3 */
|
||||
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTRST */
|
||||
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTDI */
|
||||
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTDO */
|
||||
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTMS */
|
||||
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GTCK */
|
||||
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0));
|
||||
/* D2D_N3GRTCK */
|
||||
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MSTDBY */
|
||||
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0));
|
||||
/* D2D_SWAKEUP */
|
||||
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0));
|
||||
/* D2D_IDLEREQ */
|
||||
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0));
|
||||
/* D2D_IDLEACK */
|
||||
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0));
|
||||
/* D2D_MWRITE */
|
||||
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SWRITE */
|
||||
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MREAD */
|
||||
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SREAD */
|
||||
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0));
|
||||
/* D2D_MBUSFLAG */
|
||||
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0));
|
||||
/* D2D_SBUSFLAG */
|
||||
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0));
|
||||
/* SDRC_CKE0 */
|
||||
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
|
||||
/* SDRC_CKE1 NOT USED */
|
||||
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
|
||||
#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int sdp343x_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(sdp343x_board_init);
|
|
@ -1 +1,3 @@
|
|||
obj-y += board.o
|
||||
obj-y += lowlevel.o
|
||||
pbl-y += lowlevel.o
|
||||
|
|
|
@ -47,170 +47,12 @@
|
|||
#include <ns16550.h>
|
||||
#include <asm/armlinux.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/sys_info.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/gpmc.h>
|
||||
#include <errno.h>
|
||||
#include <generated/mach-types.h>
|
||||
#include <mach/omap3-devices.h>
|
||||
|
||||
|
||||
/*
|
||||
* Boot-time initialization(s)
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the SDRC module
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* SDRAM software reset */
|
||||
/* No idle ack and RESET enable */
|
||||
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
sdelay(100);
|
||||
/* No idle ack and RESET disable */
|
||||
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC Registers Configuration --------- */
|
||||
/* SDRC_MCFG0 register */
|
||||
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_RFR_CTRL0 register */
|
||||
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLA0 register */
|
||||
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLB0 register */
|
||||
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE due to 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_MANUAL command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register Burst length=4 */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
|
||||
* do not have alternate modes. We don't program these pins.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/*
|
||||
* SDRC
|
||||
* - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPMC
|
||||
* - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
|
||||
* - GPMC_NADV_ALE: Default MUX mode is mode0.
|
||||
* - GPMC_NOE: Default MUX mode is mode0.
|
||||
* - GPMC_NWE: Default MUX mode is mode0.
|
||||
* - GPMC_WAIT0: Default MUX mode is mode0.
|
||||
*/
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
|
||||
|
||||
/*
|
||||
* Serial Interface
|
||||
*/
|
||||
#if defined(CONFIG_OMAP3EVM_UART1)
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
|
||||
#elif defined(CONFIG_OMAP3EVM_UART3)
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int omap3_evm_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(omap3_evm_board_init);
|
||||
|
||||
/*
|
||||
* Run-time initialization(s)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DRIVER_SERIAL_NS16550
|
||||
|
||||
/**
|
||||
|
|
|
@ -0,0 +1,160 @@
|
|||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <sizes.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/sys_info.h>
|
||||
|
||||
|
||||
/*
|
||||
* Boot-time initialization(s)
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the SDRC module
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void sdrc_init(void)
|
||||
{
|
||||
/* SDRAM software reset */
|
||||
/* No idle ack and RESET enable */
|
||||
writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
sdelay(100);
|
||||
/* No idle ack and RESET disable */
|
||||
writel(0x18, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* SDRC Sharing register */
|
||||
/* 32-bit SDRAM on data lane [31:0] - CS0 */
|
||||
/* pin tri-stated = 1 */
|
||||
writel(0x00000100, OMAP3_SDRC_REG(SHARING));
|
||||
|
||||
/* ----- SDRC Registers Configuration --------- */
|
||||
/* SDRC_MCFG0 register */
|
||||
writel(0x02584099, OMAP3_SDRC_REG(MCFG_0));
|
||||
|
||||
/* SDRC_RFR_CTRL0 register */
|
||||
writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLA0 register */
|
||||
writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0));
|
||||
|
||||
/* SDRC_ACTIM_CTRLB0 register */
|
||||
writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0));
|
||||
|
||||
/* Disble Power Down of CKE due to 1 CKE on combo part */
|
||||
writel(0x00000081, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* SDRC_MANUAL command register */
|
||||
/* NOP command */
|
||||
writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Precharge command */
|
||||
writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
/* Auto-refresh command */
|
||||
writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0));
|
||||
|
||||
/* SDRC MR0 register Burst length=4 */
|
||||
writel(0x00000032, OMAP3_SDRC_REG(MR_0));
|
||||
|
||||
/* SDRC DLLA control register */
|
||||
writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3
|
||||
* do not have alternate modes. We don't program these pins.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void mux_config(void)
|
||||
{
|
||||
/*
|
||||
* SDRC
|
||||
* - SDRC_D0-SDRC_D31: Default MUX mode is mode0.
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPMC
|
||||
* - GPMC_D0-GPMC_D7: Default MUX mode is mode0.
|
||||
* - GPMC_NADV_ALE: Default MUX mode is mode0.
|
||||
* - GPMC_NOE: Default MUX mode is mode0.
|
||||
* - GPMC_NWE: Default MUX mode is mode0.
|
||||
* - GPMC_WAIT0: Default MUX mode is mode0.
|
||||
*/
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0));
|
||||
|
||||
/*
|
||||
* Serial Interface
|
||||
*/
|
||||
#if defined(CONFIG_OMAP3EVM_UART1)
|
||||
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0));
|
||||
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0));
|
||||
#elif defined(CONFIG_OMAP3EVM_UART3)
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int omap3_evm_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
omap3_core_init();
|
||||
|
||||
mux_config();
|
||||
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(omap3_evm_board_init);
|
|
@ -119,7 +119,6 @@ struct gpio_led panda_leds[] = {
|
|||
|
||||
static void panda_led_init(void)
|
||||
{
|
||||
gpio_direction_output(7, 0);
|
||||
led_gpio_register(&panda_leds[0]);
|
||||
led_set_trigger(LED_TRIGGER_HEARTBEAT, &panda_leds[0].led);
|
||||
}
|
||||
|
|
|
@ -15,3 +15,5 @@
|
|||
#
|
||||
|
||||
obj-y += pca-a-l1.o
|
||||
obj-y += lowlevel.o
|
||||
pbl-y += lowlevel.o
|
||||
|
|
|
@ -0,0 +1,251 @@
|
|||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <init.h>
|
||||
#include <sizes.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/sys_info.h>
|
||||
|
||||
/* Slower full frequency range default timings for x32 operation */
|
||||
#define SDP_SDRC_SHARING 0x00000100
|
||||
/* Diabling power down mode using CKE pin */
|
||||
#define SDP_SDRC_POWER_POP 0x00000081
|
||||
/* rkw - need to find of 90/72 degree recommendation for speed like before. */
|
||||
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
|
||||
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
|
||||
|
||||
/* used to create an array of memory configuartions. */
|
||||
struct sdrc_config {
|
||||
u32 cs_cfg;
|
||||
u32 mcfg;
|
||||
u32 mr;
|
||||
u32 actim_ctrla;
|
||||
u32 actim_ctrlb;
|
||||
u32 rfr_ctrl;
|
||||
} const sdrc_config[] = {
|
||||
/* max cs_size for autodetection, common timing */
|
||||
/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
|
||||
{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
|
||||
/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
|
||||
{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
|
||||
/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
|
||||
{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
|
||||
/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
|
||||
{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
|
||||
};
|
||||
|
||||
/*
|
||||
* Boot-time initialization(s)
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
* init_sdram_ddr() - Init DDR controller.
|
||||
*********************************************************************/
|
||||
void init_sdram_ddr(void)
|
||||
{
|
||||
/* reset sdrc controller */
|
||||
writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
|
||||
writel(0, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* setup sdrc to ball mux */
|
||||
writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
|
||||
writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* set up dll */
|
||||
writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
sdelay(0x2000); /* give time to lock */
|
||||
|
||||
}
|
||||
/*********************************************************************
|
||||
* config_sdram_ddr() - Init DDR on dev board.
|
||||
*********************************************************************/
|
||||
void config_sdram_ddr(u8 cs, u8 cfg)
|
||||
{
|
||||
|
||||
writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
|
||||
writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
|
||||
writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
|
||||
writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
|
||||
|
||||
writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
|
||||
sdelay(5000);
|
||||
|
||||
writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
|
||||
/* set mr0 */
|
||||
writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
|
||||
|
||||
sdelay(2000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SDRC module
|
||||
* Initialisation for 1x256MByte but normally
|
||||
* done by x-loader.
|
||||
* @return void
|
||||
*/
|
||||
static void pcaal1_sdrc_init(void)
|
||||
{
|
||||
u32 test0, test1;
|
||||
char cfg;
|
||||
|
||||
init_sdram_ddr();
|
||||
|
||||
config_sdram_ddr(0, 0); /* 256MByte at CS0 */
|
||||
config_sdram_ddr(1, 0); /* 256MByte at CS1 */
|
||||
|
||||
test0 = get_ram_size((long *) 0x80000000, SZ_256M);
|
||||
test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
|
||||
|
||||
/* mask out lower nible, its not tested with
|
||||
in common/memsize.c */
|
||||
test1 &= 0xfffffff0;
|
||||
|
||||
if ((test1 > 0) && (test1 != test0))
|
||||
hang();
|
||||
|
||||
cfg = -1; /* illegal configuration found */
|
||||
|
||||
if (test1 == 0) {
|
||||
init_sdram_ddr();
|
||||
writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
|
||||
|
||||
/* 1 x 256MByte */
|
||||
if (test0 == SZ_256M)
|
||||
cfg = 2;
|
||||
|
||||
if (cfg != -1) {
|
||||
config_sdram_ddr(0, cfg);
|
||||
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* reinit both cs with correct size */
|
||||
/* 2 x 128MByte */
|
||||
if (test0 == SZ_128M)
|
||||
cfg = 1;
|
||||
/* 2 x 256MByte */
|
||||
if (test0 == SZ_256M)
|
||||
cfg = 3;
|
||||
|
||||
if (cfg != -1) {
|
||||
init_sdram_ddr();
|
||||
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
|
||||
config_sdram_ddr(0, cfg);
|
||||
config_sdram_ddr(1, cfg);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the necessary pin muxing required for phyCARD-A-L1.
|
||||
* Some pins in OMAP3 do not have alternate modes.
|
||||
* We don't program these pins.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void pcaal1_mux_config(void)
|
||||
{
|
||||
/*
|
||||
* Serial Interface
|
||||
*/
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
|
||||
|
||||
/* ETH_PME (GPIO_55) */
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4));
|
||||
/* #CS5 (Ethernet) */
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0));
|
||||
/* ETH_FIFO_SEL (GPIO_57) */
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4));
|
||||
/* ETH_AMDIX_EN (GPIO_58) */
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4));
|
||||
/* ETH_nRST (GPIO_64) */
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4));
|
||||
|
||||
/* HSMMC1 */
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
|
||||
|
||||
/* USBOTG_nRST (GPIO_63) */
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4));
|
||||
|
||||
/* USBH_nRST (GPIO_65) */
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int pcaal1_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
pcaal1_mux_config();
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
pcaal1_sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(pcaal1_board_init);
|
||||
|
|
@ -51,264 +51,17 @@
|
|||
#include <asm/io.h>
|
||||
#include <generated/mach-types.h>
|
||||
#include <linux/err.h>
|
||||
#include <mach/control.h>
|
||||
#include <mach/gpmc.h>
|
||||
#include <mach/gpmc_nand.h>
|
||||
#include <mach/omap_hsmmc.h>
|
||||
#include <mach/xload.h>
|
||||
#include <mach/omap3-mux.h>
|
||||
#include <mach/sdrc.h>
|
||||
#include <mach/omap3-silicon.h>
|
||||
#include <mach/sys_info.h>
|
||||
#include <mach/syslib.h>
|
||||
#include <mach/omap3-devices.h>
|
||||
|
||||
#define SMC911X_BASE 0x2c000000
|
||||
|
||||
/* Slower full frequency range default timings for x32 operation */
|
||||
#define SDP_SDRC_SHARING 0x00000100
|
||||
/* Diabling power down mode using CKE pin */
|
||||
#define SDP_SDRC_POWER_POP 0x00000081
|
||||
/* rkw - need to find of 90/72 degree recommendation for speed like before. */
|
||||
#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
|
||||
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
|
||||
|
||||
/* used to create an array of memory configuartions. */
|
||||
struct sdrc_config {
|
||||
u32 cs_cfg;
|
||||
u32 mcfg;
|
||||
u32 mr;
|
||||
u32 actim_ctrla;
|
||||
u32 actim_ctrlb;
|
||||
u32 rfr_ctrl;
|
||||
} const sdrc_config[] = {
|
||||
/* max cs_size for autodetection, common timing */
|
||||
/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */
|
||||
{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
|
||||
/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */
|
||||
{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201},
|
||||
/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */
|
||||
{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
|
||||
/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */
|
||||
{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201},
|
||||
};
|
||||
|
||||
/*
|
||||
* Boot-time initialization(s)
|
||||
*/
|
||||
|
||||
/*********************************************************************
|
||||
* init_sdram_ddr() - Init DDR controller.
|
||||
*********************************************************************/
|
||||
void init_sdram_ddr(void)
|
||||
{
|
||||
/* reset sdrc controller */
|
||||
writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000);
|
||||
writel(0, OMAP3_SDRC_REG(SYSCONFIG));
|
||||
|
||||
/* setup sdrc to ball mux */
|
||||
writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING));
|
||||
writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER));
|
||||
|
||||
/* set up dll */
|
||||
writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL));
|
||||
sdelay(0x2000); /* give time to lock */
|
||||
|
||||
}
|
||||
/*********************************************************************
|
||||
* config_sdram_ddr() - Init DDR on dev board.
|
||||
*********************************************************************/
|
||||
void config_sdram_ddr(u8 cs, u8 cfg)
|
||||
{
|
||||
|
||||
writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs));
|
||||
writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs));
|
||||
writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs));
|
||||
writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs));
|
||||
|
||||
writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
|
||||
sdelay(5000);
|
||||
|
||||
writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs));
|
||||
|
||||
/* set mr0 */
|
||||
writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs));
|
||||
|
||||
sdelay(2000);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SDRC module
|
||||
* Initialisation for 1x256MByte but normally
|
||||
* done by x-loader.
|
||||
* @return void
|
||||
*/
|
||||
static void pcaal1_sdrc_init(void)
|
||||
{
|
||||
u32 test0, test1;
|
||||
char cfg;
|
||||
|
||||
init_sdram_ddr();
|
||||
|
||||
config_sdram_ddr(0, 0); /* 256MByte at CS0 */
|
||||
config_sdram_ddr(1, 0); /* 256MByte at CS1 */
|
||||
|
||||
test0 = get_ram_size((long *) 0x80000000, SZ_256M);
|
||||
test1 = get_ram_size((long *) 0xA0000000, SZ_256M);
|
||||
|
||||
/* mask out lower nible, its not tested with
|
||||
in common/memsize.c */
|
||||
test1 &= 0xfffffff0;
|
||||
|
||||
if ((test1 > 0) && (test1 != test0))
|
||||
hang();
|
||||
|
||||
cfg = -1; /* illegal configuration found */
|
||||
|
||||
if (test1 == 0) {
|
||||
init_sdram_ddr();
|
||||
writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1));
|
||||
|
||||
/* 1 x 256MByte */
|
||||
if (test0 == SZ_256M)
|
||||
cfg = 2;
|
||||
|
||||
if (cfg != -1) {
|
||||
config_sdram_ddr(0, cfg);
|
||||
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* reinit both cs with correct size */
|
||||
/* 2 x 128MByte */
|
||||
if (test0 == SZ_128M)
|
||||
cfg = 1;
|
||||
/* 2 x 256MByte */
|
||||
if (test0 == SZ_256M)
|
||||
cfg = 3;
|
||||
|
||||
if (cfg != -1) {
|
||||
init_sdram_ddr();
|
||||
writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG));
|
||||
config_sdram_ddr(0, cfg);
|
||||
config_sdram_ddr(1, cfg);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Do the necessary pin muxing required for phyCARD-A-L1.
|
||||
* Some pins in OMAP3 do not have alternate modes.
|
||||
* We don't program these pins.
|
||||
*
|
||||
* See @ref MUX_VAL for description of the muxing mode.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static void pcaal1_mux_config(void)
|
||||
{
|
||||
/*
|
||||
* Serial Interface
|
||||
*/
|
||||
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0));
|
||||
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
|
||||
|
||||
/* GPMC */
|
||||
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
|
||||
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
|
||||
|
||||
/* ETH_PME (GPIO_55) */
|
||||
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4));
|
||||
/* #CS5 (Ethernet) */
|
||||
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0));
|
||||
/* ETH_FIFO_SEL (GPIO_57) */
|
||||
MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4));
|
||||
/* ETH_AMDIX_EN (GPIO_58) */
|
||||
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4));
|
||||
/* ETH_nRST (GPIO_64) */
|
||||
MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4));
|
||||
|
||||
/* HSMMC1 */
|
||||
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
|
||||
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
|
||||
|
||||
/* USBOTG_nRST (GPIO_63) */
|
||||
MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4));
|
||||
|
||||
/* USBH_nRST (GPIO_65) */
|
||||
MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief The basic entry point for board initialization.
|
||||
*
|
||||
* This is called as part of machine init (after arch init).
|
||||
* This is again called with stack in SRAM, so not too many
|
||||
* constructs possible here.
|
||||
*
|
||||
* @return void
|
||||
*/
|
||||
static int pcaal1_board_init(void)
|
||||
{
|
||||
int in_sdram = running_in_sdram();
|
||||
|
||||
if (!in_sdram)
|
||||
omap3_core_init();
|
||||
|
||||
pcaal1_mux_config();
|
||||
/* Dont reconfigure SDRAM while running in SDRAM! */
|
||||
if (!in_sdram)
|
||||
pcaal1_sdrc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
pure_initcall(pcaal1_board_init);
|
||||
|
||||
/*
|
||||
* Run-time initialization(s)
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the serial port to be used as console.
|
||||
*
|
||||
|
|
|
@ -90,7 +90,7 @@ static void pm_add_device_nand(void)
|
|||
|
||||
static struct at91_ether_platform_data macb_pdata = {
|
||||
.is_rmii = 1,
|
||||
.phy_addr = 0,
|
||||
.phy_addr = -1,
|
||||
};
|
||||
|
||||
static void pm9263_phy_init(void)
|
||||
|
|
|
@ -6,7 +6,6 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
|
|||
CONFIG_PBL_IMAGE=y
|
||||
CONFIG_MMU=y
|
||||
CONFIG_TEXT_BASE=0x26f00000
|
||||
CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_MALLOC_TLSF=y
|
||||
CONFIG_PROMPT="9G20-EK:"
|
||||
|
|
|
@ -50,7 +50,6 @@ CONFIG_NET_DHCP=y
|
|||
CONFIG_NET_NFS=y
|
||||
CONFIG_NET_PING=y
|
||||
CONFIG_CMD_TFTP=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_NET_NETCONSOLE=y
|
||||
CONFIG_NET_RESOLV=y
|
||||
CONFIG_DRIVER_NET_FEC_IMX=y
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
CONFIG_ARCH_OMAP=y
|
||||
CONFIG_OMAP_BUILD_IFT=y
|
||||
CONFIG_MACH_BEAGLE=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_THUMB2_BAREBOX=y
|
||||
# CONFIG_CMD_ARM_CPUINFO is not set
|
||||
# CONFIG_ARM_EXCEPTIONS is not set
|
||||
CONFIG_TEXT_BASE=0x40200000
|
||||
|
|
|
@ -57,5 +57,4 @@ CONFIG_DRIVER_NET_SMC91111=y
|
|||
CONFIG_DRIVER_CFI=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_DRIVER_VIDEO_PXA=y
|
||||
CONFIG_FS_TFTP=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
|
|
|
@ -34,6 +34,7 @@ ENDPROC(v7_mmu_cache_on)
|
|||
|
||||
.section .text.v7_mmu_cache_off
|
||||
ENTRY(v7_mmu_cache_off)
|
||||
stmfd sp!, {r0-r7, r9-r11}
|
||||
mrc p15, 0, r0, c1, c0
|
||||
#ifdef CONFIG_MMU
|
||||
bic r0, r0, #0x000d
|
||||
|
@ -50,6 +51,7 @@ ENTRY(v7_mmu_cache_off)
|
|||
mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
|
||||
mcr p15, 0, r0, c7, c10, 4 @ DSB
|
||||
mcr p15, 0, r0, c7, c5, 4 @ ISB
|
||||
ldmfd sp!, {r0-r7, r9-r11}
|
||||
mov pc, r12
|
||||
ENDPROC(v7_mmu_cache_off)
|
||||
|
||||
|
|
|
@ -294,7 +294,7 @@ void mmu_disable(void)
|
|||
__mmu_cache_off();
|
||||
}
|
||||
|
||||
#define PAGE_ALIGN(s) ((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1);
|
||||
#define PAGE_ALIGN(s) (((s) + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))
|
||||
|
||||
void *dma_alloc_coherent(size_t size)
|
||||
{
|
||||
|
|
|
@ -22,6 +22,7 @@ config ARCH_TEXT_BASE
|
|||
hex
|
||||
default 0x73f00000 if ARCH_AT91SAM9G45
|
||||
default 0x26f00000 if ARCH_AT91SAM9X5
|
||||
default 0x20f00000 if ARCH_AT91RM9200
|
||||
default 0x23f00000
|
||||
|
||||
config BOARDINFO
|
||||
|
@ -169,7 +170,7 @@ endchoice
|
|||
config ARCH_BAREBOX_MAX_BARE_INIT_SIZE
|
||||
hex
|
||||
default 0x1000 if ARCH_AT91SAM9260
|
||||
default 0x270000 if ARCH_AT91SAM9261
|
||||
default 0x27000 if ARCH_AT91SAM9261
|
||||
default 0x12000 if ARCH_AT91SAM9263
|
||||
default 0x4000 if ARCH_AT91SAM9G20
|
||||
default 0x3000 if ARCH_AT91SAM9G10
|
||||
|
|
|
@ -155,15 +155,15 @@ static struct i2c_gpio_platform_data pdata_i2c1 = {
|
|||
|
||||
void at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
|
||||
{
|
||||
struct i2c_gpio_platform_data *pdata = &pdata_i2c;
|
||||
struct i2c_gpio_platform_data *pdata;
|
||||
|
||||
i2c_register_board_info(i2c_id, devices, nr_devices);
|
||||
|
||||
switch (i2c_id) {
|
||||
case 0;
|
||||
case 0:
|
||||
pdata = &pdata_i2c0;
|
||||
break;
|
||||
case 1;
|
||||
case 1:
|
||||
pdata = &pdata_i2c1;
|
||||
break;
|
||||
default:
|
||||
|
|
|
@ -147,7 +147,6 @@ static inline struct device_d * at91_register_uart(unsigned id, unsigned pins)
|
|||
struct atmel_mci_platform_data {
|
||||
unsigned slot_b;
|
||||
unsigned bus_width;
|
||||
unsigned host_caps; /* MCI_MODE_* from mci.h */
|
||||
int detect_pin;
|
||||
int wp_pin;
|
||||
};
|
||||
|
|
|
@ -97,5 +97,7 @@ void __noreturn reset_cpu (unsigned long addr)
|
|||
rstc |= PM_RSTC_WRCFG_FULL_RESET;
|
||||
writel(PM_PASSWORD | RESET_TIMEOUT, PM_WDOG);
|
||||
writel(PM_PASSWORD | rstc, PM_RSTC);
|
||||
|
||||
while (1);
|
||||
}
|
||||
EXPORT_SYMBOL(reset_cpu);
|
||||
|
|
|
@ -68,6 +68,7 @@ static int imx25_init(void)
|
|||
add_generic_device("imx_iim", 0, NULL, MX25_IIM_BASE_ADDR, SZ_4K,
|
||||
IORESOURCE_MEM, &imx25_iim_pdata);
|
||||
|
||||
add_generic_device("imx-iomuxv3", 0, NULL, MX25_IOMUXC_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
|
||||
add_generic_device("imx25-ccm", 0, NULL, MX25_CCM_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
|
||||
add_generic_device("imx31-gpt", 0, NULL, MX25_GPT1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
|
||||
add_generic_device("imx31-gpio", 0, NULL, MX25_GPIO1_BASE_ADDR, 0x1000, IORESOURCE_MEM, NULL);
|
||||
|
|
|
@ -2,6 +2,7 @@
|
|||
#include <init.h>
|
||||
#include <memory.h>
|
||||
#include <asm-generic/memory_layout.h>
|
||||
#include <asm-generic/sections.h>
|
||||
|
||||
static int display_meminfo(void)
|
||||
{
|
||||
|
@ -9,13 +10,13 @@ static int display_meminfo(void)
|
|||
ulong mend = mem_malloc_end();
|
||||
ulong msize = mend - mstart + 1;
|
||||
|
||||
debug("barebox code: 0x%p -> 0x%p\n", _stext, _etext);
|
||||
debug("bss segment: 0x%p -> 0x%p\n", __bss_start, __bss_stop);
|
||||
debug("barebox code: 0x%p -> 0x%p\n", _stext, _etext - 1);
|
||||
debug("bss segment: 0x%p -> 0x%p\n", __bss_start, __bss_stop - 1);
|
||||
printf("malloc space: 0x%08lx -> 0x%08lx (size %s)\n",
|
||||
mstart, mend, size_human_readable(msize));
|
||||
#ifdef CONFIG_ARM
|
||||
printf("stack space: 0x%08x -> 0x%08x (size %s)\n",
|
||||
STACK_BASE, STACK_BASE + STACK_SIZE,
|
||||
STACK_BASE, STACK_BASE + STACK_SIZE - 1,
|
||||
size_human_readable(STACK_SIZE));
|
||||
#endif
|
||||
return 0;
|
||||
|
|
|
@ -74,11 +74,11 @@ static int mem_malloc_resource(void)
|
|||
request_sdram_region("barebox",
|
||||
(unsigned long)&_stext,
|
||||
(unsigned long)&_etext -
|
||||
(unsigned long)&_stext + 1);
|
||||
(unsigned long)&_stext);
|
||||
request_sdram_region("bss",
|
||||
(unsigned long)&__bss_start,
|
||||
(unsigned long)&__bss_stop -
|
||||
(unsigned long)&__bss_start + 1);
|
||||
(unsigned long)&__bss_start);
|
||||
#ifdef STACK_BASE
|
||||
request_sdram_region("stack", STACK_BASE, STACK_SIZE);
|
||||
#endif
|
||||
|
|
|
@ -79,7 +79,7 @@ static int __init gpio_keys_probe(struct device_d *dev)
|
|||
pdata->recv_fifo = kfifo_alloc(pdata->fifo_size);
|
||||
|
||||
for (i = 0; i < pdata->nbuttons; i++) {
|
||||
gpio = pdata->buttons->gpio;
|
||||
gpio = pdata->buttons[i].gpio;
|
||||
ret = gpio_request(gpio, "gpio_keys");
|
||||
if (ret) {
|
||||
pr_err("gpio_keys: (%d) can not be requested\n", gpio);
|
||||
|
|
|
@ -244,6 +244,8 @@ static int qt1070_probe(struct device_d *dev)
|
|||
sprintf(buf, "0x%x", chip_id);
|
||||
dev_add_param_fixed(dev, "chip_ip", buf);
|
||||
|
||||
memcpy(data->code, default_code, sizeof(int) * ARRAY_SIZE(default_code));
|
||||
|
||||
ret = qt1070_pdata_init(dev, data);
|
||||
if (ret) {
|
||||
dev_err(dev, "can not get pdata (%d)\n", ret);
|
||||
|
@ -258,7 +260,6 @@ static int qt1070_probe(struct device_d *dev)
|
|||
}
|
||||
data->start = get_time_ns();
|
||||
|
||||
memcpy(data->code, default_code, sizeof(int) * ARRAY_SIZE(default_code));
|
||||
|
||||
data->fifo_size = 50;
|
||||
data->recv_fifo = kfifo_alloc(data->fifo_size);
|
||||
|
|
|
@ -106,6 +106,9 @@ int led_set(struct led *led, unsigned int value)
|
|||
if (value > led->max_value)
|
||||
value = led->max_value;
|
||||
|
||||
if (!led->set)
|
||||
return -ENODEV;
|
||||
|
||||
led->set(led, value);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -1,121 +0,0 @@
|
|||
/*
|
||||
* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_mci.h]
|
||||
*
|
||||
* Copyright (C) 2005 Ivan Kokshaysky
|
||||
* Copyright (C) SAN People
|
||||
*
|
||||
* MultiMedia Card Interface (MCI) registers.
|
||||
* Based on AT91RM9200 datasheet revision F.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef AT91_MCI_H
|
||||
#define AT91_MCI_H
|
||||
|
||||
#define AT91_MCI_CR 0x00 /* Control Register */
|
||||
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
|
||||
#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
|
||||
#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
|
||||
#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
|
||||
#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
|
||||
|
||||
#define AT91_MCI_MR 0x04 /* Mode Register */
|
||||
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
|
||||
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
|
||||
#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
|
||||
#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
|
||||
#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
|
||||
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
|
||||
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
|
||||
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
|
||||
|
||||
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
|
||||
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
|
||||
#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
|
||||
#define AT91_MCI_DTOMUL_1 (0 << 4)
|
||||
#define AT91_MCI_DTOMUL_16 (1 << 4)
|
||||
#define AT91_MCI_DTOMUL_128 (2 << 4)
|
||||
#define AT91_MCI_DTOMUL_256 (3 << 4)
|
||||
#define AT91_MCI_DTOMUL_1K (4 << 4)
|
||||
#define AT91_MCI_DTOMUL_4K (5 << 4)
|
||||
#define AT91_MCI_DTOMUL_64K (6 << 4)
|
||||
#define AT91_MCI_DTOMUL_1M (7 << 4)
|
||||
|
||||
#define AT91_MCI_SDCR 0x0c /* SD Card Register */
|
||||
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
|
||||
#define AT91_MCI_SDCBUS (3 << 6) /* 1-bit, 4-bit, or 8-bit bus */
|
||||
#define AT91_MCI_SDCBUS_1BIT (0 << 6) /* 1-bit bus */
|
||||
#define AT91_MCI_SDCBUS_4BIT (2 << 6) /* 4-bit bus */
|
||||
#define AT91_MCI_SDCBUS_8BIT (3 << 6) /* 8-bit bus */
|
||||
|
||||
#define AT91_MCI_ARGR 0x10 /* Argument Register */
|
||||
|
||||
#define AT91_MCI_CMDR 0x14 /* Command Register */
|
||||
#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
|
||||
#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
|
||||
#define AT91_MCI_RSPTYP_NONE (0 << 6)
|
||||
#define AT91_MCI_RSPTYP_48 (1 << 6)
|
||||
#define AT91_MCI_RSPTYP_136 (2 << 6)
|
||||
#define AT91_MCI_RSPTYP_R1B (3 << 6)
|
||||
#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
|
||||
#define AT91_MCI_SPCMD_NONE (0 << 8)
|
||||
#define AT91_MCI_SPCMD_INIT (1 << 8)
|
||||
#define AT91_MCI_SPCMD_SYNC (2 << 8)
|
||||
#define AT91_MCI_SPCMD_ICMD (4 << 8)
|
||||
#define AT91_MCI_SPCMD_IRESP (5 << 8)
|
||||
#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
|
||||
#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
|
||||
#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
|
||||
#define AT91_MCI_TRCMD_NONE (0 << 16)
|
||||
#define AT91_MCI_TRCMD_START (1 << 16)
|
||||
#define AT91_MCI_TRCMD_STOP (2 << 16)
|
||||
#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
|
||||
#define AT91_MCI_TRDIR_RX (1 << 18) /* Read Transfer Direction */
|
||||
#define AT91_MCI_TRDIR_TX (0 << 18) /* Write Transfer Direction */
|
||||
#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
|
||||
#define AT91_MCI_TRTYP_BLOCK (0 << 19)
|
||||
#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
|
||||
#define AT91_MCI_TRTYP_STREAM (2 << 19)
|
||||
#define AT91_MCI_TRTYP_SDIO_BYTE (4 << 19)
|
||||
#define AT91_MCI_TRTYP_SDIO_BLOCK (5 << 19)
|
||||
|
||||
#define AT91_MCI_BLKR 0x18 /* Block Register */
|
||||
#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
|
||||
#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block length */
|
||||
|
||||
#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
|
||||
#define AT91_MCI_RDR 0x30 /* Receive Data Register */
|
||||
#define AT91_MCI_TDR 0x34 /* Transmit Data Register */
|
||||
|
||||
#define AT91_MCI_SR 0x40 /* Status Register */
|
||||
#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
|
||||
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
|
||||
#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
|
||||
#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
|
||||
#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
|
||||
#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
|
||||
#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
|
||||
#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
|
||||
#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
|
||||
#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
|
||||
#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
|
||||
#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
|
||||
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
|
||||
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
|
||||
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
|
||||
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
|
||||
#define AT91_MCI_RTOE (1 << 20) /* Response Time-out Error */
|
||||
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
|
||||
#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
|
||||
#define AT91_MCI_OVRE (1 << 30) /* Overrun */
|
||||
#define AT91_MCI_UNRE (1 << 31) /* Underrun */
|
||||
|
||||
#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
|
||||
#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
|
||||
#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
|
||||
|
||||
#endif
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* Atmel MultiMedia Card Interface driver
|
||||
*
|
||||
* Copyright (C) 2004-2006 Atmel Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
|
||||
* Registers and bitfields marked with [2] are only available in MCI2
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_MMC_ATMEL_MCI_H__
|
||||
#define __DRIVERS_MMC_ATMEL_MCI_H__
|
||||
|
||||
/* MCI Register Definitions */
|
||||
#define ATMCI_CR 0x0000 /* Control */
|
||||
# define ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
|
||||
# define ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
|
||||
# define ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */
|
||||
# define ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */
|
||||
# define ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */
|
||||
#define ATMCI_MR 0x0004 /* Mode */
|
||||
# define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
|
||||
# define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
|
||||
# define ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
|
||||
# define ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
|
||||
# define ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */
|
||||
# define ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */
|
||||
# define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
|
||||
# define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
|
||||
#define ATMCI_DTOR 0x0008 /* Data Timeout */
|
||||
# define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
|
||||
# define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
|
||||
#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
|
||||
# define ATMCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */
|
||||
# define ATMCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */
|
||||
# define ATMCI_SDCSEL_MASK ( 3 << 0)
|
||||
# define ATMCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
|
||||
# define ATMCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
|
||||
# define ATMCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */
|
||||
# define ATMCI_SDCBUS_MASK ( 3 << 6)
|
||||
#define ATMCI_ARGR 0x0010 /* Command Argument */
|
||||
#define ATMCI_CMDR 0x0014 /* Command */
|
||||
# define ATMCI_CMDR_CMDNB_MASK (0x3f << 0) /* Command Opcode MASK */
|
||||
# define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
|
||||
# define ATMCI_CMDR_RSPTYP ( 3 << 6) /* response mask */
|
||||
# define ATMCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */
|
||||
# define ATMCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */
|
||||
# define ATMCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */
|
||||
# define ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */
|
||||
# define ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */
|
||||
# define ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */
|
||||
# define ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */
|
||||
# define ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */
|
||||
# define ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */
|
||||
# define ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */
|
||||
# define ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
|
||||
# define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
|
||||
# define ATMCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */
|
||||
# define ATMCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */
|
||||
# define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
|
||||
# define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
|
||||
# define ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
|
||||
# define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
|
||||
# define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
|
||||
# define ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */
|
||||
# define ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */
|
||||
#define ATMCI_BLKR 0x0018 /* Block */
|
||||
# define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
|
||||
# define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
|
||||
#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
|
||||
# define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
|
||||
# define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
|
||||
#define ATMCI_RSPR 0x0020 /* Response 0 */
|
||||
#define ATMCI_RSPR1 0x0024 /* Response 1 */
|
||||
#define ATMCI_RSPR2 0x0028 /* Response 2 */
|
||||
#define ATMCI_RSPR3 0x002c /* Response 3 */
|
||||
#define ATMCI_RDR 0x0030 /* Receive Data */
|
||||
#define ATMCI_TDR 0x0034 /* Transmit Data */
|
||||
#define ATMCI_SR 0x0040 /* Status */
|
||||
#define ATMCI_IER 0x0044 /* Interrupt Enable */
|
||||
#define ATMCI_IDR 0x0048 /* Interrupt Disable */
|
||||
#define ATMCI_IMR 0x004c /* Interrupt Mask */
|
||||
# define ATMCI_CMDRDY ( 1 << 0) /* Command Ready */
|
||||
# define ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */
|
||||
# define ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */
|
||||
# define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */
|
||||
# define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
|
||||
# define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
|
||||
# define ATMCI_ENDRX ( 1 << 6) /* End of RX Buffer */
|
||||
# define ATMCI_ENDTX ( 1 << 7) /* End of TX Buffer */
|
||||
# define ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
|
||||
# define ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
|
||||
# define ATMCI_SDIOWAIT ( 1 << 12) /* SDIO Read Wait Operation Status */
|
||||
# define ATMCI_CSRCV ( 1 << 13) /* CE-ATA Completion Signal Received */
|
||||
# define ATMCI_RXBUFF ( 1 << 14) /* RX Buffer Full */
|
||||
# define ATMCI_TXBUFE ( 1 << 15) /* TX Buffer Empty */
|
||||
# define ATMCI_RINDE ( 1 << 16) /* Response Index Error */
|
||||
# define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */
|
||||
# define ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */
|
||||
# define ATMCI_RENDE ( 1 << 19) /* Response End Bit Error */
|
||||
# define ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */
|
||||
# define ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */
|
||||
# define ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */
|
||||
# define ATMCI_CSTOE ( 1 << 23) /* Completion Signal Time-out Error */
|
||||
# define ATMCI_BLKOVRE ( 1 << 24) /* DMA Block Overrun Error */
|
||||
# define ATMCI_DMADONE ( 1 << 25) /* DMA Transfer Done */
|
||||
# define ATMCI_FIFOEMPTY ( 1 << 26) /* FIFO Empty Flag */
|
||||
# define ATMCI_XFRDONE ( 1 << 27) /* Transfer Done Flag */
|
||||
# define ATMCI_ACKRCV ( 1 << 28) /* Boot Operation Acknowledge Received */
|
||||
# define ATMCI_ACKRCVE ( 1 << 29) /* Boot Operation Acknowledge Error */
|
||||
# define ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */
|
||||
# define ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */
|
||||
#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
|
||||
# define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
|
||||
# define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
|
||||
# define ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */
|
||||
#define ATMCI_CFG 0x0054 /* Configuration[2] */
|
||||
# define ATMCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */
|
||||
# define ATMCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */
|
||||
# define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
|
||||
# define ATMCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */
|
||||
#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
|
||||
# define ATMCI_WP_EN ( 1 << 0) /* WP Enable */
|
||||
# define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
|
||||
#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
|
||||
# define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
|
||||
# define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
|
||||
#define ATMCI_VERSION 0x00FC /* Version */
|
||||
#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
|
||||
|
||||
/* This is not including the FIFO Aperture on MCI2 */
|
||||
#define ATMCI_REGS_SIZE 0x100
|
||||
|
||||
/* Register access macros */
|
||||
#define atmci_readl(port,reg) \
|
||||
__raw_readl((port)->regs + reg)
|
||||
#define atmci_writel(port,reg,value) \
|
||||
__raw_writel((value), (port)->regs + reg)
|
||||
|
||||
/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
|
||||
#ifdef CONFIG_AVR32
|
||||
# define ATMCI_PDC_CONNECTED 0
|
||||
#else
|
||||
# define ATMCI_PDC_CONNECTED 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Fix sconfig's burst size according to atmel MCI. We need to convert them as:
|
||||
* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
|
||||
*
|
||||
* This can be done by finding most significant bit set.
|
||||
*/
|
||||
static inline unsigned int atmci_convert_chksize(unsigned int maxburst)
|
||||
{
|
||||
if (maxburst > 1)
|
||||
return fls(maxburst) - 2;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Atmel AT91 MCI driver
|
||||
* Atmel MCI driver
|
||||
*
|
||||
* Copyright (C) 2011 Hubert Feurstein <h.feurstein@gmail.com>
|
||||
*
|
||||
|
@ -25,11 +25,19 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/err.h>
|
||||
|
||||
#include "at91_mci.h"
|
||||
#include "atmel-mci-regs.h"
|
||||
|
||||
struct atmel_mci_host {
|
||||
struct atmel_mci_caps {
|
||||
bool has_cfg_reg;
|
||||
bool has_highspeed;
|
||||
bool has_rwproof;
|
||||
bool has_odd_clk_div;
|
||||
bool need_reset_after_xfer;
|
||||
};
|
||||
|
||||
struct atmel_mci {
|
||||
struct mci_host mci;
|
||||
void __iomem *base;
|
||||
void __iomem *regs;
|
||||
struct device_d *hw_dev;
|
||||
struct clk *clk;
|
||||
|
||||
|
@ -37,89 +45,105 @@ struct atmel_mci_host {
|
|||
struct mci_cmd *cmd;
|
||||
struct mci_data *data;
|
||||
unsigned slot_b;
|
||||
int version;
|
||||
struct atmel_mci_caps caps;
|
||||
|
||||
unsigned long bus_hz;
|
||||
u32 mode_reg;
|
||||
u32 cfg_reg;
|
||||
u32 sdc_reg;
|
||||
bool need_reset;
|
||||
};
|
||||
|
||||
#define to_mci_host(mci) container_of(mci, struct atmel_mci_host, mci)
|
||||
#define to_mci_host(mci) container_of(mci, struct atmel_mci, mci)
|
||||
|
||||
#define STATUS_ERROR_MASK (AT91_MCI_RINDE \
|
||||
| AT91_MCI_RDIRE \
|
||||
| AT91_MCI_RCRCE \
|
||||
| AT91_MCI_RENDE \
|
||||
| AT91_MCI_RTOE \
|
||||
| AT91_MCI_DCRCE \
|
||||
| AT91_MCI_DTOE \
|
||||
| AT91_MCI_OVRE \
|
||||
| AT91_MCI_UNRE)
|
||||
#define STATUS_ERROR_MASK (ATMCI_RINDE \
|
||||
| ATMCI_RDIRE \
|
||||
| ATMCI_RCRCE \
|
||||
| ATMCI_RENDE \
|
||||
| ATMCI_RTOE \
|
||||
| ATMCI_DCRCE \
|
||||
| ATMCI_DTOE \
|
||||
| ATMCI_OVRE \
|
||||
| ATMCI_UNRE)
|
||||
|
||||
static inline u32 atmel_mci_readl(struct atmel_mci_host *host, u32 offset)
|
||||
static void atmci_set_clk_rate(struct atmel_mci *host,
|
||||
unsigned int clock_min)
|
||||
{
|
||||
return readl(host->base + offset);
|
||||
}
|
||||
unsigned int clkdiv;
|
||||
|
||||
static inline void atmel_mci_writel(struct atmel_mci_host *host, u32 offset,
|
||||
u32 value)
|
||||
{
|
||||
writel(value, host->base + offset);
|
||||
}
|
||||
|
||||
static void atmel_mci_reset(struct atmel_mci_host *host)
|
||||
{
|
||||
atmel_mci_writel(host, AT91_MCI_CR, AT91_MCI_SWRST | AT91_MCI_MCIDIS);
|
||||
atmel_mci_writel(host, AT91_MCI_DTOR, 0x7f);
|
||||
atmel_mci_writel(host, AT91_MCI_IDR, ~0UL);
|
||||
}
|
||||
|
||||
static void atmel_set_clk_rate(struct atmel_mci_host *host,
|
||||
unsigned int clk_ios)
|
||||
{
|
||||
unsigned int divider;
|
||||
unsigned int clk_in = clk_get_rate(host->clk);
|
||||
|
||||
if (clk_ios > 0) {
|
||||
divider = (clk_in / clk_ios) / 2;
|
||||
if (divider > 0)
|
||||
divider -= 1;
|
||||
if (!host->mode_reg) {
|
||||
clk_enable(host->clk);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
}
|
||||
|
||||
if (clk_ios == 0 || divider > 255)
|
||||
divider = 255;
|
||||
if (host->caps.has_odd_clk_div) {
|
||||
clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
|
||||
if (clkdiv > 511) {
|
||||
dev_dbg(host->hw_dev,
|
||||
"clock %u too slow; using %lu\n",
|
||||
clock_min, host->bus_hz / (511 + 2));
|
||||
clkdiv = 511;
|
||||
}
|
||||
host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
|
||||
| ATMCI_MR_CLKODD(clkdiv & 1);
|
||||
} else {
|
||||
clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
|
||||
if (clkdiv > 255) {
|
||||
dev_dbg(host->hw_dev,
|
||||
"clock %u too slow; using %lu\n",
|
||||
clock_min, host->bus_hz / (2 * 256));
|
||||
clkdiv = 255;
|
||||
}
|
||||
host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
|
||||
}
|
||||
|
||||
dev_dbg(host->hw_dev, "atmel_set_clk_rate: clkIn=%d clkIos=%d divider=%d\n",
|
||||
clk_in, clk_ios, divider);
|
||||
dev_dbg(host->hw_dev, "atmel_set_clk_rate: clkIn=%ld clkIos=%d divider=%d\n",
|
||||
host->bus_hz, clock_min, clkdiv);
|
||||
|
||||
atmel_mci_writel(host, AT91_MCI_MR, (AT91_MCI_CLKDIV & divider)
|
||||
| AT91_MCI_RDPROOF | AT91_MCI_WRPROOF);
|
||||
/*
|
||||
* WRPROOF and RDPROOF prevent overruns/underruns by
|
||||
* stopping the clock when the FIFO is full/empty.
|
||||
* This state is not expected to last for long.
|
||||
*/
|
||||
if (host->caps.has_rwproof)
|
||||
host->mode_reg |= ATMCI_MR_RDPROOF | ATMCI_MR_WRPROOF;
|
||||
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
}
|
||||
|
||||
static int atmel_poll_status(struct atmel_mci_host *host, u32 mask)
|
||||
static int atmci_poll_status(struct atmel_mci *host, u32 mask)
|
||||
{
|
||||
u32 stat;
|
||||
uint64_t start = get_time_ns();
|
||||
|
||||
do {
|
||||
stat = atmel_mci_readl(host, AT91_MCI_SR);
|
||||
stat = atmci_readl(host, ATMCI_SR);
|
||||
if (stat & STATUS_ERROR_MASK)
|
||||
return stat;
|
||||
if (is_timeout(start, SECOND)) {
|
||||
dev_err(host->hw_dev, "timeout\n");
|
||||
return AT91_MCI_RTOE | stat;
|
||||
host->need_reset = true;
|
||||
return ATMCI_RTOE | stat;
|
||||
}
|
||||
if (stat & mask)
|
||||
return 0;
|
||||
} while (1);
|
||||
}
|
||||
|
||||
static int atmel_pull(struct atmel_mci_host *host, void *_buf, int bytes)
|
||||
static int atmci_pull(struct atmel_mci *host, void *_buf, int bytes)
|
||||
{
|
||||
unsigned int stat;
|
||||
u32 *buf = _buf;
|
||||
|
||||
while (bytes > 3) {
|
||||
stat = atmel_poll_status(host, AT91_MCI_RXRDY);
|
||||
stat = atmci_poll_status(host, ATMCI_RXRDY);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
*buf++ = atmel_mci_readl(host, AT91_MCI_RDR);
|
||||
*buf++ = atmci_readl(host, ATMCI_RDR);
|
||||
bytes -= 4;
|
||||
}
|
||||
|
||||
|
@ -130,21 +154,21 @@ static int atmel_pull(struct atmel_mci_host *host, void *_buf, int bytes)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_MCI_WRITE
|
||||
static int atmel_push(struct atmel_mci_host *host, const void *_buf, int bytes)
|
||||
static int atmci_push(struct atmel_mci *host, const void *_buf, int bytes)
|
||||
{
|
||||
unsigned int stat;
|
||||
const u32 *buf = _buf;
|
||||
|
||||
while (bytes > 3) {
|
||||
stat = atmel_poll_status(host, AT91_MCI_TXRDY);
|
||||
stat = atmci_poll_status(host, ATMCI_TXRDY);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
atmel_mci_writel(host, AT91_MCI_TDR, *buf++);
|
||||
atmci_writel(host, ATMCI_TDR, *buf++);
|
||||
bytes -= 4;
|
||||
}
|
||||
|
||||
stat = atmel_poll_status(host, AT91_MCI_TXRDY);
|
||||
stat = atmci_poll_status(host, ATMCI_TXRDY);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
|
@ -155,7 +179,7 @@ static int atmel_push(struct atmel_mci_host *host, const void *_buf, int bytes)
|
|||
}
|
||||
#endif /* CONFIG_MCI_WRITE */
|
||||
|
||||
static int atmel_transfer_data(struct atmel_mci_host *host)
|
||||
static int atmci_transfer_data(struct atmel_mci *host)
|
||||
{
|
||||
struct mci_data *data = host->data;
|
||||
int stat;
|
||||
|
@ -165,23 +189,23 @@ static int atmel_transfer_data(struct atmel_mci_host *host)
|
|||
host->datasize = 0;
|
||||
|
||||
if (data->flags & MMC_DATA_READ) {
|
||||
stat = atmel_pull(host, data->dest, length);
|
||||
stat = atmci_pull(host, data->dest, length);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
stat = atmel_poll_status(host, AT91_MCI_NOTBUSY);
|
||||
stat = atmci_poll_status(host, ATMCI_NOTBUSY);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
host->datasize += length;
|
||||
} else {
|
||||
#ifdef CONFIG_MCI_WRITE
|
||||
stat = atmel_push(host, (const void *)(data->src), length);
|
||||
stat = atmci_push(host, (const void *)(data->src), length);
|
||||
if (stat)
|
||||
return stat;
|
||||
|
||||
host->datasize += length;
|
||||
stat = atmel_poll_status(host, AT91_MCI_NOTBUSY);
|
||||
stat = atmci_poll_status(host, ATMCI_NOTBUSY);
|
||||
if (stat)
|
||||
return stat;
|
||||
#endif /* CONFIG_MCI_WRITE */
|
||||
|
@ -189,21 +213,21 @@ static int atmel_transfer_data(struct atmel_mci_host *host)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void atmel_finish_request(struct atmel_mci_host *host)
|
||||
static void atmci_finish_request(struct atmel_mci *host)
|
||||
{
|
||||
host->cmd = NULL;
|
||||
host->data = NULL;
|
||||
}
|
||||
|
||||
static int atmel_finish_data(struct atmel_mci_host *host, unsigned int stat)
|
||||
static int atmci_finish_data(struct atmel_mci *host, unsigned int stat)
|
||||
{
|
||||
int data_error = 0;
|
||||
|
||||
if (stat & STATUS_ERROR_MASK) {
|
||||
dev_err(host->hw_dev, "request failed (status=0x%08x)\n", stat);
|
||||
if (stat & AT91_MCI_DCRCE)
|
||||
if (stat & ATMCI_DCRCE)
|
||||
data_error = -EILSEQ;
|
||||
else if (stat & (AT91_MCI_RTOE | AT91_MCI_DTOE))
|
||||
else if (stat & (ATMCI_RTOE | ATMCI_DTOE))
|
||||
data_error = -ETIMEDOUT;
|
||||
else
|
||||
data_error = -EIO;
|
||||
|
@ -214,7 +238,7 @@ static int atmel_finish_data(struct atmel_mci_host *host, unsigned int stat)
|
|||
return data_error;
|
||||
}
|
||||
|
||||
static void atmel_setup_data(struct atmel_mci_host *host, struct mci_data *data)
|
||||
static void atmci_setup_data(struct atmel_mci *host, struct mci_data *data)
|
||||
{
|
||||
unsigned int nob = data->blocks;
|
||||
unsigned int blksz = data->blocksize;
|
||||
|
@ -228,13 +252,13 @@ static void atmel_setup_data(struct atmel_mci_host *host, struct mci_data *data)
|
|||
dev_dbg(host->hw_dev, "atmel_setup_data: nob=%d blksz=%d\n",
|
||||
nob, blksz);
|
||||
|
||||
atmel_mci_writel(host, AT91_MCI_BLKR, AT91_MCI_BLKR_BCNT(nob)
|
||||
| AT91_MCI_BLKR_BLKLEN(blksz));
|
||||
atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(nob)
|
||||
| ATMCI_BLKLEN(blksz));
|
||||
|
||||
host->datasize = datasize;
|
||||
}
|
||||
|
||||
static int atmel_read_response(struct atmel_mci_host *host, unsigned int stat)
|
||||
static int atmci_read_response(struct atmel_mci *host, unsigned int stat)
|
||||
{
|
||||
struct mci_cmd *cmd = host->cmd;
|
||||
int i;
|
||||
|
@ -243,10 +267,10 @@ static int atmel_read_response(struct atmel_mci_host *host, unsigned int stat)
|
|||
if (!cmd)
|
||||
return 0;
|
||||
|
||||
if (stat & (AT91_MCI_RTOE | AT91_MCI_DTOE)) {
|
||||
if (stat & (ATMCI_RTOE | ATMCI_DTOE)) {
|
||||
dev_err(host->hw_dev, "command/data timeout\n");
|
||||
return -ETIMEDOUT;
|
||||
} else if ((stat & AT91_MCI_RCRCE) && (cmd->resp_type & MMC_RSP_CRC)) {
|
||||
} else if ((stat & ATMCI_RCRCE) && (cmd->resp_type & MMC_RSP_CRC)) {
|
||||
dev_err(host->hw_dev, "cmd crc error\n");
|
||||
return -EILSEQ;
|
||||
}
|
||||
|
@ -254,39 +278,39 @@ static int atmel_read_response(struct atmel_mci_host *host, unsigned int stat)
|
|||
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
||||
if (cmd->resp_type & MMC_RSP_136) {
|
||||
for (i = 0; i < 4; i++)
|
||||
resp[i] = atmel_mci_readl(host, AT91_MCI_RSPR(0));
|
||||
resp[i] = atmci_readl(host, ATMCI_RSPR);
|
||||
} else {
|
||||
resp[0] = atmel_mci_readl(host, AT91_MCI_RSPR(0));
|
||||
resp[0] = atmci_readl(host, ATMCI_RSPR);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_cmd_done(struct atmel_mci_host *host, unsigned int stat)
|
||||
static int atmci_cmd_done(struct atmel_mci *host, unsigned int stat)
|
||||
{
|
||||
int datastat;
|
||||
int ret;
|
||||
|
||||
ret = atmel_read_response(host, stat);
|
||||
ret = atmci_read_response(host, stat);
|
||||
|
||||
if (ret) {
|
||||
atmel_finish_request(host);
|
||||
atmci_finish_request(host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (!host->data) {
|
||||
atmel_finish_request(host);
|
||||
atmci_finish_request(host);
|
||||
return 0;
|
||||
}
|
||||
|
||||
datastat = atmel_transfer_data(host);
|
||||
ret = atmel_finish_data(host, datastat);
|
||||
atmel_finish_request(host);
|
||||
datastat = atmci_transfer_data(host);
|
||||
ret = atmci_finish_data(host, datastat);
|
||||
atmci_finish_request(host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int atmel_start_cmd(struct atmel_mci_host *host, struct mci_cmd *cmd,
|
||||
static int atmci_start_cmd(struct atmel_mci *host, struct mci_cmd *cmd,
|
||||
unsigned int cmdat)
|
||||
{
|
||||
unsigned flags = 0;
|
||||
|
@ -295,47 +319,47 @@ static int atmel_start_cmd(struct atmel_mci_host *host, struct mci_cmd *cmd,
|
|||
if (host->cmd != NULL)
|
||||
dev_err(host->hw_dev, "error!\n");
|
||||
|
||||
if ((atmel_mci_readl(host, AT91_MCI_SR) & AT91_MCI_CMDRDY) == 0) {
|
||||
if ((atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY) == 0) {
|
||||
dev_err(host->hw_dev, "mci not ready!\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
host->cmd = cmd;
|
||||
cmdval = AT91_MCI_CMDNB & cmd->cmdidx;
|
||||
cmdval = ATMCI_CMDR_CMDNB_MASK & cmd->cmdidx;
|
||||
|
||||
switch (cmd->resp_type) {
|
||||
case MMC_RSP_R1: /* short CRC, OPCODE */
|
||||
case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
|
||||
flags |= AT91_MCI_RSPTYP_48;
|
||||
flags |= ATMCI_CMDR_RSPTYP_48BIT;
|
||||
break;
|
||||
case MMC_RSP_R2: /* long 136 bit + CRC */
|
||||
flags |= AT91_MCI_RSPTYP_136;
|
||||
flags |= ATMCI_CMDR_RSPTYP_136BIT;
|
||||
break;
|
||||
case MMC_RSP_R3: /* short */
|
||||
flags |= AT91_MCI_RSPTYP_48;
|
||||
flags |= ATMCI_CMDR_RSPTYP_48BIT;
|
||||
break;
|
||||
case MMC_RSP_NONE:
|
||||
flags |= AT91_MCI_RSPTYP_NONE;
|
||||
flags |= ATMCI_CMDR_RSPTYP_NONE;
|
||||
break;
|
||||
default:
|
||||
dev_err(host->hw_dev, "unhandled response type 0x%x\n",
|
||||
cmd->resp_type);
|
||||
return -EINVAL;
|
||||
}
|
||||
cmdval |= AT91_MCI_RSPTYP & flags;
|
||||
cmdval |= cmdat & ~(AT91_MCI_CMDNB | AT91_MCI_RSPTYP);
|
||||
cmdval |= ATMCI_CMDR_RSPTYP & flags;
|
||||
cmdval |= cmdat & ~(ATMCI_CMDR_CMDNB_MASK | ATMCI_CMDR_RSPTYP);
|
||||
|
||||
atmel_mci_writel(host, AT91_MCI_ARGR, cmd->cmdarg);
|
||||
atmel_mci_writel(host, AT91_MCI_CMDR, cmdval);
|
||||
atmci_writel(host, ATMCI_ARGR, cmd->cmdarg);
|
||||
atmci_writel(host, ATMCI_CMDR, cmdval);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** init the host interface */
|
||||
static int mci_reset(struct mci_host *mci, struct device_d *mci_dev)
|
||||
static int atmci_reset(struct mci_host *mci, struct device_d *mci_dev)
|
||||
{
|
||||
int ret;
|
||||
struct atmel_mci_host *host = to_mci_host(mci);
|
||||
struct atmel_mci *host = to_mci_host(mci);
|
||||
struct atmel_mci_platform_data *pd = host->hw_dev->platform_data;
|
||||
|
||||
ret = gpio_get_value(pd->detect_pin);
|
||||
|
@ -345,79 +369,102 @@ static int mci_reset(struct mci_host *mci, struct device_d *mci_dev)
|
|||
return -ENODEV;
|
||||
|
||||
clk_enable(host->clk);
|
||||
atmel_mci_reset(host);
|
||||
atmci_writel(host, ATMCI_DTOR, 0x7f);
|
||||
clk_disable(host->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/** change host interface settings */
|
||||
static void mci_set_ios(struct mci_host *mci, struct mci_ios *ios)
|
||||
static void atmci_set_ios(struct mci_host *mci, struct mci_ios *ios)
|
||||
{
|
||||
struct atmel_mci_host *host = to_mci_host(mci);
|
||||
struct atmel_mci *host = to_mci_host(mci);
|
||||
|
||||
dev_dbg(host->hw_dev, "atmel_mci_set_ios: bus_width=%d clk=%d\n",
|
||||
ios->bus_width, ios->clock);
|
||||
|
||||
host->sdc_reg &= ~ATMCI_SDCBUS_MASK;
|
||||
switch (ios->bus_width) {
|
||||
case MMC_BUS_WIDTH_4:
|
||||
atmel_mci_writel(host, AT91_MCI_SDCR, AT91_MCI_SDCBUS_4BIT);
|
||||
host->sdc_reg |= ATMCI_SDCBUS_4BIT;
|
||||
break;
|
||||
case MMC_BUS_WIDTH_8:
|
||||
atmel_mci_writel(host, AT91_MCI_SDCR, AT91_MCI_SDCBUS_8BIT);
|
||||
host->sdc_reg |= ATMCI_SDCBUS_8BIT;
|
||||
break;
|
||||
case MMC_BUS_WIDTH_1:
|
||||
atmel_mci_writel(host, AT91_MCI_SDCR, AT91_MCI_SDCBUS_1BIT);
|
||||
host->sdc_reg |= ATMCI_SDCBUS_1BIT;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
atmel_mci_writel(host, AT91_MCI_SDCR, atmel_mci_readl(host, AT91_MCI_SDCR)
|
||||
| host->slot_b);
|
||||
|
||||
if (ios->clock) {
|
||||
atmel_set_clk_rate(host, ios->clock);
|
||||
atmel_mci_writel(host, AT91_MCI_CR, AT91_MCI_MCIEN
|
||||
);
|
||||
atmci_set_clk_rate(host, ios->clock);
|
||||
|
||||
if (host->caps.has_cfg_reg) {
|
||||
/* setup High Speed mode in relation with card capacity */
|
||||
if (ios->timing == MMC_TIMING_SD_HS)
|
||||
host->cfg_reg |= ATMCI_CFG_HSMODE;
|
||||
else
|
||||
host->cfg_reg &= ~ATMCI_CFG_HSMODE;
|
||||
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
}
|
||||
} else {
|
||||
atmel_mci_writel(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
|
||||
if (host->mode_reg) {
|
||||
atmci_readl(host, ATMCI_MR);
|
||||
clk_disable(host->clk);
|
||||
}
|
||||
host->mode_reg = 0;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/** handle a command */
|
||||
static int mci_request(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
|
||||
static int atmci_request(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
|
||||
{
|
||||
struct atmel_mci_host *host = to_mci_host(mci);
|
||||
struct atmel_mci *host = to_mci_host(mci);
|
||||
u32 stat, cmdat = 0;
|
||||
int ret;
|
||||
|
||||
if (host->need_reset || host->caps.need_reset_after_xfer) {
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
||||
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
||||
if (host->caps.has_cfg_reg)
|
||||
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
||||
host->need_reset = false;
|
||||
}
|
||||
atmci_writel(host, ATMCI_SDCR, host->sdc_reg);
|
||||
|
||||
if (cmd->resp_type != MMC_RSP_NONE)
|
||||
cmdat |= AT91_MCI_MAXLAT;
|
||||
cmdat |= ATMCI_CMDR_MAXLAT_64CYC;
|
||||
|
||||
if (data) {
|
||||
atmel_setup_data(host, data);
|
||||
atmci_setup_data(host, data);
|
||||
|
||||
cmdat |= AT91_MCI_TRCMD_START | AT91_MCI_TRTYP_MULTIPLE;
|
||||
cmdat |= ATMCI_CMDR_START_XFER | ATMCI_CMDR_MULTI_BLOCK;
|
||||
|
||||
if (data->flags & MMC_DATA_READ)
|
||||
cmdat |= AT91_MCI_TRDIR_RX;
|
||||
cmdat |= ATMCI_CMDR_TRDIR_READ;
|
||||
}
|
||||
|
||||
ret = atmel_start_cmd(host, cmd, cmdat);
|
||||
ret = atmci_start_cmd(host, cmd, cmdat);
|
||||
if (ret) {
|
||||
atmel_finish_request(host);
|
||||
atmci_finish_request(host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
stat = atmel_poll_status(host, AT91_MCI_CMDRDY);
|
||||
return atmel_cmd_done(host, stat);
|
||||
stat = atmci_poll_status(host, ATMCI_CMDRDY);
|
||||
return atmci_cmd_done(host, stat);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MCI_INFO
|
||||
static void mci_info(struct device_d *mci_dev)
|
||||
static void atmci_info(struct device_d *mci_dev)
|
||||
{
|
||||
struct atmel_mci_host *host = mci_dev->priv;
|
||||
struct atmel_mci *host = mci_dev->priv;
|
||||
struct atmel_mci_platform_data *pd = host->hw_dev->platform_data;
|
||||
|
||||
printf(" Bus data width: %d bit\n", host->mci.bus_width);
|
||||
|
@ -434,68 +481,140 @@ static void mci_info(struct device_d *mci_dev)
|
|||
printf("- %u Hz upper limit", host->mci.f_max);
|
||||
|
||||
printf("\n Card detection support: %s\n",
|
||||
pd->detect_pin != 0 ? "yes" : "no");
|
||||
gpio_is_valid(pd->detect_pin) ? "yes" : "no");
|
||||
|
||||
}
|
||||
#endif /* CONFIG_MCI_INFO */
|
||||
|
||||
static int mci_probe(struct device_d *hw_dev)
|
||||
/*
|
||||
* HSMCI (High Speed MCI) module is not fully compatible with MCI module.
|
||||
* HSMCI provides DMA support and a new config register but no more supports
|
||||
* PDC.
|
||||
*/
|
||||
static void atmci_get_cap(struct atmel_mci *host)
|
||||
{
|
||||
unsigned long clk_rate;
|
||||
struct atmel_mci_host *host;
|
||||
unsigned int version;
|
||||
|
||||
version = atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
|
||||
host->version = version;
|
||||
|
||||
dev_info(host->hw_dev, "version: 0x%x\n", version);
|
||||
|
||||
host->caps.has_cfg_reg = 0;
|
||||
host->caps.has_highspeed = 0;
|
||||
host->caps.need_reset_after_xfer = 1;
|
||||
|
||||
switch (version & 0xf00) {
|
||||
case 0x500:
|
||||
host->caps.has_odd_clk_div = 1;
|
||||
case 0x400:
|
||||
case 0x300:
|
||||
host->caps.has_cfg_reg = 1;
|
||||
host->caps.has_highspeed = 1;
|
||||
case 0x200:
|
||||
host->caps.has_rwproof = 1;
|
||||
case 0x100:
|
||||
host->caps.need_reset_after_xfer = 0;
|
||||
case 0x0:
|
||||
break;
|
||||
default:
|
||||
dev_warn(host->hw_dev,
|
||||
"Unmanaged mci version, set minimum capabilities\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int atmci_probe(struct device_d *hw_dev)
|
||||
{
|
||||
struct atmel_mci *host;
|
||||
struct atmel_mci_platform_data *pd = hw_dev->platform_data;
|
||||
int ret;
|
||||
|
||||
if (!pd) {
|
||||
dev_err(hw_dev, "missing platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (gpio_is_valid(pd->detect_pin)) {
|
||||
ret = gpio_request(pd->detect_pin, "mci_cd");
|
||||
if (ret) {
|
||||
dev_err(hw_dev, "Impossible to request CD gpio %d (%d)\n",
|
||||
ret, pd->detect_pin);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = gpio_direction_input(pd->detect_pin);
|
||||
if (ret) {
|
||||
dev_err(hw_dev, "Impossible to configure CD gpio %d as input (%d)\n",
|
||||
ret, pd->detect_pin);
|
||||
goto err_gpio_cd_request;
|
||||
}
|
||||
}
|
||||
|
||||
host = xzalloc(sizeof(*host));
|
||||
host->mci.send_cmd = mci_request;
|
||||
host->mci.set_ios = mci_set_ios;
|
||||
host->mci.init = mci_reset;
|
||||
host->mci.send_cmd = atmci_request;
|
||||
host->mci.set_ios = atmci_set_ios;
|
||||
host->mci.init = atmci_reset;
|
||||
host->mci.hw_dev = hw_dev;
|
||||
|
||||
host->mci.host_caps = pd->host_caps;
|
||||
if (pd->bus_width >= 4)
|
||||
host->mci.host_caps |= MMC_MODE_4BIT;
|
||||
if (pd->bus_width == 8)
|
||||
host->mci.host_caps |= MMC_MODE_8BIT;
|
||||
host->slot_b = pd->slot_b;
|
||||
|
||||
host->base = dev_request_mem_region(hw_dev, 0);
|
||||
host->regs = dev_request_mem_region(hw_dev, 0);
|
||||
host->hw_dev = hw_dev;
|
||||
hw_dev->priv = host;
|
||||
host->clk = clk_get(hw_dev, "mci_clk");
|
||||
if (IS_ERR(host->clk)) {
|
||||
dev_err(hw_dev, "no mci_clk\n");
|
||||
return PTR_ERR(host->clk);
|
||||
ret = PTR_ERR(host->clk);
|
||||
goto err_gpio_cd_request;
|
||||
}
|
||||
|
||||
clk_rate = clk_get_rate(host->clk);
|
||||
clk_enable(host->clk);
|
||||
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
||||
atmci_writel(host, ATMCI_IDR, ~0UL);
|
||||
host->bus_hz = clk_get_rate(host->clk);
|
||||
clk_disable(host->clk);
|
||||
|
||||
host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
|
||||
host->mci.f_min = clk_rate >> 9;
|
||||
host->mci.f_max = clk_rate >> 1;
|
||||
host->mci.f_min = DIV_ROUND_UP(host->bus_hz, 512);
|
||||
host->mci.f_max = host->bus_hz >> 1;
|
||||
|
||||
atmci_get_cap(host);
|
||||
|
||||
if (host->caps.has_highspeed)
|
||||
host->mci.host_caps |= MMC_MODE_HS;
|
||||
|
||||
if (host->slot_b)
|
||||
host->sdc_reg = ATMCI_SDCSEL_SLOT_B;
|
||||
else
|
||||
host->sdc_reg = ATMCI_SDCSEL_SLOT_A;
|
||||
|
||||
mci_register(&host->mci);
|
||||
|
||||
return 0;
|
||||
|
||||
err_gpio_cd_request:
|
||||
if (gpio_is_valid(pd->detect_pin))
|
||||
gpio_free(pd->detect_pin);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct driver_d atmel_mci_driver = {
|
||||
static struct driver_d atmci_driver = {
|
||||
.name = "atmel_mci",
|
||||
.probe = mci_probe,
|
||||
.probe = atmci_probe,
|
||||
#ifdef CONFIG_MCI_INFO
|
||||
.info = mci_info,
|
||||
.info = atmci_info,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int atmel_mci_init_driver(void)
|
||||
static int atmci_init_driver(void)
|
||||
{
|
||||
platform_driver_register(&atmel_mci_driver);
|
||||
platform_driver_register(&atmci_driver);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(atmel_mci_init_driver);
|
||||
device_initcall(atmci_init_driver);
|
||||
|
|
|
@ -114,7 +114,9 @@ int mtd_ioctl(struct cdev *cdev, int request, void *buf)
|
|||
struct mtd_ecc_stats *ecc = buf;
|
||||
#endif
|
||||
struct region_info_user *reg = buf;
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
struct erase_info_user *ei = buf;
|
||||
#endif
|
||||
loff_t *offset = buf;
|
||||
|
||||
switch (request) {
|
||||
|
|
|
@ -487,9 +487,9 @@ struct device_node *of_find_node_by_path(const char *path)
|
|||
|
||||
list_for_each_entry(np, &allnodes, list) {
|
||||
if (np->full_name && (strcmp(np->full_name, path) == 0))
|
||||
break;
|
||||
return np;
|
||||
}
|
||||
return np;
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL(of_find_node_by_path);
|
||||
|
||||
|
|
|
@ -400,7 +400,7 @@ static int atmel_spi_probe(struct device_d *dev)
|
|||
as->cs_pins = pdata->chipselect;
|
||||
as->regs = dev_request_mem_region(dev, 0);
|
||||
|
||||
for (i = 0; i <= master->num_chipselect; i++) {
|
||||
for (i = 0; i < master->num_chipselect; i++) {
|
||||
ret = gpio_request(as->cs_pins[i], dev_name(dev));
|
||||
if (ret)
|
||||
goto out_gpio;
|
||||
|
|
|
@ -8,7 +8,12 @@ config USB_EHCI_OMAP
|
|||
|
||||
config USB_OHCI
|
||||
bool "OHCI driver"
|
||||
depends on !MMU
|
||||
|
||||
if USB_OHCI
|
||||
|
||||
config USB_OHCI_AT91
|
||||
depends on ARCH_AT91
|
||||
bool "AT91 OHCI driver"
|
||||
|
||||
endif
|
||||
|
|
|
@ -16,10 +16,10 @@
|
|||
* @is_open_drain: GPIO pin is configured as open drain
|
||||
*/
|
||||
struct w1_gpio_platform_data {
|
||||
unsigned int pin;
|
||||
int pin;
|
||||
unsigned int is_open_drain:1;
|
||||
void (*enable_external_pullup)(int enable);
|
||||
unsigned int ext_pullup_enable_pin;
|
||||
int ext_pullup_enable_pin;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_W1_GPIO_H */
|
||||
|
|
|
@ -342,6 +342,8 @@ spi_transfer_del(struct spi_transfer *t)
|
|||
|
||||
int spi_sync(struct spi_device *spi, struct spi_message *message);
|
||||
|
||||
struct spi_device *spi_new_device(struct spi_master *master,
|
||||
struct spi_board_info *chip);
|
||||
int spi_register_master(struct spi_master *master);
|
||||
|
||||
#ifdef CONFIG_SPI
|
||||
|
|
|
@ -219,7 +219,7 @@ int fb_open(const char * fbdev, struct screen *sc, bool offscreen)
|
|||
sc->s.y = 0;
|
||||
sc->s.width = sc->info.xres;
|
||||
sc->s.height = sc->info.yres;
|
||||
sc->fbsize = sc->s.x * sc->s.x * (sc->info.bits_per_pixel >> 3);
|
||||
sc->fbsize = sc->s.width * sc->s.height * (sc->info.bits_per_pixel >> 3);
|
||||
|
||||
if (offscreen) {
|
||||
/* Don't fail if malloc fails, just continue rendering directly
|
||||
|
|
10
pbl/string.c
10
pbl/string.c
|
@ -5,6 +5,7 @@
|
|||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
void *memcpy(void *__dest, __const void *__src, size_t __n)
|
||||
{
|
||||
|
@ -103,7 +104,7 @@ void *memchr(const void *s, int c, size_t count)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
char *strchr(const char *s, int c)
|
||||
char *_strchr(const char *s, int c)
|
||||
{
|
||||
while (*s != (char)c)
|
||||
if (*s++ == '\0')
|
||||
|
@ -111,8 +112,6 @@ char *strchr(const char *s, int c)
|
|||
return (char *)s;
|
||||
}
|
||||
|
||||
#undef memset
|
||||
|
||||
void *memset(void *s, int c, size_t count)
|
||||
{
|
||||
char *xs = s;
|
||||
|
@ -120,8 +119,3 @@ void *memset(void *s, int c, size_t count)
|
|||
*xs++ = c;
|
||||
return s;
|
||||
}
|
||||
|
||||
void __memzero(void *s, size_t count)
|
||||
{
|
||||
memset(s, 0, count);
|
||||
}
|
||||
|
|
|
@ -248,3 +248,14 @@ cmd_disasm = $(OBJDUMP) -d $< > $@
|
|||
|
||||
quiet_cmd_ln = LN $@
|
||||
cmd_ln = ln -sf $< $@
|
||||
|
||||
# Check size of a file
|
||||
quiet_cmd_check_file_size = CHKSIZE $@
|
||||
cmd_check_file_size = set -e; \
|
||||
size=`stat -c%s $@`; \
|
||||
max_size=`printf "%d" $2`; \
|
||||
if [ $$size -gt $$max_size ] ; \
|
||||
then \
|
||||
echo "$@ size $$size > of the maximum size $$max_size" >&2; \
|
||||
exit 1 ; \
|
||||
fi;
|
||||
|
|
Loading…
Reference in New Issue