scripts: socfpga sequencer extraction tool
This script extracts the socfpga sequencer from a generated u-boot automagically. The resulting changes of the barebox tree should be enough to compile with the new sequencer. Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Markus Pargmann
Sascha Hauer
parent
ab3313e1a0
commit
4e6ab1a1fa
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@ -45,15 +45,6 @@ handoff files. As these files are split up in the code base and generated
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explicitely for some specific U-boot code base, some manual work might be
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necessary.
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The following files are generic and belong into the
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`arch/arm/mach-socfpga` directory tree:
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* sequencer.c (Not for the faint of heart.)
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* sequencer.h
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* system.h
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It should normally not be necessary to touch these if barebox is up-to-date.
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The boardspecific files for `arch/arm/boards/<yourboard>` are:
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* iocsr_config_cyclone5.c
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@ -78,3 +69,20 @@ To update the handoff files, the following procedure is necessary::
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7. Click ``Ok`` than ``Generate``
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8. Copy the files generated in `software/spl_bsp/generated/` to your
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board folder
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The following files are generic and belong into the
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`arch/arm/mach-socfpga` directory tree:
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* sdram_io.h
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* sequencer.c
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* sequencer.h
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* sequencer_defines.h
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* system.h
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* tclrpt.h
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To add these files, run::
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scripts/socfpga_get_sequencer <UBOOT-SRC> scripts/socfpga_sequencer_defines_defaults
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where `<UBOOT-SRC>` is the directory where the Altera bsp-editor generated the u-boot
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directory. Refer to the Altera documentation for how to use the bsp-editor.
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@ -0,0 +1,78 @@
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#!/bin/bash
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if [ "$#" -lt "2" ]
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then
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echo "USAGE: $0 <UBOOT-SRC> <SEQUENCER_DEFINES>"
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exit 1
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fi
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ubootsrc=$1
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sequencer_defines=$2
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bareboxsrc=.
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cd ${bareboxsrc}
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copy_source() {
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local src
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local tgt
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src=$1
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tgt=$2
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echo "Merging source code $src to $tgt"
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cp $src $tgt
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unifdef -f ${sequencer_defines} $tgt -o $tgt
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echo " Fixing extern/static keywords..."
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# Statify all global variables with missing static keyword
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sed -i 's/^\(extern \|static \|\)\([^*#\/ ][^(]* [^( ]*\((.*).*$\|=.*;.*$\)\)/static \2/g' $tgt
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sed -i 's/^extern /static /g' $tgt
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echo " Translating altera int types..."
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# Replace altera types
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sed -i 's/alt_u32/uint32_t/g' $tgt
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sed -i 's/alt_u16/uint16_t/g' $tgt
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sed -i 's/alt_16/int16_t/g' $tgt
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sed -i 's/alt_32/int32_t/g' $tgt
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sed -i 's/alt_u8/uint8_t/g' $tgt
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sed -i 's/alt_8/int8_t/g' $tgt
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sed -i 's/#include "alt_types.h"//g' $tgt
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echo " Fixing include pathes..."
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# Fix include pathes
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sed -i 's/#include <sdram.h>/#include <mach\/sdram.h>/g' $tgt
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sed -i 's/#include "sequencer_auto.h"//g' $tgt
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echo " Automated readability fixup..."
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indent -npro -kr -i8 -ts8 -sob -l100 -ss -ncs -cp1 -il0 $tgt
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}
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copy_source ${ubootsrc}/board/altera/socfpga/sdram/sequencer.c arch/arm/mach-socfpga/include/mach/sequencer.c
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sed -i 's/static int sdram_calibration(void)/static int socfpga_mem_calibration(void)/g' arch/arm/mach-socfpga/include/mach/sequencer.c
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cat <<'EOF' > arch/arm/mach-socfpga/include/mach/sequencer_defines.h
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#define TINIT_CNTR1_VAL 32
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#define TINIT_CNTR2_VAL 32
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#define TINIT_CNTR0_VAL 99
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#define TRESET_CNTR1_VAL 99
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#define TRESET_CNTR2_VAL 10
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#define TRESET_CNTR0_VAL 99
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EOF
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copy_source ${ubootsrc}/board/altera/socfpga/sdram/sequencer.h arch/arm/mach-socfpga/include/mach/sequencer.h
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copy_source ${ubootsrc}/board/altera/socfpga/sdram/tclrpt.h arch/arm/mach-socfpga/include/mach/tclrpt.h
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copy_source ${ubootsrc}/board/altera/socfpga/sdram/sdram_io.h arch/arm/mach-socfpga/include/mach/sdram_io.h
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cat <<'EOF' >> arch/arm/mach-socfpga/include/mach/sdram_io.h
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#define write_register(BASE, OFFSET, DATA) \
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writel(DATA, ((BASE) + (OFFSET)))
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#define read_register(BASE, OFFSET) \
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readl((BASE) + (OFFSET))
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#define HPS_SDR_BASE 0xffc20000
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EOF
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copy_source ${ubootsrc}/board/altera/socfpga/sdram/system.h arch/arm/mach-socfpga/include/mach/system.h
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#unifdef -f ${sequencer_defines} ${ubootsrc}/board/altera/socfpga/sdram/tclrpt.c -o arch/arm/mach-socfpga/include/mach/tclrpt.c
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echo "DONE"
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@ -0,0 +1,144 @@
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/*
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Copyright (c) 2012, Altera Corporation
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All rights reserved.
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SPDX-License-Identifier: BSD-3-Clause
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of Altera Corporation nor the
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names of its contributors may be used to endorse or promote products
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derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define ENABLE_SWEEP_ALL_GROUPS 0
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#define ENABLE_DQSEN_SWEEP 0
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#define STATIC_QUICK_CALIBRATION 0
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#define DYNAMIC_CALIBRATION_MODE 0
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#define DISABLE_GUARANTEED_READ 0
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#define ARRIAVGZ 0
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#define ARRIAV 0
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#define AVL_CLK_FREQ 67
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#define BFM_MODE 0
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#define BURST2 0
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#define CALIBRATE_BIT_SLIPS 0
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#define CALIB_LFIFO_OFFSET 8
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#define CALIB_VFIFO_OFFSET 6
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#define CYCLONEV 1
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#define DDR2 0
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#define DDR3 1
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#define DDRX 1
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#define DM_PINS_ENABLED 1
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#define ENABLE_ASSERT 0
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#define ENABLE_PRINTF_LOG 0
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#define ENABLE_BRINGUP_DEBUGGING 0
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#define ENABLE_DELAY_CHAIN_WRITE 0
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#define ENABLE_DQS_IN_CENTERING 1
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#define ENABLE_DQS_OUT_CENTERING 0
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#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
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#define ENABLE_INST_ROM_WRITE 1
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#define ENABLE_MARGIN_REPORT_GEN 0
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#define ENABLE_NON_DESTRUCTIVE_CALIB 0
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#define ENABLE_SUPER_QUICK_CALIBRATION 0
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#define ENABLE_TCL_DEBUG 0
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#define FAKE_CAL_FAIL 0
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#define FULL_RATE 1
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#define GUARANTEED_READ_BRINGUP_TEST 0
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#define HALF_RATE 0
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#define HARD_PHY 1
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#define HARD_VFIFO 1
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#define HCX_COMPAT_MODE 0
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#define HHP_HPS_SIMULATION 0
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#define HHP_HPS_VERIFICATION 0
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#define HHP_HPS 1
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#define HPS_HW 1
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#define HR_DDIO_OUT_HAS_THREE_REGS 0
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#define IO_DELAY_PER_DCHAIN_TAP 25
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#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
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#define IO_DELAY_PER_OPA_TAP 312
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#define IO_DLL_CHAIN_LENGTH 8
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#define IO_DM_OUT_RESERVE 0
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#define IO_DQDQS_OUT_PHASE_MAX 0
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#define IO_DQS_EN_DELAY_MAX 31
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#define IO_DQS_EN_DELAY_OFFSET 0
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#define IO_DQS_EN_PHASE_MAX 7
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#define IO_DQS_IN_DELAY_MAX 31
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#define IO_DQS_IN_RESERVE 4
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#define IO_DQS_OUT_RESERVE 4
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#define IO_DQ_OUT_RESERVE 0
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#define IO_IO_IN_DELAY_MAX 31
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#define IO_IO_OUT1_DELAY_MAX 31
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#define IO_IO_OUT2_DELAY_MAX 0
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#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
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#define LPDDR1 0
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#define LPDDR2 0
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#define LRDIMM 0
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#define M10_DQ_WIDTH_8 0
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#define M10_DQ_WIDTH_16 0
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#define M10_DQ_WIDTH_24 0
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#define MARGIN_VARIATION_TEST 0
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#define MAX_LATENCY_COUNT_WIDTH 5
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#define MEM_ADDR_WIDTH 13
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#define MRS_MIRROR_PING_PONG_ATSO 0
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#define MULTIPLE_AFI_WLAT 0
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#define NUM_SHADOW_REGS 1
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#define QDRII 0
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#define QUARTER_RATE 0
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#define RDIMM 0
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#define READ_AFTER_WRITE_CALIBRATION 1
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#define READ_VALID_FIFO_SIZE 16
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#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
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#define RLDRAM3 0
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#define RLDRAMII 0
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#define RLDRAMX 0
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#define RUNTIME_CAL_REPORT 0
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#define RW_MGR_MEM_ADDRESS_MIRRORING 0
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#define RW_MGR_MEM_ADDRESS_WIDTH 15
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#define RW_MGR_MEM_BANK_WIDTH 3
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#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
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#define RW_MGR_MEM_CLK_EN_WIDTH 1
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#define RW_MGR_MEM_CONTROL_WIDTH 1
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#define RW_MGR_MEM_DATA_MASK_WIDTH 4
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#define RW_MGR_MEM_DATA_WIDTH 32
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#define RW_MGR_MEM_DQ_PER_READ_DQS 8
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#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
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#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
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#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
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#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
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#define RW_MGR_MEM_NUMBER_OF_RANKS 1
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#define RW_MGR_MEM_ODT_WIDTH 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
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#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
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#define RW_MGR_MR0_BL 1
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#define RW_MGR_MR0_CAS_LATENCY 3
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#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
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#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
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#define SKEW_CALIBRATION 0
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#define STATIC_FULL_CALIBRATION 1
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#define STATIC_SIM_FILESET 0
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#define STATIC_SKIP_MEM_INIT 0
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#define STRATIXV 0
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#define TRACKING_ERROR_TEST 0
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#define TRACKING_WATCH_TEST 0
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#define TW0_CAPTURE_CLOCKS 0
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#define USE_DQS_TRACKING 1
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#define USE_SHADOW_REGS 0
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#define USE_USER_RDIMM_VALUE 0
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