Merge branch 'for-next/imx'

Conflicts: arch/arm/boards/Makefile
2013-08-05 12:49:42 +02:00 · 2013-08-05 12:49:42 +02:00 · 5034e4eacc
parent b8c60d554f 30f29e3e16
commit 5034e4eacc
45 changed files with 4134 additions and 183 deletions
--- a/Documentation/devicetree/bindings/misc/fsl,imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/misc/fsl,imx-ocotp.txt
@ -0,0 +1,20 @@
+Freescale i.MX OCOTP (On-Chip OTP)
+
+Required properties:
+
+- compatible: fsl,imx6q-ocotp
+- reg: physical register base and size
+
+Optional properties:
+
+- barebox,provide-mac-address: Provide MAC addresses for ethernet devices. This
+  can be multiple entries in the form <&phandle regofs> to specify a MAC
+  address to a ethernet device.
+
+Example:
+
+ocotp1: ocotp@021bc000 {
+	compatible = "fsl,imx6q-ocotp";
+	reg = <0x021bc000 0x4000>;
+	barebox,provide-mac-address = <&fec 0x620>;
+};
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@ -36,6 +36,7 @@ obj-$(CONFIG_MACH_FREESCALE_MX51_PDK)		+= freescale-mx51-pdk/
 obj-$(CONFIG_MACH_FREESCALE_MX53_LOCO)		+= freescale-mx53-loco/
 obj-$(CONFIG_MACH_FREESCALE_MX53_SMD)		+= freescale-mx53-smd/
 obj-$(CONFIG_MACH_GE863)			+= telit-evk-pro3/
+obj-$(CONFIG_MACH_GK802)			+= gk802/
 obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG)		+= globalscale-guruplug/
 obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX)		+= globalscale-mirabox/
 obj-$(CONFIG_MACH_GUF_CUPID)			+= guf-cupid/
@ -64,6 +65,7 @@ obj-$(CONFIG_MACH_PCM038)			+= pcm038/
 obj-$(CONFIG_MACH_PCM043)			+= pcm043/
 obj-$(CONFIG_MACH_PCM049)			+= pcm049/
 obj-$(CONFIG_MACH_PCM051)			+= pcm051/
+obj-$(CONFIG_MACH_PHYTEC_PFLA02)		+= phytec-pfla02/
 obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3)	+= plathome-openblocks-ax3/
 obj-$(CONFIG_MACH_PM9261)			+= pm9261/
 obj-$(CONFIG_MACH_PM9263)			+= pm9263/
@ -81,6 +83,7 @@ obj-$(CONFIG_MACH_TNY_A9263)			+= tny-a926x/
 obj-$(CONFIG_MACH_TNY_A9G20)			+= tny-a926x/
 obj-$(CONFIG_MACH_TOSHIBA_AC100)		+= toshiba-ac100/
 obj-$(CONFIG_MACH_TQMA53)			+= tqma53/
+obj-$(CONFIG_MACH_TQMA6X)			+= tqma6x/
 obj-$(CONFIG_MACH_TX25)				+= karo-tx25/
 obj-$(CONFIG_MACH_TX28)				+= karo-tx28/
 obj-$(CONFIG_MACH_TX51)				+= karo-tx51/
--- a/arch/arm/boards/freescale-mx6-sabrelite/board.c
+++ b/arch/arm/boards/freescale-mx6-sabrelite/board.c
@ -106,26 +106,6 @@ static int sabrelite_ksz9021rn_setup(void)
 */
 fs_initcall(sabrelite_ksz9021rn_setup);

-static inline int imx6_iim_register_fec_ethaddr(void)
-{
-	u32 value;
-	u8 buf[6];
-
-	value = readl(MX6_OCOTP_BASE_ADDR + 0x630);
-	buf[0] = (value >> 8);
-	buf[1] = value;
-
-	value = readl(MX6_OCOTP_BASE_ADDR + 0x620);
-	buf[2] = value >> 24;
-	buf[3] = value >> 16;
-	buf[4] = value >> 8;
-	buf[5] = value;
-
-	eth_register_ethaddr(0, buf);
-
-	return 0;
-}
-
 static void sabrelite_ehci_init(void)
 {
 	imx6_usb_phy2_disable_oc();
@ -157,9 +137,6 @@ static int sabrelite_coredevices_init(void)
 {
 	phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
 					   ksz9021rn_phy_fixup);
-
-	imx6_iim_register_fec_ethaddr();
-
 	return 0;
 }
 coredevice_initcall(sabrelite_coredevices_init);
--- a/arch/arm/boards/freescale-mx6-sabresd/board.c
+++ b/arch/arm/boards/freescale-mx6-sabresd/board.c
@ -80,26 +80,6 @@ static void sabresd_phy_reset(void)
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
 }

-static inline int imx6_iim_register_fec_ethaddr(void)
-{
-	u32 value;
-	u8 buf[6];
-
-	value = readl(MX6_OCOTP_BASE_ADDR + 0x630);
-	buf[0] = (value >> 8);
-	buf[1] = value;
-
-	value = readl(MX6_OCOTP_BASE_ADDR + 0x620);
-	buf[2] = value >> 24;
-	buf[3] = value >> 16;
-	buf[4] = value >> 8;
-	buf[5] = value;
-
-	eth_register_ethaddr(0, buf);
-
-	return 0;
-}
-
 static int sabresd_devices_init(void)
 {
 	armlinux_set_bootparams((void *)0x10000100);
@ -118,8 +98,6 @@ static int sabresd_coredevices_init(void)
 	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
 			ar8031_phy_fixup);

-	imx6_iim_register_fec_ethaddr();
-
 	return 0;
 }
 /*
--- a/arch/arm/boards/gk802/Makefile
+++ b/arch/arm/boards/gk802/Makefile
@ -0,0 +1,3 @@
+obj-y += board.o flash-header.dcd.o
+extra-y += flash-header.dcd.S flash-header.dcd
+lwl-y += lowlevel.o
--- a/arch/arm/boards/gk802/board.c
+++ b/arch/arm/boards/gk802/board.c
@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2013 Philipp Zabel
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+#include <bootsource.h>
+#include <common.h>
+#include <environment.h>
+#include <envfs.h>
+#include <gpio.h>
+#include <init.h>
+#include <mach/generic.h>
+#include <mach/imx6-regs.h>
+#include <mach/imx6.h>
+#include <mfd/imx6q-iomuxc-gpr.h>
+#include <sizes.h>
+
+#define GK802_GPIO_RECOVERY_BTN	IMX_GPIO_NR(3, 16)	/* recovery button */
+#define GK802_GPIO_RTL8192_PDN	IMX_GPIO_NR(2, 0)	/* RTL8192CU powerdown */
+
+static int gk802_env_init(void)
+{
+	char *bootsource_name;
+	char *barebox_name;
+	char *default_environment_name;
+
+	if (!of_machine_is_compatible("zealz,imx6q-gk802"))
+		return 0;
+
+	/* Keep RTL8192CU disabled */
+	gpio_direction_output(GK802_GPIO_RTL8192_PDN, 1);
+
+	gpio_direction_input(GK802_GPIO_RECOVERY_BTN);
+	setenv("recovery", gpio_get_value(GK802_GPIO_RECOVERY_BTN) ? "0" : "1");
+
+	if (bootsource_get() != BOOTSOURCE_MMC)
+		return 0;
+
+	switch (bootsource_get_instance()) {
+	case 2:
+		bootsource_name = "mmc2";
+		barebox_name = "mmc2.barebox";
+		default_environment_name = "mmc2.bareboxenv";
+		default_environment_path = "/dev/mmc2.bareboxenv";
+		break;
+	case 3:
+		bootsource_name = "mmc3";
+		barebox_name = "mmc3.barebox";
+		default_environment_name = "mmc3.bareboxenv";
+		default_environment_path = "/dev/mmc3.bareboxenv";
+		break;
+	default:
+		return 0;
+	}
+
+	device_detect_by_name(bootsource_name);
+	devfs_add_partition(bootsource_name, 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, barebox_name);
+	devfs_add_partition(bootsource_name, SZ_512K, SZ_512K, DEVFS_PARTITION_FIXED, default_environment_name);
+
+	return 0;
+}
+late_initcall(gk802_env_init);
+
+static int gk802_console_init(void)
+{
+	if (!of_machine_is_compatible("zealz,imx6q-gk802"))
+		return 0;
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(gk802_console_init);
--- a/arch/arm/boards/gk802/env/config-board
+++ b/arch/arm/boards/gk802/env/config-board
@ -0,0 +1,7 @@
+#!/bin/sh
+
+# board defaults, do not change in running system. Change /env/config
+# instead
+
+global.hostname=gk802
+global.linux.bootargs.base="console=ttymxc3,115200"
--- a/arch/arm/boards/gk802/flash-header.imxcfg
+++ b/arch/arm/boards/gk802/flash-header.imxcfg
@ -0,0 +1,96 @@
+loadaddr 0x10000000
+soc imx6
+dcdofs 0x400
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7975
+wm 32 0x021b0010 0xff538e64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005b0e21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831a0000
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00000007
+wm 32 0x021b4818 0x00000007
+wm 32 0x021b083c 0x427b030a
+wm 32 0x021b0840 0x02740269
+wm 32 0x021b483c 0x43100313
+wm 32 0x021b4840 0x027d024d
+wm 32 0x021b0848 0x46384240
+wm 32 0x021b4848 0x4442414a
+wm 32 0x021b0850 0x45444645
+wm 32 0x021b4850 0x4a354946
+wm 32 0x021b080c 0x001f001f
+wm 32 0x021b0810 0x001f001f
+wm 32 0x021b480c 0x00440044
+wm 32 0x021b4810 0x00440044
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020e0010 0xf00000ff
+wm 32 0x020e0018 0x007f007f
+wm 32 0x020e001c 0x007f007f
--- a/arch/arm/boards/gk802/lowlevel.c
+++ b/arch/arm/boards/gk802/lowlevel.c
@ -0,0 +1,18 @@
+#include <common.h>
+#include <sizes.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+
+extern char __dtb_imx6q_gk802_start[];
+
+ENTRY_FUNCTION(start_imx6_gk802)(void)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	fdt = (uint32_t)__dtb_imx6q_gk802_start - get_runtime_offset();
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
--- a/arch/arm/boards/phytec-pfla02/Makefile
+++ b/arch/arm/boards/phytec-pfla02/Makefile
@ -0,0 +1,5 @@
+obj-y += board.o
+obj-y += flash-header-phytec-pfla02-1gib.dcd.o flash-header-phytec-pfla02-2gib.dcd.o
+extra-y += flash-header-phytec-pfla02-1gib.dcd.S flash-header-phytec-pfla02-2gib.dcd.S
+extra-y += flash-header-phytec-pfla02-1gib.dcd flash-header-phytec-pfla02-2gib.dcd
+lwl-y += lowlevel.o
--- a/arch/arm/boards/phytec-pfla02/board.c
+++ b/arch/arm/boards/phytec-pfla02/board.c
@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <common.h>
+#include <gpio.h>
+#include <init.h>
+#include <of.h>
+
+#include <mach/imx6.h>
+
+#define ETH_PHY_RST	IMX_GPIO_NR(3, 23)
+
+static int eth_phy_reset(void)
+{
+	gpio_request(ETH_PHY_RST, "phy reset");
+	gpio_direction_output(ETH_PHY_RST, 0);
+	mdelay(1);
+	gpio_set_value(ETH_PHY_RST, 1);
+
+	return 0;
+}
+
+static int phytec_pfla02_init(void)
+{
+	if (!of_machine_is_compatible("phytec,imx6q-pfla02"))
+		return 0;
+
+	eth_phy_reset();
+
+	return 0;
+}
+device_initcall(phytec_pfla02_init);
+
+static int phytec_pfla02_core_init(void)
+{
+	if (!of_machine_is_compatible("phytec,imx6q-pfla02"))
+		return 0;
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(phytec_pfla02_core_init);
--- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg
+++ b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg
@ -0,0 +1,6 @@
+
+#define SETUP_1GIB_2GIB			\
+	wm 32 0x021b0040 0x00000017;	\
+	wm 32 0x021b0000 0xc21a0000
+
+#include "flash-header-phytec-pfla02.h"
--- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg
+++ b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg
@ -0,0 +1,6 @@
+
+#define SETUP_1GIB_2GIB			\
+	wm 32 0x021b0040 0x00000027;	\
+	wm 32 0x021b0000 0xC31A0000
+
+#include "flash-header-phytec-pfla02.h"
--- a/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02.h
+++ b/arch/arm/boards/phytec-pfla02/flash-header-phytec-pfla02.h
@ -0,0 +1,99 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7975
+wm 32 0x021b0010 0xff538e64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005b0e21
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+
+SETUP_1GIB_2GIB
+
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x09408030
+wm 32 0x021b001c 0x09408038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b083c 0x433c033f
+wm 32 0x021b0840 0x033e033d
+wm 32 0x021b483c 0x43490351
+wm 32 0x021b4840 0x0344032f
+wm 32 0x021b0848 0x4a434146
+wm 32 0x021b4848 0x4745434b
+wm 32 0x021b0850 0x3d3d433a
+wm 32 0x021b4850 0x48334b3e
+wm 32 0x021b080c 0x000f0011
+wm 32 0x021b0810 0x00200022
+wm 32 0x021b480c 0x0033002e
+wm 32 0x021b4810 0x003e003b
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020e0010 0xf00000ff
+wm 32 0x020e0018 0x007f007f
+wm 32 0x020e001c 0x007f007f
+wm 32 0x020c8000 0x80002021
--- a/arch/arm/boards/phytec-pfla02/lowlevel.c
+++ b/arch/arm/boards/phytec-pfla02/lowlevel.c
@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+extern char __dtb_imx6q_phytec_pbab01_start[];
+
+ENTRY_FUNCTION(start_phytec_pbab01_1gib)(void)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_phytec_pbab01_2gib)(void)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_2G, fdt);
+}
--- a/arch/arm/boards/tqma6x/Makefile
+++ b/arch/arm/boards/tqma6x/Makefile
@ -0,0 +1,5 @@
+obj-y += board.o
+obj-y += flash-header-tqma6q.dcd.o flash-header-tqma6dl.dcd.o
+extra-y += flash-header-tqma6q.dcd.S flash-header-tqma6dl.dcd.S
+extra-y += flash-header-tqma6q.dcd flash-header-tqma6dl.dcd
+lwl-y += lowlevel.o
--- a/arch/arm/boards/tqma6x/board.c
+++ b/arch/arm/boards/tqma6x/board.c
@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2013 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation.
+ *
+ */
+
+#include <generated/mach-types.h>
+#include <environment.h>
+#include <bootsource.h>
+#include <partition.h>
+#include <common.h>
+#include <envfs.h>
+#include <sizes.h>
+#include <init.h>
+#include <gpio.h>
+#include <fec.h>
+
+#include <linux/micrel_phy.h>
+#include <mfd/stmpe-i2c.h>
+
+#include <asm/armlinux.h>
+#include <asm/io.h>
+
+#include <mach/devices-imx6.h>
+#include <mach/imx6-regs.h>
+#include <mach/iomux-mx6.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/generic.h>
+#include <mach/imx6.h>
+#include <mach/bbu.h>
+
+#define RQ7_GPIO_ENET_PHYADD2	IMX_GPIO_NR(6, 30)
+#define RQ7_GPIO_ENET_MODE0	IMX_GPIO_NR(6, 25)
+#define RQ7_GPIO_ENET_MODE1	IMX_GPIO_NR(6, 27)
+#define RQ7_GPIO_ENET_MODE2	IMX_GPIO_NR(6, 28)
+#define RQ7_GPIO_ENET_MODE3	IMX_GPIO_NR(6, 29)
+#define RQ7_GPIO_ENET_EN_CLK125	IMX_GPIO_NR(6, 24)
+
+static iomux_v3_cfg_t tqma6x_pads_gpio[] = {
+	MX6Q_PAD_RGMII_RXC__GPIO_6_30,
+	MX6Q_PAD_RGMII_RD0__GPIO_6_25,
+	MX6Q_PAD_RGMII_RD1__GPIO_6_27,
+	MX6Q_PAD_RGMII_RD2__GPIO_6_28,
+	MX6Q_PAD_RGMII_RD3__GPIO_6_29,
+	MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24,
+};
+
+static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
+{
+	phy_write(dev, 0x0d, device);
+	phy_write(dev, 0x0e, reg);
+	phy_write(dev, 0x0d, (1 << 14) | device);
+	phy_write(dev, 0x0e, val);
+}
+
+static int ksz9031rn_phy_fixup(struct phy_device *dev)
+{
+	/*
+	 * min rx data delay, max rx/tx clock delay,
+	 * min rx/tx control delay
+	 */
+	mmd_write_reg(dev, 2, 4, 0);
+	mmd_write_reg(dev, 2, 5, 0);
+	mmd_write_reg(dev, 2, 8, 0x003ff);
+
+	return 0;
+}
+
+static int tqma6x_enet_init(void)
+{
+	if (!of_machine_is_compatible("tq,mba6x"))
+		return 0;
+
+	mxc_iomux_v3_setup_multiple_pads(tqma6x_pads_gpio, ARRAY_SIZE(tqma6x_pads_gpio));
+	gpio_direction_output(RQ7_GPIO_ENET_PHYADD2, 0);
+	gpio_direction_output(RQ7_GPIO_ENET_MODE0, 1);
+	gpio_direction_output(RQ7_GPIO_ENET_MODE1, 1);
+	gpio_direction_output(RQ7_GPIO_ENET_MODE2, 1);
+	gpio_direction_output(RQ7_GPIO_ENET_MODE3, 1);
+	gpio_direction_output(RQ7_GPIO_ENET_EN_CLK125, 1);
+
+	gpio_direction_output(25, 0);
+	mdelay(50);
+
+	gpio_direction_output(25, 1);
+	mdelay(50);
+
+	phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
+					   ksz9031rn_phy_fixup);
+
+	return 0;
+}
+fs_initcall(tqma6x_enet_init);
+
+extern char flash_header_tqma6dl_start[];
+extern char flash_header_tqma6dl_end[];
+
+extern char flash_header_tqma6q_start[];
+extern char flash_header_tqma6q_end[];
+
+static int tqma6x_env_init(void)
+{
+	void *flash_header_start;
+	void *flash_header_end;
+
+	if (of_machine_is_compatible("tq,tqma6s")) {
+		flash_header_start = (void *)flash_header_tqma6dl_start;
+		flash_header_end = (void *)flash_header_tqma6dl_end;
+	} else if (of_machine_is_compatible("tq,tqma6q")) {
+		flash_header_start = (void *)flash_header_tqma6q_start;
+		flash_header_end = (void *)flash_header_tqma6q_end;
+	} else {
+		return 0;
+	}
+
+	devfs_add_partition("m25p0", 0, SZ_512K, DEVFS_PARTITION_FIXED, "m25p0.barebox");
+
+	imx6_bbu_internal_spi_i2c_register_handler("spiflash", "/dev/m25p0.barebox",
+		BBU_HANDLER_FLAG_DEFAULT, (void *)flash_header_start,
+		flash_header_end - flash_header_start, 0);
+	imx6_bbu_internal_mmc_register_handler("emmc", "/dev/mmc2.boot0",
+		0, (void *)flash_header_start, flash_header_end - flash_header_start, 0);
+
+	device_detect_by_name("mmc2");
+
+	default_environment_path = "/dev/mmc2.boot1";
+
+	return 0;
+}
+late_initcall(tqma6x_env_init);
+
+static int tqma6x_core_init(void)
+{
+	if (!of_machine_is_compatible("tq,mba6x"))
+		return 0;
+
+	imx6_init_lowlevel();
+
+	return 0;
+}
+postcore_initcall(tqma6x_core_init);
--- a/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg
+++ b/arch/arm/boards/tqma6x/flash-header-tqma6dl.imxcfg
@ -0,0 +1,99 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+wm 32 0x020e04bc 0x00000030
+wm 32 0x020e04c0 0x00000030
+wm 32 0x020e04c4 0x00000030
+wm 32 0x020e04c8 0x00000030
+wm 32 0x020e04cc 0x00000030
+wm 32 0x020e04d0 0x00000030
+wm 32 0x020e04d4 0x00000030
+wm 32 0x020e04d8 0x00000030
+wm 32 0x020e0764 0x00000030
+wm 32 0x020e0770 0x00000030
+wm 32 0x020e0778 0x00000030
+wm 32 0x020e077c 0x00000030
+wm 32 0x020e0780 0x00000030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e076c 0x00000030
+wm 32 0x020e0470 0x00020030
+wm 32 0x020e0474 0x00020030
+wm 32 0x020e0478 0x00020030
+wm 32 0x020e047c 0x00020030
+wm 32 0x020e0480 0x00020030
+wm 32 0x020e0484 0x00020030
+wm 32 0x020e0488 0x00020030
+wm 32 0x020e048c 0x00020030
+wm 32 0x020e0464 0x00020030
+wm 32 0x020e0490 0x00020030
+wm 32 0x020e04ac 0x00020030
+wm 32 0x020e04b0 0x00020030
+wm 32 0x020e0494 0x000e0030
+wm 32 0x020e04a4 0x00003000
+wm 32 0x020e04a8 0x00003000
+wm 32 0x020e04b4 0x00003030
+wm 32 0x020e04b8 0x00003030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0760 0x00020000
+wm 32 0x020e0754 0x00000000
+wm 32 0x020e04a0 0x00000000
+wm 32 0x020e0774 0x000C0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b0004 0x0002002D
+wm 32 0x021b000c 0x40435323
+wm 32 0x021b0010 0xB66E8D63
+wm 32 0x021b0014 0x01FF00DB
+wm 32 0x021b002c 0x000026D2
+wm 32 0x021b0030 0x00431023
+wm 32 0x021b0008 0x00333030
+wm 32 0x021b0004 0x0002556D
+wm 32 0x021b0040 0x00000017
+wm 32 0x021b0000 0x83190000
+wm 32 0x021b001c 0x04008032
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x00048031
+wm 32 0x021b001c 0x13208030
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b0800 0xA1390003
+wm 32 0x021b4800 0xA1390003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b083c 0x42350231
+wm 32 0x021b483c 0x42350231
+wm 32 0x021b0840 0x021A0218
+wm 32 0x021b4840 0x021A0218
+wm 32 0x021b0848 0x4B4B4E49
+wm 32 0x021b4848 0x4B4B4E49
+wm 32 0x021b0850 0x3F3F3035
+wm 32 0x021b4850 0x3F3F3035
+wm 32 0x021b080c 0x0040003C
+wm 32 0x021b0810 0x0032003E
+wm 32 0x021b480c 0x0040003C
+wm 32 0x021b4810 0x0032003E
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020C4068 0x00C03F3F
+wm 32 0x020C406c 0x0030FC03
+wm 32 0x020C4070 0x0FFFC000
+wm 32 0x020C4074 0x3FF00000
+wm 32 0x020C4078 0x00FFF300
+wm 32 0x020C407c 0x0F0000C3
+wm 32 0x020C4080 0x000003FF
+wm 32 0x020e0010 0xF00000CF
+wm 32 0x020e0018 0x007F007F
+wm 32 0x020e001c 0x007F007F
--- a/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg
+++ b/arch/arm/boards/tqma6x/flash-header-tqma6q.imxcfg
@ -0,0 +1,104 @@
+soc imx6
+loadaddr 0x20000000
+dcdofs 0x400
+
+wm 32 0x020e05a8 0x00000030
+wm 32 0x020e05b0 0x00000030
+wm 32 0x020e0524 0x00000030
+wm 32 0x020e051c 0x00000030
+wm 32 0x020e0518 0x00000030
+wm 32 0x020e050c 0x00000030
+wm 32 0x020e05b8 0x00000030
+wm 32 0x020e05c0 0x00000030
+wm 32 0x020e05ac 0x00020030
+wm 32 0x020e05b4 0x00020030
+wm 32 0x020e0528 0x00020030
+wm 32 0x020e0520 0x00020030
+wm 32 0x020e0514 0x00020030
+wm 32 0x020e0510 0x00020030
+wm 32 0x020e05bc 0x00020030
+wm 32 0x020e05c4 0x00020030
+wm 32 0x020e056c 0x00020030
+wm 32 0x020e0578 0x00020030
+wm 32 0x020e0588 0x00020030
+wm 32 0x020e0594 0x00020030
+wm 32 0x020e057c 0x00020030
+wm 32 0x020e0590 0x00003000
+wm 32 0x020e0598 0x00003000
+wm 32 0x020e058c 0x00000000
+wm 32 0x020e059c 0x00003030
+wm 32 0x020e05a0 0x00003030
+wm 32 0x020e0784 0x00000030
+wm 32 0x020e0788 0x00000030
+wm 32 0x020e0794 0x00000030
+wm 32 0x020e079c 0x00000030
+wm 32 0x020e07a0 0x00000030
+wm 32 0x020e07a4 0x00000030
+wm 32 0x020e07a8 0x00000030
+wm 32 0x020e0748 0x00000030
+wm 32 0x020e074c 0x00000030
+wm 32 0x020e0750 0x00020000
+wm 32 0x020e0758 0x00000000
+wm 32 0x020e0774 0x00020000
+wm 32 0x020e078c 0x00000030
+wm 32 0x020e0798 0x000c0000
+wm 32 0x021b081c 0x33333333
+wm 32 0x021b0820 0x33333333
+wm 32 0x021b0824 0x33333333
+wm 32 0x021b0828 0x33333333
+wm 32 0x021b481c 0x33333333
+wm 32 0x021b4820 0x33333333
+wm 32 0x021b4824 0x33333333
+wm 32 0x021b4828 0x33333333
+wm 32 0x021b0018 0x00081740
+wm 32 0x021b001c 0x00008000
+wm 32 0x021b000c 0x555a7974
+wm 32 0x021b0010 0xdb538f64
+wm 32 0x021b0014 0x01ff00db
+wm 32 0x021b002c 0x000026d2
+wm 32 0x021b0030 0x005a1023
+wm 32 0x021b0008 0x09444040
+wm 32 0x021b0004 0x00025576
+wm 32 0x021b0040 0x00000027
+wm 32 0x021b0000 0x831a0000
+wm 32 0x021b001c 0x04088032
+wm 32 0x021b001c 0x0408803a
+wm 32 0x021b001c 0x00008033
+wm 32 0x021b001c 0x0000803b
+wm 32 0x021b001c 0x00428031
+wm 32 0x021b001c 0x00428039
+wm 32 0x021b001c 0x19308030
+wm 32 0x021b001c 0x19308038
+wm 32 0x021b001c 0x04008040
+wm 32 0x021b001c 0x04008048
+wm 32 0x021b0800 0xa1380003
+wm 32 0x021b4800 0xa1380003
+wm 32 0x021b0020 0x00005800
+wm 32 0x021b0818 0x00022227
+wm 32 0x021b4818 0x00022227
+wm 32 0x021b083c 0x434b0350
+wm 32 0x021b0840 0x034c0359
+wm 32 0x021b483c 0x434b0350
+wm 32 0x021b4840 0x03650348
+wm 32 0x021b0848 0x4436383b
+wm 32 0x021b4848 0x39393341
+wm 32 0x021b0850 0x35373933
+wm 32 0x021b4850 0x48254a36
+wm 32 0x021b080c 0x001f001f
+wm 32 0x021b0810 0x001f001f
+wm 32 0x021b480c 0x00440044
+wm 32 0x021b4810 0x00440044
+wm 32 0x021b08b8 0x00000800
+wm 32 0x021b48b8 0x00000800
+wm 32 0x021b001c 0x00000000
+wm 32 0x021b0404 0x00011006
+wm 32 0x020c4068 0x00c03f3f
+wm 32 0x020c406c 0x0030fc03
+wm 32 0x020c4070 0x0fffc000
+wm 32 0x020c4074 0x3ff00000
+wm 32 0x020c4078 0x00fff300
+wm 32 0x020c407c 0x0f0000c3
+wm 32 0x020c4080 0x000003ff
+wm 32 0x020e0010 0xf00000cf
+wm 32 0x020e0018 0x007f007f
+wm 32 0x020e001c 0x007f007f
--- a/arch/arm/boards/tqma6x/lowlevel.c
+++ b/arch/arm/boards/tqma6x/lowlevel.c
@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <debug_ll.h>
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/sections.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <mach/imx6-mmdc.h>
+#include <mach/imx6.h>
+
+static inline void setup_uart(void)
+{
+	/* Enable UART for lowlevel debugging purposes */
+	writel(0x00000000, 0x021e8080);
+	writel(0x00004027, 0x021e8084);
+	writel(0x00000704, 0x021e8088);
+	writel(0x00000a81, 0x021e8090);
+	writel(0x0000002b, 0x021e809c);
+	writel(0x00013880, 0x021e80b0);
+	writel(0x0000047f, 0x021e80a4);
+	writel(0x0000c34f, 0x021e80a8);
+	writel(0x00000001, 0x021e8080);
+}
+
+extern char __dtb_imx6q_mba6x_start[];
+extern char __dtb_imx6dl_mba6x_start[];
+
+ENTRY_FUNCTION(start_imx6q_mba6x)(void)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		writel(0x2, 0x020e0338);
+		setup_uart();
+		PUTC_LL('a');
+	}
+
+	arm_early_mmu_cache_invalidate();
+
+	fdt = (uint32_t)__dtb_imx6q_mba6x_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_1G, fdt);
+}
+
+ENTRY_FUNCTION(start_imx6dl_mba6x)(void)
+{
+	uint32_t fdt;
+
+	__barebox_arm_head();
+
+	arm_cpu_lowlevel_init();
+
+	arm_setup_stack(0x00920000 - 8);
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		writel(0x2, 0x020e035c);
+		setup_uart();
+		PUTC_LL('a');
+	}
+
+	arm_early_mmu_cache_invalidate();
+
+	fdt = (uint32_t)__dtb_imx6dl_mba6x_start - get_runtime_offset();
+
+	barebox_arm_entry(0x10000000, SZ_512M, fdt);
+}
--- a/arch/arm/configs/imx_v7_defconfig
+++ b/arch/arm/configs/imx_v7_defconfig
@ -3,7 +3,10 @@ CONFIG_IMX_MULTI_BOARDS=y
 CONFIG_MACH_EFIKA_MX_SMARTBOOK=y
 CONFIG_MACH_FREESCALE_MX51_PDK=y
 CONFIG_MACH_FREESCALE_MX53_LOCO=y
+CONFIG_MACH_PHYTEC_PFLA02=y
 CONFIG_MACH_REALQ7=y
+CONFIG_MACH_GK802=y
+CONFIG_MACH_TQMA6X=y
 CONFIG_IMX_IIM=y
 CONFIG_IMX_IIM_FUSE_BLOW=y
 CONFIG_THUMB2_BAREBOX=y
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@ -1,9 +1,13 @@
 dtb-$(CONFIG_ARCH_IMX51) += imx51-babbage.dtb \
 	imx51-genesi-efika-sb.dtb
 dtb-$(CONFIG_ARCH_IMX53) += imx53-qsb.dtb
-dtb-$(CONFIG_ARCH_IMX6) += imx6q-dmo-realq7.dtb \
+dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
+	imx6q-dmo-realq7.dtb \
 	imx6q-sabrelite.dtb \
-	imx6q-sabresd.dtb
+	imx6q-sabresd.dtb \
+	imx6dl-mba6x.dtb \
+	imx6q-mba6x.dtb \
+	imx6q-phytec-pbab01.dtb

 BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
 obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
@ -11,7 +15,10 @@ obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
 pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o
 pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o
+pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6q-phytec-pbab01.dtb.o
 pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
+pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
+pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o

 .SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
 .SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))
--- a/arch/arm/dts/imx6dl-mba6x.dts
+++ b/arch/arm/dts/imx6dl-mba6x.dts
@ -0,0 +1,67 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+
+#include "imx6dl-tqma6s.dtsi"
+#include "imx6qdl-mba6x.dtsi"
+
+/ {
+	model = "TQ TQMA6S on MBa6x";
+	compatible = "tq,mba6x", "tq,tqma6s", "fsl,imx6dl";
+
+	chosen {
+		linux,stdout-path = &uart2;
+	};
+
+	memory {
+		reg = <0x10000000 0x20000000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	gpiobuttons {
+		pinctrl_gpiobuttons_1: gpiogrp-1 {
+			fsl,pins = <
+				MX6DL_PAD_GPIO_17__GPIO7_IO12 0x80000000
+				MX6DL_PAD_GPIO_18__GPIO7_IO13 0x80000000
+				MX6DL_PAD_GPIO_8__GPIO1_IO08 0x80000000
+			>;
+		};
+	};
+
+	hog {
+		pinctrl_hog: hoggrp-1 {
+			fsl,pins = <
+				MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
+				MX6DL_PAD_GPIO_4__GPIO1_IO04  0x80000000 /* usdhc2 CD */
+				MX6DL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
+				MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
+				MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
+				MX6DL_PAD_EIM_D22__GPIO3_IO22 0x80000000
+				MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x80000000
+				MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
+				MX6DL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
+				MX6DL_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
+				MX6DL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
+				MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
+			>;
+		};
+	};
+};
+
+&disp0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_disp0_ipu1>;
+	crtcs = <&ipu1 0>;
+};
--- a/arch/arm/dts/imx6dl-pinfunc.h
+++ b/arch/arm/dts/imx6dl-pinfunc.h
--- a/arch/arm/dts/imx6dl-tqma6s.dtsi
+++ b/arch/arm/dts/imx6dl-tqma6s.dtsi
@ -0,0 +1,99 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-tqma6x.dtsi"
+
+&iomuxc {
+	can1 {
+		pinctrl_can1_1: can1grp-1 {
+			fsl,pins = <
+				MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+				MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+			>;
+		};
+	};
+
+	can2 {
+		pinctrl_can2_1: can2grp-1 {
+			fsl,pins = <
+				MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+				MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+			>;
+		};
+	};
+
+	disp0 {
+		pinctrl_disp0_ipu1: disp0grp-1 {
+			fsl,pins = <
+				MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
+				MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
+				MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
+				MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
+				MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
+				MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
+				MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
+				MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
+				MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
+				MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
+				MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
+				MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
+				MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
+				MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
+				MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
+				MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
+				MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
+				MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
+				MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
+				MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
+				MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
+				MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
+				MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
+				MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
+				MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
+				MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
+				MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
+				MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6DL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+				MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+				MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x {
+			fsl,pins = <
+				MX6DL_PAD_SD2_CMD__SD2_CMD    0x000070f0
+				MX6DL_PAD_SD2_CLK__SD2_CLK    0x000070f0
+				MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
+				MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
+				MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
+				MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
+			>;
+		};
+	};
+};
--- a/arch/arm/dts/imx6dl.dtsi
+++ b/arch/arm/dts/imx6dl.dtsi
@ -0,0 +1,438 @@
+
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "imx6qdl.dtsi"
+#include "imx6dl-pinfunc.h"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+	};
+
+	soc {
+		aips1: aips-bus@02000000 {
+			iomuxc: iomuxc@020e0000 {
+				compatible = "fsl,imx6dl-iomuxc";
+				reg = <0x020e0000 0x4000>;
+
+				audmux {
+					pinctrl_audmux_1: audmux-1 {
+						fsl,pins = <
+							MX6DL_PAD_SD2_DAT0__AUD4_RXD  0x80000000
+							MX6DL_PAD_SD2_DAT3__AUD4_TXC  0x80000000
+							MX6DL_PAD_SD2_DAT2__AUD4_TXD  0x80000000
+							MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
+						>;
+					};
+
+					pinctrl_audmux_2: audmux-2 {
+						fsl,pins = <
+							MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+							MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+							MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+							MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+						>;
+					};
+				};
+
+				ecspi1 {
+					pinctrl_ecspi1_1: ecspi1grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+							MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+							MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+						>;
+					};
+
+					pinctrl_ecspi1_2: ecspi1grp-2 {
+						fsl,pins = <
+							MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+							MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+							MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+						>;
+					};
+				};
+
+				ecspi3 {
+					pinctrl_ecspi3_1: ecspi3grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
+							MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
+							MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+						>;
+					};
+				};
+
+				enet {
+					pinctrl_enet_1: enetgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+							MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+							MX6DL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
+						>;
+					};
+
+					pinctrl_enet_2: enetgrp-2 {
+						fsl,pins = <
+							MX6DL_PAD_KEY_COL1__ENET_MDIO        0x1b0b0
+							MX6DL_PAD_KEY_COL2__ENET_MDC         0x1b0b0
+							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+						>;
+					};
+
+					pinctrl_enet_3: enetgrp-3 {
+						fsl,pins = <
+							MX6DL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+							MX6DL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+							MX6DL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+							MX6DL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+							MX6DL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+							MX6DL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+							MX6DL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+							MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+							MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+							MX6DL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+							MX6DL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+							MX6DL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+							MX6DL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+							MX6DL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+							MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+							MX6DL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+						>;
+					};
+				};
+
+				gpmi-nand {
+					pinctrl_gpmi_nand_1: gpmi-nand-1 {
+						fsl,pins = <
+							MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+							MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+							MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+							MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+							MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+							MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+							MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+							MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+							MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+							MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+							MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+							MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+							MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+							MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+							MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+							MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+							MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+						>;
+					};
+				};
+
+				i2c1 {
+					pinctrl_i2c1_1: i2c1grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+							MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+						>;
+					};
+
+					pinctrl_i2c1_2: i2c1grp-2 {
+						fsl,pins = <
+							MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+							MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+						>;
+					};
+				};
+
+				i2c2 {
+					pinctrl_i2c2_1: i2c2grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+							MX6DL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+						>;
+					};
+				};
+
+				i2c3 {
+					pinctrl_i2c3_1: i2c3grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
+							MX6DL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
+						>;
+					};
+				};
+
+				uart1 {
+					pinctrl_uart1_1: uart1grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
+							MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
+						>;
+					};
+				};
+
+				uart2 {
+					pinctrl_uart2_1: uart2grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+							MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+						>;
+					};
+				};
+
+				uart4 {
+					pinctrl_uart4_1: uart4grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+							MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+						>;
+					};
+				};
+
+				usbotg {
+					pinctrl_usbotg_1: usbotggrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
+						>;
+					};
+
+					pinctrl_usbotg_2: usbotggrp-2 {
+						fsl,pins = <
+							MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+						>;
+					};
+				};
+
+				usdhc2 {
+					pinctrl_usdhc2_1: usdhc2grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
+							MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
+							MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+							MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+							MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+							MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+							MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
+							MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
+							MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
+							MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
+						>;
+					};
+
+					pinctrl_usdhc2_2: usdhc2grp-2 {
+						fsl,pins = <
+							MX6DL_PAD_SD2_CMD__SD2_CMD    0x17059
+							MX6DL_PAD_SD2_CLK__SD2_CLK    0x10059
+							MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+							MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+							MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+							MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+						>;
+					};
+				};
+
+				usdhc3 {
+					pinctrl_usdhc3_1: usdhc3grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+							MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+							MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+							MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+							MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+						>;
+					};
+
+					pinctrl_usdhc3_2: usdhc3grp-2 {
+						fsl,pins = <
+							MX6DL_PAD_SD3_CMD__SD3_CMD    0x17059
+							MX6DL_PAD_SD3_CLK__SD3_CLK    0x10059
+							MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+							MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+							MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+							MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+						>;
+					};
+				};
+
+				usdhc4 {
+					pinctrl_usdhc4_1: usdhc4grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
+							MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
+							MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+							MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+							MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+							MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+							MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x17059
+							MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x17059
+							MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x17059
+							MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x17059
+						>;
+					};
+
+					pinctrl_usdhc4_2: usdhc4grp-2 {
+						fsl,pins = <
+							MX6DL_PAD_SD4_CMD__SD4_CMD    0x17059
+							MX6DL_PAD_SD4_CLK__SD4_CLK    0x10059
+							MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x17059
+							MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x17059
+							MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x17059
+							MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x17059
+						>;
+					};
+				};
+
+				weim {
+					pinctrl_weim_cs0_1: weim_cs0grp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+						>;
+					};
+
+					pinctrl_weim_nor_1: weim_norgrp-1 {
+						fsl,pins = <
+							MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+							MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+							MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+							/* data */
+							MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+							MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+							MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+							MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+							MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+							MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+							MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+							MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+							MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+							MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+							MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+							MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+							MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+							MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+							MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+							MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+							/* address */
+							MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+							MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+							MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+							MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+							MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+							MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+							MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+							MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+							MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+							MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+							MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+							MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+							MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+							MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+							MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+							MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+							MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+							MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+							MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+							MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+							MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+							MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+							MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+							MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+						>;
+					};
+				};
+			};
+
+			pxp: pxp@020f0000 {
+				reg = <0x020f0000 0x4000>;
+				interrupts = <0 98 0x04>;
+			};
+
+			epdc: epdc@020f4000 {
+				reg = <0x020f4000 0x4000>;
+				interrupts = <0 97 0x04>;
+			};
+
+			lcdif: lcdif@020f8000 {
+				reg = <0x020f8000 0x4000>;
+				interrupts = <0 39 0x04>;
+			};
+		};
+
+		aips2: aips-bus@02100000 {
+			i2c4: i2c@021f8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx1-i2c";
+				reg = <0x021f8000 0x4000>;
+				interrupts = <0 35 0x04>;
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&ldb {
+	clocks = <&clks 33>, <&clks 34>,
+		 <&clks 39>, <&clks 40>,
+		 <&clks 135>, <&clks 136>;
+	clock-names = "di0_pll", "di1_pll",
+		      "di0_sel", "di1_sel",
+		      "di0", "di1";
+
+	lvds-channel@0 {
+		crtcs = <&ipu1 0>, <&ipu1 1>;
+	};
+
+	lvds-channel@1 {
+		crtcs = <&ipu1 0>, <&ipu1 1>;
+	};
+};
--- a/arch/arm/dts/imx6q-gk802.dts
+++ b/arch/arm/dts/imx6q-gk802.dts
@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2013 Philipp Zabel
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "imx6q.dtsi"
+
+/ {
+	model = "Zealz GK802";
+	compatible = "zealz,imx6q-gk802", "fsl,imx6q";
+
+	chosen {
+		linux,stdout-path = "/soc/aips-bus@02100000/serial@021f0000";
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+
+		reg_3p3v: 3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "3P3V";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		recovery-button {
+			label = "recovery";
+			gpios = <&gpio3 16 1>;
+			linux,code = <0x198>; /* KEY_RESTART */
+			gpio-key,wakeup;
+		};
+	};
+};
+
+/* Internal I2C */
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_gk802>;
+	clock-frequency = <100000>;
+	status = "okay";
+
+	/* SDMC DM2016 1024 bit EEPROM + 128 bit OTP */
+	eeprom: dm2016@51 {
+		compatible = "sdmc,dm2016";
+		reg = <0x51>;
+	};
+};
+
+/* External I2C via HDMI */
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3_gk802>;
+	clock-frequency = <100000>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	hog {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				/* Recovery button, active-low */
+				MX6Q_PAD_EIM_D16__GPIO3_IO16  0x100b1
+				/* RTL8192CU enable GPIO, active-low */
+				MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+			>;
+		};
+	};
+
+	i2c2 {
+		pinctrl_i2c2_gk802: i2c2grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+				MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_gk802: i2c3grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_GPIO_5__I2C3_SCL  0x4001b8b1
+				MX6Q_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
+			>;
+		};
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_1>;
+	status = "okay";
+};
+
+/* External USB-A port (USBOTG) */
+&usbotg {
+	phy-mode = "utmi";
+	dr_mode = "host";
+	barebox,phy_type = "utmi";
+	disable-over-current;
+	status = "okay";
+};
+
+/* Internal USB port (USBH1), connected to RTL8192CU */
+&usbh1 {
+	phy-mode = "utmi";
+	dr_mode = "host";
+	barebox,phy_type = "utmi";
+	disable-over-current;
+	status = "okay";
+};
+
+/* External microSD */
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3_2>;
+	bus-width = <4>;
+	cd-gpios = <&gpio6 11 0>;
+	vmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
+
+/* Internal microSD */
+&usdhc4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc4_2>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_3p3v>;
+	status = "okay";
+};
--- a/arch/arm/dts/imx6q-mba6x.dts
+++ b/arch/arm/dts/imx6q-mba6x.dts
@ -0,0 +1,71 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+
+#include "imx6q-tqma6q.dtsi"
+#include "imx6qdl-mba6x.dtsi"
+
+/ {
+	model = "TQ TQMA6Q on MBa6x";
+	compatible = "tq,mba6x", "tq,tqma6q", "fsl,imx6q";
+
+	chosen {
+		linux,stdout-path = &uart2;
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	gpiobuttons {
+		pinctrl_gpiobuttons_1: gpiogrp-1 {
+			fsl,pins = <
+				MX6Q_PAD_GPIO_17__GPIO7_IO12 0x80000000
+				MX6Q_PAD_GPIO_18__GPIO7_IO13 0x80000000
+				MX6Q_PAD_GPIO_8__GPIO1_IO08 0x80000000
+			>;
+		};
+	};
+
+	hog {
+		pinctrl_hog: hoggrp-1 {
+			fsl,pins = <
+				MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
+				MX6Q_PAD_GPIO_4__GPIO1_IO04  0x80000000 /* usdhc2 CD */
+				MX6Q_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
+				MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
+				MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
+				MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
+				MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* beeper (1 = on) */
+				MX6Q_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* LCD.PWR_EN */
+				MX6Q_PAD_GPIO_7__GPIO1_IO07 0x80000000 /* LCD.RESET */
+				MX6Q_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* LCD.BLT_EN */
+				MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x80000000 /* LCD.CONTRAST */
+			>;
+		};
+	};
+};
+
+&disp0 {
+	pinctrl-names = "ipu1-di0", "ipu2-di0";
+	pinctrl-0 = <&pinctrl_disp0_ipu1>;
+	pinctrl-1 = <&pinctrl_disp0_ipu2>;
+	crtcs = <&ipu1 0 &ipu2 0>;
+};
+
+&sata {
+	status = "okay";
+};
--- a/arch/arm/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/dts/imx6q-phytec-pbab01.dts
@ -0,0 +1,47 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q-phytec-pfla02.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
+	compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
+
+	chosen {
+		linux,stdout-path = &uart4;
+
+		environment@0 {
+			compatible = "barebox,environment";
+			device-path = &flash, "partname:barebox-environment";
+		};
+	};
+};
+
+&fec {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&uart4 {
+	status = "okay";
+};
+
+&usdhc2 {
+	status = "okay";
+};
+
+&usdhc3 {
+	status = "okay";
+};
--- a/arch/arm/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/dts/imx6q-phytec-pfla02.dtsi
@ -0,0 +1,127 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+	model = "Phytec phyFLEX-i.MX6 Ouad";
+	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+};
+
+&ecspi3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi3_1>;
+	status = "okay";
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio4 24 0>;
+
+	flash: m25p80@0 {
+		compatible = "m25p80";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	hog {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+				MX6Q_PAD_DISP0_DAT3__GPIO4_IO24	0x80000000 /* SPI NOR chipselect */
+			>;
+		};
+	};
+
+	pfla02 {
+		pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+			fsl,pins = <
+				MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+				MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+			>;
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_3>;
+	phy-mode = "rgmii";
+	phy-reset-gpios = <&gpio3 23 0>;
+	status = "disabled";
+};
+
+&flash {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0x80000>;
+	};
+
+	partition@1 {
+		label = "barebox-environment";
+		reg = <0x80000 0x10000>;
+	};
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	nand-on-flash-bbt;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	partition@0 {
+		label = "barebox";
+		reg = <0x0 0x200000>;
+	};
+
+	partition@1 {
+		label = "ubi";
+		reg = <0x200000 0x3fe00000>;
+	};
+};
+
+&ocotp1 {
+	barebox,provide-mac-address = <&fec 0x620>;
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4_1>;
+	status = "disabled";
+};
+
+&usdhc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_2>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+		     &pinctrl_usdhc3_pfla02>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
--- a/arch/arm/dts/imx6q-sabrelite.dts
+++ b/arch/arm/dts/imx6q-sabrelite.dts
@ -108,6 +108,10 @@
 	};
 };

+&ocotp1 {
+	barebox,provide-mac-address = <&fec 0x620>;
+};
+
 &usbotg {
 	vbus-supply = <&reg_usb_otg_vbus>;
 	pinctrl-names = "default";
--- a/arch/arm/dts/imx6q-tqma6q.dtsi
+++ b/arch/arm/dts/imx6q-tqma6q.dtsi
@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+#include "imx6qdl-tqma6x.dtsi"
+
+&iomuxc {
+	can1 {
+		pinctrl_can1_1: can1grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+				MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+			>;
+		};
+	};
+
+	can2 {
+		pinctrl_can2_1: can2grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+				MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+			>;
+		};
+	};
+
+	disp0 {
+		pinctrl_disp0_ipu1: disp0grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x80000000
+				MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x80000000
+				MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x80000000
+				MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x80000000
+				MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x80000000
+				MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x80000000
+				MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x80000000
+				MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x80000000
+				MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x80000000
+				MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x80000000
+				MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x80000000
+				MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x80000000
+				MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x80000000
+				MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x80000000
+				MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x80000000
+				MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x80000000
+				MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x80000000
+				MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x80000000
+				MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x80000000
+				MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x80000000
+				MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x80000000
+				MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x80000000
+				MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x80000000
+				MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x80000000
+				MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x80000000
+				MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x80000000
+				MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x80000000
+				MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x80000000
+			>;
+		};
+
+		pinctrl_disp0_ipu2: disp0grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x80000000
+				MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x80000000
+				MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x80000000
+				MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x80000000
+				MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x80000000
+				MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x80000000
+				MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x80000000
+				MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x80000000
+				MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x80000000
+				MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x80000000
+				MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x80000000
+				MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x80000000
+				MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x80000000
+				MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x80000000
+				MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x80000000
+				MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x80000000
+				MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x80000000
+				MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x80000000
+				MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x80000000
+				MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x80000000
+				MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x80000000
+				MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x80000000
+				MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x80000000
+				MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x80000000
+				MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x80000000
+				MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x80000000
+				MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x80000000
+				MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x80000000
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+				MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+				MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	usdhc2 {
+		pinctrl_usdhc2_tqma6x: usdhc2grp-tqma6x {
+			fsl,pins = <
+				MX6Q_PAD_SD2_CMD__SD2_CMD    0x000070f0
+				MX6Q_PAD_SD2_CLK__SD2_CLK    0x000070f0
+				MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x000070f0
+				MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x000070f0
+				MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x000070f0
+				MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x000070f0
+			>;
+		};
+	};
+};
--- a/arch/arm/dts/imx6q-tqma6x.dts
+++ b/arch/arm/dts/imx6q-tqma6x.dts
@ -0,0 +1,320 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+
+#include "imx6q.dtsi"
+
+/ {
+	model = "TQ TQMa6x";
+	compatible = "tq,tqma6x", "fsl,imx6q";
+
+	chosen {
+		linux,stdout-path = "/soc/aips-bus@02100000/serial@021e8000";
+	};
+
+	memory {
+		reg = <0x10000000 0x40000000>;
+	};
+
+	gpio_buttons: gpio_buttons@0 {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpiobuttons_1>;
+
+		button@1 {
+			label = "button0";
+			linux,code = <0x100>;
+			gpios = <&gpio7 13 0>;
+		};
+
+		button@2 {
+			label = "button1";
+			linux,code = <0x101>;
+			gpios = <&gpio7 12 0>;
+		};
+
+		button@3 {
+			label = "button2";
+			linux,code = <0x102>;
+			gpios = <&gpio1 8 0>;
+		};
+	};
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_1>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can2_1>;
+	status = "okay";
+};
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	status = "okay";
+
+	flash: m25p80@0 {
+		compatible = "m25p80";
+		spi-max-frequency = <40000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_1>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&hdmi {
+	status = "okay";
+	ddc = <&i2c2>;
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3_2>;
+
+	pmic: pf0100@08 {
+		compatible = "pf0100-regulator";
+		reg = <0x08>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <10 8>;
+
+		regulators {
+			reg_vddcore: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_vddsoc: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_gen_3v3: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5a: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5b: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_vtt: sw4 {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_5v_600mA: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-always-on;
+			};
+
+			reg_snvs_3v: vsnvs {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			reg_vrefddr: vrefddr {
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-always-on;
+			};
+
+			reg_vgen1_1v5: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				/* not used */
+			};
+
+			reg_vgen2_1v2_eth: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			reg_vgen3_2v8: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen4_1v8: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen5_1v8_eth: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen6_3v3: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	sensor1: lm75@48 {
+		compatible = "lm75";
+		reg = <0x48>;
+	};
+
+	sensor2: lm75@49 {
+		compatible = "lm75";
+		reg = <0x49>;
+	};
+
+	eeprom: m24c64@50 { /* FIXME: Baseboard */
+		compatible = "st,24c64", "at24";
+		reg = <0x50>;
+	};
+
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	can1 {
+		pinctrl_can1_1: can1grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
+				MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
+			>;
+		};
+	};
+
+	can2 {
+		pinctrl_can2_1: can2grp-1 {
+			fsl,pins = <
+				MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+				MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+			>;
+		};
+	};
+
+	hog {
+		pinctrl_hog: hoggrp-1 {
+			fsl,pins = <
+				MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 /* FEC phy reset */
+				MX6Q_PAD_GPIO_4__GPIO1_IO04  0x80000000 /* usdhc2 CD */
+				MX6Q_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* usdhc2 WP */
+				MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* eCSPI1 SS1 */
+				MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x80000000 /* PMIC irq */
+				MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
+			>;
+		};
+	};
+
+	i2c3 {
+		pinctrl_i2c3_2: i2c3grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+				MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+			>;
+		};
+	};
+
+	uart2 {
+		pinctrl_uart2_2: uart2grp-2 {
+			fsl,pins = <
+				MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
+				MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
+			>;
+		};
+	};
+
+	gpiobuttons {
+		pinctrl_gpiobuttons_1: gpiogrp-1 {
+			fsl,pins = <
+				MX6Q_PAD_GPIO_17__GPIO7_IO12 0x80000000
+				MX6Q_PAD_GPIO_18__GPIO7_IO13 0x80000000
+				MX6Q_PAD_GPIO_8__GPIO1_IO08 0x80000000
+			>;
+		};
+	};
+};
+
+&sata {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_2>;
+};
+
+&usbh1 {
+	status = "okay";
+	barebox,phy_type = "utmi";
+	disable-over-current;
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg_1>;
+	barebox,phy_type = "utmi";
+	barebox,dr_mode = "peripheral";
+	dr_mode = "host";
+	disable-over-current;
+	otg_id_pin_select_change;
+	status = "okay";
+};
+
+&usdhc2 { /* Baseboard Slot */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_1>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	max-frequency = <1000000>;
+	status = "okay";
+};
+
+&usdhc3 { /* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	non-removable;
+	bus-width = <8>;
+	status = "disabled";
+};
--- a/arch/arm/dts/imx6q.dtsi
+++ b/arch/arm/dts/imx6q.dtsi
@ -104,6 +104,14 @@
 							MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
 						>;
 					};
+
+					pinctrl_ecspi1_2: ecspi1grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+							MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+							MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
+						>;
+					};
 				};

 				ecspi3 {
@ -157,6 +165,27 @@
 							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 						>;
 					};
+
+					pinctrl_enet_3: enetgrp-3 {
+						fsl,pins = <
+							MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+							MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+							MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+							MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+							MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+							MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+							MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+							MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+							MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+							MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+							MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+							MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+							MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+							MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+							MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+							MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+						>;
+					};
 				};

 				gpmi-nand {
@ -192,6 +221,13 @@
 							MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
 						>;
 					};
+
+					pinctrl_i2c1_2: i2c1grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+							MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+						>;
+					};
 				};

 				i2c2 {
@ -268,6 +304,17 @@
 							MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
 						>;
 					};
+
+					pinctrl_usdhc2_2: usdhc2grp-2 {
+						fsl,pins = <
+							MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+							MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+							MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+							MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+							MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+							MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+						>;
+					};
 				};

 				usdhc3 {
--- a/arch/arm/dts/imx6qdl-mba6x.dtsi
+++ b/arch/arm/dts/imx6qdl-mba6x.dtsi
@ -0,0 +1,190 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+	gpio_buttons: gpio_buttons@0 {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpiobuttons_1>;
+
+		button@1 {
+			label = "s6";
+			linux,code = <64>; /* KEY_F6 */
+			gpios = <&gpio7 13 0>;
+		};
+
+		button@2 {
+			label = "s7";
+			linux,code = <65>; /* KEY_F7 */
+			gpios = <&gpio7 12 0>;
+		};
+
+		button@3 {
+			label = "s8";
+			linux,code = <66>; /* KEY_F8 */
+			gpios = <&gpio1 8 0>;
+		};
+	};
+
+	beeper: beeper@0 {
+		compatible = "pwm-beeper";
+		pwms = <&pwm1 2 5000000>;
+	};
+
+	disp0: display@0 {
+		compatible = "fsl,imx-parallel-display";
+		interface-pix-fmt = "rgb24";
+		gpios = <&gpio7 11 0>; /* LCD.PWR_EN */
+		status = "disabled";
+
+		display-timings {
+			tx14d11vm1cpd {
+				clock-frequency = <4854369 5847953 7042253>;
+				hactive = <320>;
+				vactive = <240>;
+				hfront-porch = <22 30 35>;
+				hback-porch = <23 30 35>;
+				hsync-len = <4 5 7>;
+				vback-porch = <4 5 9>;
+				vfront-porch = <5 6 10>;
+				vsync-len = <2>;
+				pixelclk-active = <1>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+			};
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		lcd-backlight-enable {
+			label = "backlight";
+			gpios = <&gpio4 5 0>; /* LCD.BLT_EN */
+			linux,default-trigger = "default-on";
+		};
+
+		lcd-contrast {
+			label = "contrast";
+			gpios = <&gpio4 20 0>; /* LCD.CONTRAST */
+			linux,default-trigger = "default-on";
+		};
+	};
+
+	sound {
+		/* Currently the kernel does not have a fabric driver for this */
+		compatible = "fsl,imx6-tqma6x-tlv320aic23",
+			     "fsl,imx-audio-tlv320aic23";
+		model = "imx6-tqma6x-tlv320aic23";
+		ssi-controller = <&ssi1>;
+		audio-codec = <&codec>;
+		mux-int-port = <1>;
+		mux-ext-port = <3>;
+	};
+};
+
+&audmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_audmux_2>;
+	status = "okay";
+};
+
+&can1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can1_1>;
+	status = "okay";
+};
+
+&can2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_can2_1>;
+	status = "okay";
+};
+
+&i2c1 {
+	codec: tlv320@18 {
+		compatible = "ti,tlv320aic23";
+		reg = <0x18>;
+	};
+};
+
+&i2c3 {
+	sensor1: lm75@49 {
+		compatible = "lm75";
+		reg = <0x49>;
+	};
+};
+
+&ldb {
+	status = "disabled";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "disabled";
+
+		display-timings {
+			chimei-g070y2-l01 {
+				clock-frequency = <27000000 29500000 33000000>;
+				hactive = <800>;
+				vactive = <480>;
+				hfront-porch = <0>;
+				hback-porch = <0>;
+				hsync-len = <130 192 290>;
+				vback-porch = <0>;
+				vfront-porch = <2>;
+				vsync-len = <10 20 70>;
+				de-active = <1>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+			};
+		};
+	};
+};
+
+&ssi1 {
+	fsl,mode = "i2s-slave";
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2_2>;
+};
+
+&usbh1 {
+	status = "okay";
+	barebox,phy_type = "utmi";
+	disable-over-current;
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg_1>;
+	barebox,phy_type = "utmi";
+	barebox,dr_mode = "peripheral";
+	dr_mode = "host";
+	disable-over-current;
+	otg_id_pin_select_change;
+	status = "okay";
+};
+
+&usdhc2 { /* Baseboard Slot */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc2_tqma6x>;
+	cd-gpios = <&gpio1 4 0>;
+	wp-gpios = <&gpio1 2 0>;
+	status = "okay";
+};
--- a/arch/arm/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/dts/imx6qdl-sabresd.dtsi
@ -52,6 +52,10 @@
 	status = "okay";
 };

+&ocotp1 {
+	barebox,provide-mac-address = <&fec 0x620>;
+};
+
 &uart1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_uart1_1>;
--- a/arch/arm/dts/imx6qdl-tqma6x.dtsi
+++ b/arch/arm/dts/imx6qdl-tqma6x.dtsi
@ -0,0 +1,162 @@
+/*
+ * Copyright 2013 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+&ecspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1_1>;
+	fsl,spi-num-chipselects = <1>;
+	cs-gpios = <&gpio3 19 0>;
+	status = "okay";
+
+	flash: m25p80@0 {
+		compatible = "m25p80";
+		spi-max-frequency = <40000000>;
+		reg = <0>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet_1>;
+	phy-mode = "rgmii";
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_2>;
+};
+
+&i2c3 {
+	status = "okay";
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3_2>;
+
+	pmic: pf0100@08 {
+		compatible = "pf0100-regulator";
+		reg = <0x08>;
+		interrupt-parent = <&gpio6>;
+		interrupts = <10 8>;
+
+		regulators {
+			reg_vddcore: sw1ab {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_vddsoc: sw1c {
+				regulator-min-microvolt = <300000>;
+				regulator-max-microvolt = <1875000>;
+				regulator-always-on;
+			};
+
+			reg_gen_3v3: sw2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5a: sw3a {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_1v5b: sw3b {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_ddr_vtt: sw4 {
+				regulator-min-microvolt = <400000>;
+				regulator-max-microvolt = <1975000>;
+				regulator-always-on;
+			};
+
+			reg_5v_600mA: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+				regulator-always-on;
+			};
+
+			reg_snvs_3v: vsnvs {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-always-on;
+			};
+
+			reg_vrefddr: vrefddr {
+				regulator-min-microvolt = <750000>;
+				regulator-max-microvolt = <750000>;
+				regulator-always-on;
+			};
+
+			reg_vgen1_1v5: vgen1 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				/* not used */
+			};
+
+			reg_vgen2_1v2_eth: vgen2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			reg_vgen3_2v8: vgen3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen4_1v8: vgen4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen5_1v8_eth: vgen5 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			reg_vgen6_3v3: vgen6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	sensor2: lm75@48 {
+		compatible = "lm75";
+		reg = <0x48>;
+	};
+
+	eeprom: m24c64@50 {
+		compatible = "st,24c64", "at24";
+		reg = <0x50>;
+	};
+};
+
+&usdhc3 { /* eMMC */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3_1>;
+	non-removable;
+	bus-width = <8>;
+	status = "okay";
+};
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@ -751,12 +751,12 @@
 				interrupts = <0 14 0x04>;
 			};

-			ocotp@021bc000 {
+			ocotp1: ocotp@021bc000 {
 				compatible = "fsl,imx6q-ocotp";
 				reg = <0x021bc000 0x4000>;
 			};

-			ocotp@021c0000 {
+			ocotp2: ocotp@021c0000 {
 				reg = <0x021c0000 0x4000>;
 				interrupts = <0 21 0x04>;
 			};
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@ -32,6 +32,9 @@ config ARCH_TEXT_BASE
 	default 0x97f00000 if MACH_EFIKA_MX_SMARTBOOK
 	default 0x17800000 if MACH_SABRESD
 	default 0x4fc00000 if MACH_REALQ7
+	default 0x4fc00000 if MACH_GK802
+	default 0x2fc00000 if MACH_TQMA6X
+	default 0x4fc00000 if MACH_PHYTEC_PFLA02

 config BOARDINFO
 	default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
@ -61,6 +64,7 @@ config BOARDINFO
 	default "Garz+Fricke Vincell" if MACH_GUF_VINCELL
 	default "SabreSD" if MACH_SABRESD
 	default "DataModul i.MX6Q Real Qseven" if MACH_REALQ7
+	default "Zealz GK802" if MACH_GK802
 	default "unused" if IMX_MULTI_BOARDS

 choice
@ -141,22 +145,6 @@ config ARCH_IMX_EXTERNAL_BOOT_NAND
 	prompt "Support Starting barebox from NAND"
 	depends on ARCH_IMX_EXTERNAL_BOOT

-choice
-	depends on ARCH_IMX_EXTERNAL_BOOT_NAND
-	default NAND_IMX_BOOT_512_2K
-	prompt "select nand pagesize you want to support booting from"
-
-config NAND_IMX_BOOT_512
-	bool "512 byte page size"
-
-config NAND_IMX_BOOT_2K
-	bool "2048 byte page size"
-
-config NAND_IMX_BOOT_512_2K
-	bool "512 byte and 2048 byte pagesize"
-
-endchoice
-
 config BAREBOX_UPDATE_IMX_EXTERNAL_NAND
 	bool
 	depends on ARCH_IMX_EXTERNAL_BOOT_NAND
@ -239,12 +227,24 @@ config MACH_FREESCALE_MX53_LOCO
 	bool "Freescale i.MX53 LOCO"
 	select ARCH_IMX53

+config MACH_PHYTEC_PFLA02
+	bool "Phytec phyFLEX-i.MX6 Ouad"
+	select ARCH_IMX6
+
 config MACH_REALQ7
 	bool "DataModul i.MX6Q Real Qseven Board"
 	select ARCH_IMX6
 	select HAVE_DEFAULT_ENVIRONMENT_NEW
 	select HAVE_PBL_MULTI_IMAGES

+config MACH_GK802
+	bool "Zealz GK802 Mini PC"
+	select ARCH_IMX6
+
+config MACH_TQMA6X
+	bool "TQ tqma6x on mba6x"
+	select ARCH_IMX6
+
 endif

 # ----------------------------------------------------------
@ -618,6 +618,15 @@ config IMX_IIM_FUSE_BLOW
 	  enable it:
 	    imx_iim0.permanent_write_enable=1

+config IMX_OCOTP
+	tristate "i.MX6 On Chip OTP controller"
+	depends on ARCH_IMX6
+	depends on OFDEVICE
+	help
+	  This adds support for the i.MX6 On-Chip OTP controller. Currently the
+	  only supported functionality is reading the MAC address and assigning
+	  it to an ethernet device.
+
 endmenu

 endif
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@ -12,6 +12,7 @@ pbl-$(CONFIG_ARCH_IMX53) += imx53.o imx5.o esdctl-v4.o
 obj-$(CONFIG_ARCH_IMX6) += imx6.o usb-imx6.o clk-imx6.o
 lwl-$(CONFIG_ARCH_IMX6) += imx6-mmdc.o
 obj-$(CONFIG_IMX_IIM)	+= iim.o
+obj-$(CONFIG_IMX_OCOTP)	+= ocotp.o
 obj-$(CONFIG_NAND_IMX) += nand.o
 lwl-$(CONFIG_ARCH_IMX_EXTERNAL_BOOT_NAND) += external-nand-boot.o
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-pfd.o
--- a/arch/arm/mach-imx/external-nand-boot.c
+++ b/arch/arm/mach-imx/external-nand-boot.c
@ -121,40 +121,6 @@ static void __bare_init __memcpy32(void *trg, const void *src, int size)
 		*t++ = *s++;
 }

-static int __maybe_unused is_pagesize_2k(void)
-{
-#ifdef CONFIG_ARCH_IMX21
-	if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
-		return 1;
-	else
-		return 0;
-#endif
-#if defined(CONFIG_ARCH_IMX25)
-	if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
-		return 1;
-	else
-		return 0;
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
-		return 1;
-	else
-		return 0;
-#endif
-#ifdef CONFIG_ARCH_IMX31
-	if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
-		return 1;
-	else
-		return 0;
-#endif
-#if defined(CONFIG_ARCH_IMX35)
-	if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
-		return 1;
-	else
-		return 0;
-#endif
-}
-
 static noinline void __bare_init imx_nandboot_get_page(void *regs,
 		u32 offs, int pagesize_2k)
 {
@ -163,19 +129,12 @@ static noinline void __bare_init imx_nandboot_get_page(void *regs,
 	imx_nandboot_send_page(regs, NFC_OUTPUT, pagesize_2k);
 }

-void __bare_init imx_nand_load_image(void *dest, int size)
+void __bare_init imx_nand_load_image(void *dest, int size, void __iomem *base,
+		int pagesize_2k)
 {
 	u32 tmp, page, block, blocksize, pagesize, badblocks;
-	int pagesize_2k = 1, bbt = 0;
-	void *regs, *base, *spare0;
-
-#if defined(CONFIG_NAND_IMX_BOOT_512)
-	pagesize_2k = 0;
-#elif defined(CONFIG_NAND_IMX_BOOT_2K)
-	pagesize_2k = 1;
-#else
-	pagesize_2k = is_pagesize_2k();
-#endif
+	int bbt = 0;
+	void *regs, *spare0;

 	if (pagesize_2k) {
 		pagesize = 2048;
@ -185,21 +144,6 @@ void __bare_init imx_nand_load_image(void *dest, int size)
 		blocksize = 16 * 1024;
 	}

-#ifdef CONFIG_ARCH_IMX21
-	base = (void __iomem *)MX21_NFC_BASE_ADDR;
-#endif
-#ifdef CONFIG_ARCH_IMX25
-	base = (void __iomem *)MX25_NFC_BASE_ADDR;
-#endif
-#ifdef CONFIG_ARCH_IMX27
-	base = (void __iomem *)MX27_NFC_BASE_ADDR;
-#endif
-#ifdef CONFIG_ARCH_IMX31
-	base = (void __iomem *)MX31_NFC_BASE_ADDR;
-#endif
-#ifdef CONFIG_ARCH_IMX35
-	base = (void __iomem *)MX35_NFC_BASE_ADDR;
-#endif
 	if (nfc_is_v21()) {
 		regs = base + 0x1e00;
 		spare0 = base + 0x1000;
@ -332,115 +276,120 @@ int __bare_init imx_barebox_boot_nand_external(unsigned long nfc_base)
 	return 1;
 }

+#define BARE_INIT_FUNCTION(name)  \
+	void __noreturn __section(.text_bare_init_##name) \
+		name
+
 /*
 * SoC specific entries for booting in external NAND mode. To be called from
 * the board specific entry code. This is safe to call even if not booting from
 * NAND. In this case the booting is continued without loading an image from
 * NAND. This function needs a stack to be set up.
 */
-#ifdef CONFIG_ARCH_IMX21
-void __bare_init __noreturn imx21_barebox_boot_nand_external(void)
+#ifdef BROKEN
+BARE_INIT_FUNCTION(imx21_barebox_boot_nand_external)(void)
 {
 	unsigned long nfc_base = MX21_NFC_BASE_ADDR;
+	int pagesize_2k;

 	if (imx_barebox_boot_nand_external(nfc_base)) {
 		jump_sdram(nfc_base - ld_var(_text));
+
+		if (readl(MX21_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
+			pagesize_2k = 1;
+		else
+			pagesize_2k = 0;
+
 		imx_nand_load_image((void *)ld_var(_text),
-				ld_var(barebox_image_size));
+				ld_var(barebox_image_size),
+				(void *)nfc_base, pagesize_2k);
 	}

+	/* This function doesn't exist yet */
 	imx21_barebox_entry(0);
 }
 #endif

-#ifdef CONFIG_ARCH_IMX25
-void __bare_init __noreturn imx25_barebox_boot_nand_external(void)
+BARE_INIT_FUNCTION(imx25_barebox_boot_nand_external)(void)
 {
 	unsigned long nfc_base = MX25_NFC_BASE_ADDR;
+	int pagesize_2k;

 	if (imx_barebox_boot_nand_external(nfc_base)) {
 		jump_sdram(nfc_base - ld_var(_text));
+
+		if (readl(MX25_CCM_BASE_ADDR + MX25_CCM_RCSR) & (1 << 8))
+			pagesize_2k = 1;
+		else
+			pagesize_2k = 0;
+
 		imx_nand_load_image((void *)ld_var(_text),
-				ld_var(_barebox_image_size));
+				ld_var(_barebox_image_size),
+				(void *)nfc_base, pagesize_2k);
 	}

 	imx25_barebox_entry(0);
 }
-#endif

-#ifdef CONFIG_ARCH_IMX27
-void __bare_init __noreturn imx27_barebox_boot_nand_external(void)
+BARE_INIT_FUNCTION(imx27_barebox_boot_nand_external)(void)
 {
 	unsigned long nfc_base = MX27_NFC_BASE_ADDR;
+	int pagesize_2k;

 	if (imx_barebox_boot_nand_external(nfc_base)) {
 		jump_sdram(nfc_base - ld_var(_text));
+
+		if (readl(MX27_SYSCTRL_BASE_ADDR + 0x14) & (1 << 5))
+			pagesize_2k = 1;
+		else
+			pagesize_2k = 0;
+
 		imx_nand_load_image((void *)ld_var(_text),
-				ld_var(_barebox_image_size));
+				ld_var(_barebox_image_size),
+				(void *)nfc_base, pagesize_2k);
 	}

 	imx27_barebox_entry(0);
 }
-#endif

-#ifdef CONFIG_ARCH_IMX31
-void __bare_init __noreturn imx31_barebox_boot_nand_external(void)
+BARE_INIT_FUNCTION(imx31_barebox_boot_nand_external)(void)
 {
 	unsigned long nfc_base = MX31_NFC_BASE_ADDR;
+	int pagesize_2k;

 	if (imx_barebox_boot_nand_external(nfc_base)) {
 		jump_sdram(nfc_base - ld_var(_text));
+
+		if (readl(MX31_CCM_BASE_ADDR + MX31_CCM_RCSR) & MX31_RCSR_NFMS)
+			pagesize_2k = 1;
+		else
+			pagesize_2k = 0;
+
 		imx_nand_load_image((void *)ld_var(_text),
-				ld_var(_barebox_image_size));
+				ld_var(_barebox_image_size),
+				(void *)nfc_base, pagesize_2k);
 	}

 	imx31_barebox_entry(0);
 }
-#endif

-#ifdef CONFIG_ARCH_IMX35
-void __bare_init __noreturn imx35_barebox_boot_nand_external(void)
+BARE_INIT_FUNCTION(imx35_barebox_boot_nand_external)(void)
 {
 	unsigned long nfc_base = MX35_NFC_BASE_ADDR;
+	int pagesize_2k;

 	if (imx_barebox_boot_nand_external(nfc_base)) {
 		jump_sdram(nfc_base - ld_var(_text));
+
+		if (readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR) & (1 << 8))
+			pagesize_2k = 1;
+		else
+			pagesize_2k = 0;
+
 		imx_nand_load_image((void *)ld_var(_text),
-				ld_var(_barebox_image_size));
+				ld_var(_barebox_image_size),
+				(void *)nfc_base, pagesize_2k);
 	}

 	imx35_barebox_entry(0);
 }
-#endif
-
-#define CONFIG_NAND_IMX_BOOT_DEBUG
-#ifdef CONFIG_NAND_IMX_BOOT_DEBUG
-#include <command.h>
-
-static int do_nand_boot_test(int argc, char *argv[])
-{
-	void *dest;
-	int size;
-
-	if (argc < 3)
-		return COMMAND_ERROR_USAGE;
-
-	dest = (void *)strtoul_suffix(argv[1], NULL, 0);
-	size = strtoul_suffix(argv[2], NULL, 0);
-
-	imx_nand_load_image(dest, size);
-
-	return 0;
-}
-
-static const __maybe_unused char cmd_nand_boot_test_help[] =
-"Usage: nand_boot_test <dest> <size>\n"
-"This command loads the booloader from the NAND memory like the reset\n"
-"routine does. Its intended for development tests only";
-
-BAREBOX_CMD_START(nand_boot_test)
-	.cmd		= do_nand_boot_test,
-	.usage		= "load bootloader from NAND",
-	BAREBOX_CMD_HELP(cmd_nand_boot_test_help)
-BAREBOX_CMD_END
-#endif
--- a/arch/arm/mach-imx/ocotp.c
+++ b/arch/arm/mach-imx/ocotp.c
@ -0,0 +1,105 @@
+/*
+ * ocotp.c - i.MX6 ocotp fusebox driver
+ *
+ * Provide an interface for programming and sensing the information that are
+ * stored in on-chip fuse elements. This functionality is part of the IC
+ * Identification Module (IIM), which is present on some i.MX CPUs.
+ *
+ * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
+ * 	Orex Computed Radiography
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <init.h>
+#include <net.h>
+#include <io.h>
+
+/*
+ * a single MAC address reference has the form
+ * <&phandle regoffset>
+ */
+#define MAC_ADDRESS_PROPLEN	(2 * sizeof(__be32))
+
+static void imx_ocotp_init_dt(struct device_d *dev, void __iomem *base)
+{
+	char mac[6];
+	const __be32 *prop;
+	struct device_node *node = dev->device_node;
+	int len;
+
+	if (!node)
+		return;
+
+	prop = of_get_property(node, "barebox,provide-mac-address", &len);
+	if (!prop)
+		return;
+
+	while (len >= MAC_ADDRESS_PROPLEN) {
+		struct device_node *rnode;
+		uint32_t phandle, offset, value;
+
+		phandle = be32_to_cpup(prop++);
+
+		rnode = of_find_node_by_phandle(phandle);
+		offset = be32_to_cpup(prop++);
+
+		value = readl(base + offset + 0x10);
+		mac[0] = (value >> 8);
+		mac[1] = value;
+		value = readl(base + offset);
+		mac[2] = value >> 24;
+		mac[3] = value >> 16;
+		mac[4] = value >> 8;
+		mac[5] = value;
+
+		of_eth_register_ethaddr(rnode, mac);
+
+		len -= MAC_ADDRESS_PROPLEN;
+	}
+}
+
+static int imx_ocotp_probe(struct device_d *dev)
+{
+	void __iomem *base;
+
+	base = dev_request_mem_region(dev, 0);
+	if (!base)
+		return -EBUSY;
+
+	imx_ocotp_init_dt(dev, base);
+
+	return 0;
+}
+
+static __maybe_unused struct of_device_id imx_ocotp_dt_ids[] = {
+	{
+		.compatible = "fsl,imx6q-ocotp",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d imx_ocotp_driver = {
+	.name	= "imx_ocotp",
+	.probe	= imx_ocotp_probe,
+	.of_compatible = DRV_OF_COMPAT(imx_ocotp_dt_ids),
+};
+
+static int imx_ocotp_init(void)
+{
+	platform_driver_register(&imx_ocotp_driver);
+
+	return 0;
+}
+coredevice_initcall(imx_ocotp_init);
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@ -35,3 +35,33 @@ CFG_start_imx6_realq7.pblx.imximg = $(board)/dmo-mx6-realq7/flash-header.imxcfg
 imximage-$(CONFIG_MACH_REALQ7) += start_imx6_realq7.pblx.imximg
 FILE_barebox-datamodul-edm-qmx6.img = start_imx6_realq7.pblx.imximg
 image-$(CONFIG_MACH_REALQ7) += barebox-datamodul-edm-qmx6.img
+
+pblx-$(CONFIG_MACH_GK802) += start_imx6_gk802
+CFG_start_imx6_gk802.pblx.imximg = $(board)/gk802/flash-header.imxcfg
+imximage-$(CONFIG_MACH_GK802) += start_imx6_gk802.pblx.imximg
+FILE_barebox-gk802.img = start_imx6_gk802.pblx.imximg
+image-$(CONFIG_MACH_GK802) += barebox-gk802.img
+
+pblx-$(CONFIG_MACH_TQMA6X) += start_imx6dl_mba6x
+CFG_start_imx6dl_mba6x.pblx.imximg = $(board)/tqma6x/flash-header-tqma6dl.imxcfg
+imximage-$(CONFIG_MACH_TQMA6X) += start_imx6dl_mba6x.pblx.imximg
+FILE_barebox-tq-tqma6s-mba6x.img = start_imx6dl_mba6x.pblx.imximg
+image-$(CONFIG_MACH_TQMA6X) += barebox-tq-tqma6s-mba6x.img
+
+pblx-$(CONFIG_MACH_TQMA6X) += start_imx6q_mba6x
+CFG_start_imx6q_mba6x.pblx.imximg = $(board)/tqma6x/flash-header-tqma6q.imxcfg
+imximage-$(CONFIG_MACH_TQMA6X) += start_imx6q_mba6x.pblx.imximg
+FILE_barebox-tq-tqma6q-mba6x.img = start_imx6q_mba6x.pblx.imximg
+image-$(CONFIG_MACH_TQMA6X) += barebox-tq-tqma6q-mba6x.img
+
+pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_2gib
+CFG_start_phytec_pbab01_2gib.pblx.imximg = $(board)/phytec-pfla02/flash-header-phytec-pfla02-2gib.imxcfg
+imximage-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_2gib.pblx.imximg
+FILE_barebox-phytec-pbab01-2gib.img = start_phytec_pbab01_2gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-2gib.img
+
+pblx-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_1gib
+CFG_start_phytec_pbab01_1gib.pblx.imximg = $(board)/phytec-pfla02/flash-header-phytec-pfla02-1gib.imxcfg
+imximage-$(CONFIG_MACH_PHYTEC_PFLA02) += start_phytec_pbab01_1gib.pblx.imximg
+FILE_barebox-phytec-pbab01-1gib.img = start_phytec_pbab01_1gib.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_PFLA02) += barebox-phytec-pbab01-1gib.img
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@ -319,8 +319,13 @@ cmd_imximage_S_dcd=						\
 	echo '.balign STRUCT_ALIGNMENT';			\
 ) > $@

+imxcfg_cpp_flags  = -Wp,-MD,$(depfile) -nostdinc -x assembler-with-cpp
+
+dcd-tmp = $(subst $(comma),_,$(dot-target).dcd.tmp)
+
 quiet_cmd_dcd = DCD     $@
-      cmd_dcd = $(objtree)/scripts/imx/imx-image -d -o $@ -c $<
+      cmd_dcd = $(CPP) $(imxcfg_cpp_flags) -o $(dcd-tmp) $< ; \
+		$(objtree)/scripts/imx/imx-image -d -o $@ -c $(dcd-tmp)

 $(obj)/%.dcd: $(obj)/%.imxcfg FORCE
 	$(call if_changed,dcd)
@ -328,5 +333,8 @@ $(obj)/%.dcd: $(obj)/%.imxcfg FORCE
 $(obj)/%.dcd.S: $(obj)/%.dcd
 	$(call cmd,imximage_S_dcd)

+imximg-tmp = $(subst $(comma),_,$(dot-target).imxcfg.tmp)
+
 quiet_cmd_imx_image = IMX-IMG $@
-      cmd_imx_image = $(objtree)/scripts/imx/imx-image -b -c $(CFG_$(@F)) -f $< -o $@
+      cmd_imx_image = $(CPP) $(imxcfg_cpp_flags) -o $(imximg-tmp) $(CFG_$(@F)) ; \
+		      $(objtree)/scripts/imx/imx-image -o $@ -b -c $(imximg-tmp) -f $<
--- a/scripts/imx/imx-image.c
+++ b/scripts/imx/imx-image.c
@ -492,12 +492,40 @@ struct command cmds[] = {
 	},
 };

+static char *readcmd(FILE *f)
+{
+	static char *buf;
+	char *str;
+	ssize_t ret;
+
+	if (!buf) {
+		buf = malloc(4096);
+		if (!buf)
+			return NULL;
+	}
+
+	str = buf;
+	*str = 0;
+
+	while (1) {
+		ret = fread(str, 1, 1, f);
+		if (!ret)
+			return strlen(buf) ? buf : NULL;
+
+		if (*str == '\n' || *str == ';') {
+			*str = 0;
+			return buf;
+		}
+
+		str++;
+	}
+}
+
 static int parse_config(const char *filename)
 {
 	FILE *f;
 	int lineno = 0;
 	char *line = NULL, *tmp;
-	size_t len;
 	char *argv[MAXARGS];
 	int nargs, i, ret;

@ -507,13 +535,14 @@ static int parse_config(const char *filename)
 		exit(1);
 	}

-	while ((getline(&line, &len, f)) > 0) {
+	while (1) {
+		line = readcmd(f);
+		if (!line)
+			break;
+
 		lineno++;

 		tmp = strchr(line, '#');
-		if (tmp)
-			*tmp = 0;
-		tmp = strrchr(line, '\n');
 		if (tmp)
 			*tmp = 0;