ARM i.MX53 Loco: Use generic lowlevel init code
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
2d6568b408
commit
504d951ec3
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@ -1,3 +1,2 @@
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obj-y += lowlevel_init.o
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obj-y += board.o
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obj-y += flash_header.o
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@ -34,6 +34,7 @@
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#include <mach/gpio.h>
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#include <mach/imx-nand.h>
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#include <mach/iim.h>
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#include <mach/imx53.h>
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#include <asm/armlinux.h>
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#include <io.h>
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@ -122,6 +123,8 @@ static int loco_console_init(void)
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{
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mxc_iomux_v3_setup_multiple_pads(loco_pads, ARRAY_SIZE(loco_pads));
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mx53_init_lowlevel();
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imx53_add_uart0();
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return 0;
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}
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@ -1,172 +0,0 @@
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/*
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* Copyright (C) 2007 Guennadi Liakhovetski <lg@denx.de>
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* Copyright (C) 2009 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <config.h>
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#include <mach/imx-regs.h>
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#include <mach/clock-imx51_53.h>
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/*
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* L2CC Cache setup/invalidation/disable
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*/
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.macro init_l2cc
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/* explicitly disable L2 cache */
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mrc 15, 0, r0, c1, c0, 1
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bic r0, r0, #0x2
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mcr 15, 0, r0, c1, c0, 1
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/* reconfigure L2 cache aux control reg */
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mov r0, #0xC0 /* tag RAM */
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add r0, r0, #0x4 /* data RAM */
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orr r0, r0, #(1 << 24) /* disable write allocate delay */
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orr r0, r0, #(1 << 23) /* disable write allocate combine */
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orr r0, r0, #(1 << 22) /* disable write allocate */
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cmp r3, #0x10 /* r3 contains the silicon rev */
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/* disable write combine for TO 2 and lower revs */
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orrls r0, r0, #(1 << 25)
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mcr 15, 1, r0, c9, c0, 2
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.endm /* init_l2cc */
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/* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =MX53_AIPS1_BASE_ADDR
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ldr r1, =0x77777777
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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ldr r0, =MX53_AIPS2_BASE_ADDR
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str r1, [r0, #0x0]
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str r1, [r0, #0x4]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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.endm /* init_aips */
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.macro setup_pll pll, freq
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ldr r0, =\pll
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ldr r1, =0x00001232
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str r1, [r0, #MX5_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
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mov r1, #0x2
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str r1, [r0, #MX5_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
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ldr r1, W_DP_OP_\freq
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str r1, [r0, #MX5_PLL_DP_OP]
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str r1, [r0, #MX5_PLL_DP_HFS_OP]
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ldr r1, W_DP_MFD_\freq
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str r1, [r0, #MX5_PLL_DP_MFD]
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str r1, [r0, #MX5_PLL_DP_HFS_MFD]
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ldr r1, W_DP_MFN_\freq
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str r1, [r0, #MX5_PLL_DP_MFN]
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str r1, [r0, #MX5_PLL_DP_HFS_MFN]
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ldr r1, =0x00001232
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str r1, [r0, #MX5_PLL_DP_CTL]
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1: ldr r1, [r0, #MX5_PLL_DP_CTL]
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ands r1, r1, #0x1
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beq 1b
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.endm
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.macro init_clock
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ldr r0, =MX53_CCM_BASE_ADDR
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/* Switch ARM to step clock */
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mov r1, #0x4
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str r1, [r0, #MX5_CCM_CCSR]
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setup_pll MX53_PLL1_BASE_ADDR, 1000
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setup_pll MX53_PLL3_BASE_ADDR, 216
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/* Set the platform clock dividers */
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ldr r0, =MX53_ARM_BASE_ADDR
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ldr r1, =0x00000725
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str r1, [r0, #0x14]
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ldr r0, =MX53_CCM_BASE_ADDR
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mov r1, #0
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str r1, [r0, #MX5_CCM_CACRR]
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/* Switch ARM back to PLL 1 */
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mov r1, #0
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str r1, [r0, #MX5_CCM_CCSR]
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/* Restore the default values in the Gate registers */
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #MX5_CCM_CCGR0]
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str r1, [r0, #MX5_CCM_CCGR1]
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str r1, [r0, #MX5_CCM_CCGR2]
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str r1, [r0, #MX5_CCM_CCGR3]
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str r1, [r0, #MX5_CCM_CCGR4]
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str r1, [r0, #MX5_CCM_CCGR5]
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str r1, [r0, #MX5_CCM_CCGR6]
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#if 0
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str r1, [r0, #MX5_CCM_CCGR7]
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#endif
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ldr r1, [r0, #MX5_CCM_CSCDR1]
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orr r1, r1, #0x3f
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eor r1, r1, #0x3f
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orr r1, r1, #0x21
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str r1, [r0, #MX5_CCM_CSCDR1]
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/* make sure divider effective */
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1: ldr r1, [r0, #MX5_CCM_CDHIPR]
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cmp r1, #0x0
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bne 1b
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mov r1, #0x0
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str r1, [r0, #MX5_CCM_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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add r1, r1, #0x00000F0
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str r1, [r0, #MX5_CCM_CCOSR]
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.endm
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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init_l2cc
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init_aips
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init_clock
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mov pc, r10
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/* Board level setting value */
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W_DP_OP_1000: .word MX5_PLL_DP_OP_1000
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W_DP_MFD_1000: .word MX5_PLL_DP_MFD_1000
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W_DP_MFN_1000: .word MX5_PLL_DP_MFN_1000
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W_DP_OP_800: .word MX5_PLL_DP_OP_800
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W_DP_MFD_800: .word MX5_PLL_DP_MFD_800
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W_DP_MFN_800: .word MX5_PLL_DP_MFN_800
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W_DP_OP_665: .word MX5_PLL_DP_OP_665
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W_DP_MFD_665: .word MX5_PLL_DP_MFD_665
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W_DP_MFN_665: .word MX5_PLL_DP_MFN_665
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W_DP_OP_216: .word MX5_PLL_DP_OP_216
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W_DP_MFD_216: .word MX5_PLL_DP_MFD_216
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W_DP_MFN_216: .word MX5_PLL_DP_MFN_216
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@ -401,7 +401,6 @@ choice
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config MACH_FREESCALE_MX53_LOCO
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bool "Freescale i.MX53 LOCO"
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select MACH_HAS_LOWLEVEL_INIT
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endchoice
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