diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi index efc0531c9..4d430878c 100644 --- a/arch/mips/dts/ar9331.dtsi +++ b/arch/mips/dts/ar9331.dtsi @@ -1,8 +1,13 @@ -#include +#include #include "skeleton.dtsi" / { + ref: ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -13,7 +18,8 @@ serial0: serial@18020000 { compatible = "qca,ar9330-uart"; reg = <0x18020000 0x14>; - clocks = <&ar9331_clk AR933X_CLK_UART>; + clocks = <&ref>; + clock-names = "uart"; status = "disabled"; }; @@ -27,9 +33,13 @@ status = "disabled"; }; - ar9331_clk: clock { - compatible = "qca,ar933x-clk"; - reg = <0x18050000 0x48>; + pll: pll-controller@18050000 { + compatible = "qca,ar9330-pll"; + reg = <0x18050000 0x100>; + + clocks = <&ref>; + clock-names = "ref"; + #clock-cells = <1>; }; diff --git a/arch/mips/dts/black-swift.dts b/arch/mips/dts/black-swift.dts index d19c381df..aa0aeaeea 100644 --- a/arch/mips/dts/black-swift.dts +++ b/arch/mips/dts/black-swift.dts @@ -37,6 +37,10 @@ }; }; +&ref { + clock-frequency = <25000000>; +}; + &serial0 { status = "okay"; }; diff --git a/arch/mips/dts/tplink-mr3020.dts b/arch/mips/dts/tplink-mr3020.dts index 804d2908f..a315713ba 100644 --- a/arch/mips/dts/tplink-mr3020.dts +++ b/arch/mips/dts/tplink-mr3020.dts @@ -44,6 +44,10 @@ }; }; +&ref { + clock-frequency = <25000000>; +}; + &serial0 { status = "okay"; }; diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c index ffbd4dfab..f5cfd39cd 100644 --- a/drivers/clk/clk-ar933x.c +++ b/drivers/clk/clk-ar933x.c @@ -24,9 +24,9 @@ #include #include -#include +#include -static struct clk *clks[AR933X_CLK_END]; +static struct clk *clks[ATH79_CLK_END]; static struct clk_onecell_data clk_data; struct clk_ar933x { @@ -100,39 +100,19 @@ static struct clk *clk_ar933x(const char *name, const char *parent, return &f->clk; } -static void ar933x_ref_clk_init(void __iomem *base) -{ - u32 t; - unsigned long ref_rate; - - t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP); - if (t & AR933X_BOOTSTRAP_REF_CLK_40) - ref_rate = (40 * 1000 * 1000); - else - ref_rate = (25 * 1000 * 1000); - - clks[AR933X_CLK_REF] = clk_fixed("ref", ref_rate); -} - static void ar933x_pll_init(void __iomem *base) { - clks[AR933X_CLK_UART] = clk_fixed_factor("uart", "ref", 1, 1, - CLK_SET_RATE_PARENT); - - clks[AR933X_CLK_CPU] = clk_ar933x("cpu", "ref", base, + clks[ATH79_CLK_CPU] = clk_ar933x("cpu", "ref", base, AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT, AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK); - clks[AR933X_CLK_DDR] = clk_ar933x("ddr", "ref", base, + clks[ATH79_CLK_DDR] = clk_ar933x("ddr", "ref", base, AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT, AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK); - clks[AR933X_CLK_AHB] = clk_ar933x("ahb", "ref", base, + clks[ATH79_CLK_AHB] = clk_ar933x("ahb", "ref", base, AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT, AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK); - - clks[AR933X_CLK_WDT] = clk_fixed_factor("wdt", "ahb", 1, 1, - CLK_SET_RATE_PARENT); } static int ar933x_clk_probe(struct device_d *dev) @@ -145,7 +125,6 @@ static int ar933x_clk_probe(struct device_d *dev) return PTR_ERR(iores); base = IOMEM(iores->start); - ar933x_ref_clk_init(base); ar933x_pll_init(base); clk_data.clks = clks; @@ -158,7 +137,7 @@ static int ar933x_clk_probe(struct device_d *dev) static __maybe_unused struct of_device_id ar933x_clk_dt_ids[] = { { - .compatible = "qca,ar933x-clk", + .compatible = "qca,ar9330-pll", }, { /* sentinel */ } diff --git a/include/dt-bindings/clock/ar933x-clk.h b/include/dt-bindings/clock/ar933x-clk.h deleted file mode 100644 index f04893072..000000000 --- a/include/dt-bindings/clock/ar933x-clk.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Antony Pavlov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef __DT_BINDINGS_AR933X_CLK_H -#define __DT_BINDINGS_AR933X_CLK_H - -#define AR933X_CLK_REF 0 -#define AR933X_CLK_UART 1 -#define AR933X_CLK_CPU 2 -#define AR933X_CLK_DDR 3 -#define AR933X_CLK_AHB 4 -#define AR933X_CLK_WDT 5 - -#define AR933X_CLK_END 6 - -#endif /* __DT_BINDINGS_AR933X_CLK_H */