update scb9328 config
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sascha
parent
fdf739c7a5
commit
52fb34f5ad
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@ -18,9 +18,64 @@
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*
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#define CPU200
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#ifdef CPU200
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#define CFG_MPCTL0_VAL 0x00321431
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#else
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#define CFG_MPCTL0_VAL 0x040e200e
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#endif
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#define BUS72
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#ifdef BUS72
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#define CFG_SPCTL0_VAL 0x04002400
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#endif
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#ifdef BUS96
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#define CFG_SPCTL0_VAL 0x04001800
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#endif
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#ifdef BUS64
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#define CFG_SPCTL0_VAL 0x08001800
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#endif
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/* Das ist der BCLK Divider, der aus der System PLL
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BCLK und HCLK erzeugt:
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31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
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0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
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0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
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0x2f001003 : 192MHz/5=38,4MHz
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0x2f000003 : 64MHz/1
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Bit 22: SPLL Restart
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Bit 21: MPLL Restart */
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#ifdef BUS64
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#define CFG_CSCR_VAL 0x2f030003
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#endif
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#ifdef BUS72
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#define CFG_CSCR_VAL 0x2f030403
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#endif
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/* Bit[0:3] contain PERCLK1DIV for UART 1
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0x000b00b ->b<- -> 192MHz/12=16MHz
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0x000b00b ->8<- -> 144MHz/09=16MHz
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0x000b00b ->3<- -> 64MHz/4=16MHz */
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#ifdef BUS96
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#define CFG_PCDR_VAL 0x000b00b5
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#endif
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#ifdef BUS64
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#define CFG_PCDR_VAL 0x000b00b3
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#endif
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#ifdef BUS72
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#define CFG_PCDR_VAL 0x000b00b8
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#endif
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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@ -31,13 +86,13 @@ board_init_lowlevel:
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mov r10, lr
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/* Change PERCLK1DIV to 14 ie 14+1 */
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/* Change PERCLK1DIV to 14 ie 14+1 */
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writel(CFG_PCDR_VAL, PCDR)
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/* set MCU PLL Control Register 0 */
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/* set MCU PLL Control Register 0 */
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writel(CFG_MPCTL0_VAL, MPCTL0)
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/* set mpll restart bit */
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/* set mpll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<21)
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@ -53,10 +108,10 @@ board_init_lowlevel:
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subs r2,r2,#1
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bne 1b
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/* set System PLL Control Register 0 */
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/* set System PLL Control Register 0 */
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writel(CFG_SPCTL0_VAL, SPCTL0)
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/* set spll restart bit */
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/* set spll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<22)
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@ -29,8 +29,6 @@
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#define CONFIG_ARCH_NUMBER MACH_TYPE_SCB9328
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#define CONFIG_BOOT_PARAMS 0x08000100
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#define CFG_CPUSPEED 0x141 /* core clock - register value */
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/*
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* Definitions related to passing arguments to kernel.
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*/
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@ -39,109 +37,7 @@
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#define CONFIG_STACKSIZE (120<<10) /* stack size */
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/* CNC == 3 too long
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#define CFG_CS5U_VAL 0x0000C210 */
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/* #define CFG_CS5U_VAL 0x00008400
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mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
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kaum langsamer ist */
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/* #define CFG_CS5U_VAL 0x00009400
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#define CFG_CS5L_VAL 0x11010D03 */
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#define CONFIG_DM9000_BASE 0x16000000
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#define DM9000_IO CONFIG_DM9000_BASE
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#define DM9000_DATA (CONFIG_DM9000_BASE+4)
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/* #define CONFIG_DM9000_USE_8BIT */
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#define CONFIG_DM9000_USE_16BIT
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/* #define CONFIG_DM9000_USE_32BIT */
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/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
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f_ref=16,777MHz
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0x002a141f: 191,9944MHz
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0x040b2007: 144MHz
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0x042a141f: 96MHz
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0x0811140d: 64MHz
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0x040e200e: 150MHz
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0x00321431: 200MHz
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0x08001800: 64MHz mit 16er Quarz
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0x04001800: 96MHz mit 16er Quarz
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0x04002400: 144MHz mit 16er Quarz
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31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
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|XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
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#define CPU200
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#ifdef CPU200
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#define CFG_MPCTL0_VAL 0x00321431
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#else
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#define CFG_MPCTL0_VAL 0x040e200e
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#endif
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/* #define BUS64 */
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#define BUS72
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#ifdef BUS72
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#define CFG_SPCTL0_VAL 0x04002400
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#endif
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#ifdef BUS96
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#define CFG_SPCTL0_VAL 0x04001800
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#endif
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#ifdef BUS64
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#define CFG_SPCTL0_VAL 0x08001800
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#endif
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/* Das ist der BCLK Divider, der aus der System PLL
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BCLK und HCLK erzeugt:
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31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
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0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
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0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
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0x2f001003 : 192MHz/5=38,4MHz
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0x2f000003 : 64MHz/1
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Bit 22: SPLL Restart
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Bit 21: MPLL Restart */
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#ifdef BUS64
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#define CFG_CSCR_VAL 0x2f030003
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#endif
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#ifdef BUS72
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#define CFG_CSCR_VAL 0x2f030403
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#endif
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#define MHZ16QUARZINUSE
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#ifdef MHZ16QUARZINUSE
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#define CONFIG_SYSPLL_CLK_FREQ 16000000
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#else
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#define CONFIG_SYSPLL_CLK_FREQ 16780000
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#endif
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#define CONFIG_SYS_CLK_FREQ 16780000
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/* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
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#define CFG_FMCR_VAL 0x00000001
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/* Bit[0:3] contain PERCLK1DIV for UART 1
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0x000b00b ->b<- -> 192MHz/12=16MHz
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0x000b00b ->8<- -> 144MHz/09=16MHz
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0x000b00b ->3<- -> 64MHz/4=16MHz */
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#ifdef BUS96
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#define CFG_PCDR_VAL 0x000b00b5
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#endif
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#ifdef BUS64
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#define CFG_PCDR_VAL 0x000b00b3
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#endif
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#ifdef BUS72
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#define CFG_PCDR_VAL 0x000b00b8
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#endif
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#endif /* __CONFIG_H */
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