ARM i.MX1: give register base addresses a proper MX1_ prefix
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
1abd9ab08f
commit
5455ecea55
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@ -13,14 +13,15 @@
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#include <common.h>
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#include <init.h>
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#include <mach/imx-regs.h>
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static int imx1_init(void)
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{
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add_generic_device("imx1-gpt", 0, NULL, 0x00202000, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 0, NULL, 0x0021c000, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 1, NULL, 0x0021c100, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 2, NULL, 0x0021c200, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 3, NULL, 0x0021c300, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpt", 0, NULL, MX1_TIM1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 0, NULL, MX1_GPIO1_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 1, NULL, MX1_GPIO2_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 2, NULL, MX1_GPIO3_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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add_generic_device("imx1-gpio", 3, NULL, MX1_GPIO4_BASE_ADDR, 0x100, IORESOURCE_MEM, NULL);
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return 0;
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}
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@ -2,10 +2,10 @@
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static inline struct device_d *imx1_add_uart0(void)
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{
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return imx_add_uart((void *)IMX_UART1_BASE, 0);
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return imx_add_uart((void *)MX1_UART1_BASE_ADDR, 0);
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}
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static inline struct device_d *imx1_add_uart1(void)
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{
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return imx_add_uart((void *)IMX_UART2_BASE, 1);
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return imx_add_uart((void *)MX1_UART2_BASE_ADDR, 1);
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}
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@ -5,77 +5,105 @@
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#error "Please do not include directly"
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#endif
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#define IMX_IO_BASE 0x00200000
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#define MX1_IO_BASE_ADDR 0x00200000
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#define MX1_IO_SIZE SZ_1M
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#define MX1_CS0_PHYS 0x10000000
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#define MX1_CS0_SIZE 0x02000000
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#define MX1_CS1_PHYS 0x12000000
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#define MX1_CS1_SIZE 0x01000000
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#define MX1_CS2_PHYS 0x13000000
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#define MX1_CS2_SIZE 0x01000000
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#define MX1_CS3_PHYS 0x14000000
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#define MX1_CS3_SIZE 0x01000000
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#define MX1_CS4_PHYS 0x15000000
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#define MX1_CS4_SIZE 0x01000000
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#define MX1_CS5_PHYS 0x16000000
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#define MX1_CS5_SIZE 0x01000000
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/*
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* Register BASEs, based on OFFSETs
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*/
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#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
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#define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
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#define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
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#define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
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#define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
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#define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
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#define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
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#define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
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#define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
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#define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
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#define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
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#define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
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#define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
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#define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
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#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
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#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
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#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
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#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
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#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
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#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
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#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
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#define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
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#define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE)
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#define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
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#define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
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#define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
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#define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
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#define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
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#define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
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#define MX1_AIPI1_BASE_ADDR (0x00000 + MX1_IO_BASE_ADDR)
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#define MX1_WDT_BASE_ADDR (0x01000 + MX1_IO_BASE_ADDR)
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#define MX1_TIM1_BASE_ADDR (0x02000 + MX1_IO_BASE_ADDR)
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#define MX1_TIM2_BASE_ADDR (0x03000 + MX1_IO_BASE_ADDR)
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#define MX1_RTC_BASE_ADDR (0x04000 + MX1_IO_BASE_ADDR)
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#define MX1_LCDC_BASE_ADDR (0x05000 + MX1_IO_BASE_ADDR)
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#define MX1_UART1_BASE_ADDR (0x06000 + MX1_IO_BASE_ADDR)
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#define MX1_UART2_BASE_ADDR (0x07000 + MX1_IO_BASE_ADDR)
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#define MX1_PWM_BASE_ADDR (0x08000 + MX1_IO_BASE_ADDR)
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#define MX1_DMA_BASE_ADDR (0x09000 + MX1_IO_BASE_ADDR)
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#define MX1_AIPI2_BASE_ADDR (0x10000 + MX1_IO_BASE_ADDR)
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#define MX1_SIM_BASE_ADDR (0x11000 + MX1_IO_BASE_ADDR)
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#define MX1_USBD_BASE_ADDR (0x12000 + MX1_IO_BASE_ADDR)
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#define MX1_CSPI1_BASE_ADDR (0x13000 + MX1_IO_BASE_ADDR)
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#define MX1_MMC_BASE_ADDR (0x14000 + MX1_IO_BASE_ADDR)
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#define MX1_ASP_BASE_ADDR (0x15000 + MX1_IO_BASE_ADDR)
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#define MX1_BTA_BASE_ADDR (0x16000 + MX1_IO_BASE_ADDR)
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#define MX1_I2C_BASE_ADDR (0x17000 + MX1_IO_BASE_ADDR)
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#define MX1_SSI_BASE_ADDR (0x18000 + MX1_IO_BASE_ADDR)
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#define MX1_CSPI2_BASE_ADDR (0x19000 + MX1_IO_BASE_ADDR)
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#define MX1_MSHC_BASE_ADDR (0x1A000 + MX1_IO_BASE_ADDR)
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#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
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#define MX1_SCM_BASE_ADDR (0x1B800 + MX1_IO_BASE_ADDR)
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#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
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#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
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#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
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#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
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#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
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#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
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#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
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#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
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#define MX1_AVIC_BASE_ADDR (0x23000 + MX1_IO_BASE_ADDR)
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#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
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/* FIXME: get rid of these */
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#define IMX_TIM1_BASE MX1_CCM_BASE_ADDR
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#define IMX_WDT_BASE MX1_WDT_BASE_ADDR
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#define IMX_GPIO_BASE MX1_GPIO_BASE_ADDR
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/* SYSCTRL Registers */
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#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
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#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
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#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
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#define SIDR __REG(MX1_SCM_BASE_ADDR + 0x4) /* Silicon ID Register */
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#define FMCR __REG(MX1_SCM_BASE_ADDR + 0x8) /* Function Multiplex Control Register */
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#define GPCR __REG(MX1_SCM_BASE_ADDR + 0xC) /* Function Multiplex Control Register */
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/* SDRAM controller registers */
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#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
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#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
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#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
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#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
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#define SDCTL0 __REG(MX1_SDRAMC_BASE_ADDR) /* SDRAM 0 Control Register */
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#define SDCTL1 __REG(MX1_SDRAMC_BASE_ADDR + 0x4) /* SDRAM 1 Control Register */
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#define SDMISC __REG(MX1_SDRAMC_BASE_ADDR + 0x14) /* Miscellaneous Register */
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#define SDRST __REG(MX1_SDRAMC_BASE_ADDR + 0x18) /* SDRAM Reset Register */
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/* PLL registers */
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#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
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#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
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#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
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#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
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#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
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#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
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#define CSCR __REG(MX1_CCM_BASE_ADDR) /* Clock Source Control Register */
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#define MPCTL0 __REG(MX1_CCM_BASE_ADDR + 0x4) /* MCU PLL Control Register 0 */
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#define MPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x8) /* MCU PLL and System Clock Register 1 */
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#define SPCTL0 __REG(MX1_CCM_BASE_ADDR + 0xc) /* System PLL Control Register 0 */
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#define SPCTL1 __REG(MX1_CCM_BASE_ADDR + 0x10) /* System PLL Control Register 1 */
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#define PCDR __REG(MX1_CCM_BASE_ADDR + 0x20) /* Peripheral Clock Divider Register */
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#define CSCR_MPLL_RESTART (1<<21)
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/* Chip Select Registers */
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#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
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#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
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#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
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#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
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#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
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#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
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#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
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#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
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#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
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#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
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#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
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#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
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#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
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#define CS0U __REG(MX1_EIM_BASE_ADDR) /* Chip Select 0 Upper Register */
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#define CS0L __REG(MX1_EIM_BASE_ADDR + 0x4) /* Chip Select 0 Lower Register */
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#define CS1U __REG(MX1_EIM_BASE_ADDR + 0x8) /* Chip Select 1 Upper Register */
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#define CS1L __REG(MX1_EIM_BASE_ADDR + 0xc) /* Chip Select 1 Lower Register */
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#define CS2U __REG(MX1_EIM_BASE_ADDR + 0x10) /* Chip Select 2 Upper Register */
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#define CS2L __REG(MX1_EIM_BASE_ADDR + 0x14) /* Chip Select 2 Lower Register */
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#define CS3U __REG(MX1_EIM_BASE_ADDR + 0x18) /* Chip Select 3 Upper Register */
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#define CS3L __REG(MX1_EIM_BASE_ADDR + 0x1c) /* Chip Select 3 Lower Register */
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#define CS4U __REG(MX1_EIM_BASE_ADDR + 0x20) /* Chip Select 4 Upper Register */
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#define CS4L __REG(MX1_EIM_BASE_ADDR + 0x24) /* Chip Select 4 Lower Register */
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#define CS5U __REG(MX1_EIM_BASE_ADDR + 0x28) /* Chip Select 5 Upper Register */
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#define CS5L __REG(MX1_EIM_BASE_ADDR + 0x2c) /* Chip Select 5 Lower Register */
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#define EIM __REG(MX1_EIM_BASE_ADDR + 0x30) /* EIM Configuration Register */
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/* assignements for GPIO alternate/primary functions */
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