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ARM: i.MX7: initialize architected timer 

This is the same that U-Boot does. The registers are not documented.
Without this the architected timer on the i.MX7 does not work.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2017-01-19 10:30:22 +01:00
parent eb101add59
commit 595da7d68c
1 changed files with 35 additions and 0 deletions
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35
arch/arm/mach-imx/imx7.c
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@ -46,6 +46,39 @@ void imx7_init_lowlevel(void)
writel(0, aips2 + 0x50);
}
#define SC_CNTCR 0x0
#define SC_CNTSR 0x4
#define SC_CNTCV1 0x8
#define SC_CNTCV2 0xc
#define SC_CNTFID0 0x20
#define SC_CNTFID1 0x24
#define SC_CNTFID2 0x28
#define SC_counterid 0xfcc
#define SC_CNTCR_ENABLE (1 << 0)
#define SC_CNTCR_HDBG (1 << 1)
#define SC_CNTCR_FREQ0 (1 << 8)
#define SC_CNTCR_FREQ1 (1 << 9)
static int imx7_timer_init(void)
{
void __iomem *sctr = IOMEM(MX7_SCTR_BASE_ADDR);
unsigned long val, freq;
freq = 8000000;
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
writel(freq, sctr + SC_CNTFID0);
/* Enable system counter */
val = readl(sctr + SC_CNTCR);
val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
writel(val, sctr + SC_CNTCR);
return 0;
}
int imx7_init(void)
{
const char *cputypestr;
@ -53,6 +86,8 @@ int imx7_init(void)
imx7_init_lowlevel();
imx7_timer_init();
imx7_boot_save_loc();
imx7_silicon_revision = imx7_cpu_revision();