ARM: am33xx: Add am33xx_ prefix to SoC specific functions
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -126,11 +126,11 @@ static int beaglebone_board_init(void)
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/* Setup the PLLs and the clocks for the peripherals */
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/* Setup the PLLs and the clocks for the peripherals */
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if (is_beaglebone_black()) {
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if (is_beaglebone_black()) {
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pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
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am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_400);
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am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs,
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am335x_sdram_init(0x18B, &ddr3_cmd_ctrl, &ddr3_regs,
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&ddr3_data);
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&ddr3_data);
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} else {
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} else {
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pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
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am33xx_pll_init(MPUPLL_M_500, 24, DDRPLL_M_266);
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs,
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am335x_sdram_init(0x18B, &ddr2_cmd_ctrl, &ddr2_regs,
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&ddr2_data);
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&ddr2_data);
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}
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}
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@ -68,7 +68,7 @@ static int pcm051_board_init(void)
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if (am33xx_running_in_sdram())
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if (am33xx_running_in_sdram())
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return 0;
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return 0;
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pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
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am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
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am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
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am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
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&MT41J256M8HX15E_2x256M8_regs,
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&MT41J256M8HX15E_2x256M8_regs,
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@ -276,7 +276,7 @@ static void ddr_pll_config(int osc, int ddrpll_M)
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
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while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000001) != 0x1);
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}
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}
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void enable_ddr_clocks(void)
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void am33xx_enable_ddr_clocks(void)
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{
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{
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/* Enable the EMIF_FW Functional clock */
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/* Enable the EMIF_FW Functional clock */
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__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
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__raw_writel(PRCM_MOD_EN, CM_PER_EMIF_FW_CLKCTRL);
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@ -293,7 +293,7 @@ void enable_ddr_clocks(void)
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/*
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/*
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* Configure the PLL/PRCM for necessary peripherals
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* Configure the PLL/PRCM for necessary peripherals
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*/
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*/
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void pll_init(int mpupll_M, int osc, int ddrpll_M)
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void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M)
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{
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{
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mpu_pll_config(mpupll_M, osc);
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mpu_pll_config(mpupll_M, osc);
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core_pll_config(osc);
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core_pll_config(osc);
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@ -337,7 +337,7 @@ void am335x_sdram_init(int ioctrl, const struct am33xx_cmd_control *cmd_ctrl,
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{
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{
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uint32_t val;
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uint32_t val;
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enable_ddr_clocks();
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am33xx_enable_ddr_clocks();
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am33xx_config_vtp();
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am33xx_config_vtp();
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@ -184,7 +184,7 @@
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#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
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#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
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extern void pll_init(int mpupll_M, int osc, int ddrpll_M);
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void am33xx_pll_init(int mpupll_M, int osc, int ddrpll_M);
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extern void enable_ddr_clocks(void);
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void am33xx_enable_ddr_clocks(void);
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#endif /* endif _AM33XX_CLOCKS_H_ */
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#endif /* endif _AM33XX_CLOCKS_H_ */
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