ARM: Add Altera SoCFPGA support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
947d79651e
commit
5b5f6ab6bf
|
@ -117,6 +117,17 @@ config ARCH_PXA
|
|||
bool "Intel/Marvell PXA based"
|
||||
select GENERIC_GPIO
|
||||
|
||||
config ARCH_SOCFPGA
|
||||
bool "Altera SOCFPGA cyclone5"
|
||||
select HAS_DEBUG_LL
|
||||
select ARM_SMP_TWD
|
||||
select CPU_V7
|
||||
select COMMON_CLK
|
||||
select CLKDEV_LOOKUP
|
||||
select GENERIC_GPIO
|
||||
select GPIOLIB
|
||||
select HAVE_PBL_MULTI_IMAGES
|
||||
|
||||
config ARCH_S3C24xx
|
||||
bool "Samsung S3C2410, S3C2440"
|
||||
select ARCH_SAMSUNG
|
||||
|
@ -183,6 +194,7 @@ source arch/arm/mach-nomadik/Kconfig
|
|||
source arch/arm/mach-omap/Kconfig
|
||||
source arch/arm/mach-pxa/Kconfig
|
||||
source arch/arm/mach-samsung/Kconfig
|
||||
source arch/arm/mach-socfpga/Kconfig
|
||||
source arch/arm/mach-versatile/Kconfig
|
||||
source arch/arm/mach-vexpress/Kconfig
|
||||
source arch/arm/mach-tegra/Kconfig
|
||||
|
|
|
@ -64,6 +64,7 @@ machine-$(CONFIG_ARCH_NETX) := netx
|
|||
machine-$(CONFIG_ARCH_OMAP) := omap
|
||||
machine-$(CONFIG_ARCH_PXA) := pxa
|
||||
machine-$(CONFIG_ARCH_SAMSUNG) := samsung
|
||||
machine-$(CONFIG_ARCH_SOCFPGA) := socfpga
|
||||
machine-$(CONFIG_ARCH_VERSATILE) := versatile
|
||||
machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
|
||||
machine-$(CONFIG_ARCH_TEGRA) := tegra
|
||||
|
|
|
@ -0,0 +1,648 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
mmc0 = &mmc;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu@1 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
intc: intc@fffed000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0xfffed000 0x1000>,
|
||||
<0xfffec100 0x100>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
device_type = "soc";
|
||||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@ffe01000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0xffe01000 0x1000>;
|
||||
interrupts = <0 180 4>;
|
||||
#dma-cells = <1>;
|
||||
#dma-channels = <8>;
|
||||
#dma-requests = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
clkmgr@ffd04000 {
|
||||
compatible = "altr,clk-mgr";
|
||||
reg = <0xffd04000 0x1000>;
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
osc: osc1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
};
|
||||
|
||||
f2s_periph_ref_clk: f2s_periph_ref_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <10000000>;
|
||||
};
|
||||
|
||||
main_pll: main_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x40>;
|
||||
|
||||
mpuclk: mpuclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <2>;
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
mainclk: mainclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <4>;
|
||||
reg = <0x4C>;
|
||||
};
|
||||
|
||||
dbg_base_clk: dbg_base_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
fixed-divider = <4>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
main_qspi_clk: main_qspi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x54>;
|
||||
};
|
||||
|
||||
main_nand_sdmmc_clk: main_nand_sdmmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x58>;
|
||||
};
|
||||
|
||||
cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&main_pll>;
|
||||
reg = <0x5C>;
|
||||
};
|
||||
};
|
||||
|
||||
periph_pll: periph_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0x80>;
|
||||
|
||||
emac0_clk: emac0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x88>;
|
||||
};
|
||||
|
||||
emac1_clk: emac1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x8C>;
|
||||
};
|
||||
|
||||
per_qspi_clk: per_qsi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x90>;
|
||||
};
|
||||
|
||||
per_nand_mmc_clk: per_nand_mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x94>;
|
||||
};
|
||||
|
||||
per_base_clk: per_base_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x98>;
|
||||
};
|
||||
|
||||
h2f_usr1_clk: h2f_usr1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&periph_pll>;
|
||||
reg = <0x9C>;
|
||||
};
|
||||
};
|
||||
|
||||
sdram_pll: sdram_pll {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-pll-clock";
|
||||
clocks = <&osc>;
|
||||
reg = <0xC0>;
|
||||
|
||||
ddr_dqs_clk: ddr_dqs_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xC8>;
|
||||
};
|
||||
|
||||
ddr_2x_dqs_clk: ddr_2x_dqs_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xCC>;
|
||||
};
|
||||
|
||||
ddr_dq_clk: ddr_dq_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xD0>;
|
||||
};
|
||||
|
||||
h2f_usr2_clk: h2f_usr2_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-perip-clk";
|
||||
clocks = <&sdram_pll>;
|
||||
reg = <0xD4>;
|
||||
};
|
||||
};
|
||||
|
||||
mpu_periph_clk: mpu_periph_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mpuclk>;
|
||||
fixed-divider = <4>;
|
||||
};
|
||||
|
||||
mpu_l2_ram_clk: mpu_l2_ram_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mpuclk>;
|
||||
fixed-divider = <2>;
|
||||
};
|
||||
|
||||
l4_main_clk: l4_main_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>;
|
||||
clk-gate = <0x60 0>;
|
||||
};
|
||||
|
||||
l3_main_clk: l3_main_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>;
|
||||
};
|
||||
|
||||
l3_mp_clk: l3_mp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>;
|
||||
div-reg = <0x64 0 2>;
|
||||
clk-gate = <0x60 1>;
|
||||
};
|
||||
|
||||
l3_sp_clk: l3_sp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>;
|
||||
div-reg = <0x64 2 2>;
|
||||
};
|
||||
|
||||
l4_mp_clk: l4_mp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>, <&per_base_clk>;
|
||||
div-reg = <0x64 4 3>;
|
||||
parent-reg = <0x70 0 1>;
|
||||
clk-gate = <0x60 2>;
|
||||
};
|
||||
|
||||
l4_sp_clk: l4_sp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&mainclk>, <&per_base_clk>;
|
||||
div-reg = <0x64 7 3>;
|
||||
parent-reg = <0x70 1 1>;
|
||||
clk-gate = <0x60 3>;
|
||||
};
|
||||
|
||||
dbg_at_clk: dbg_at_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&dbg_base_clk>;
|
||||
div-reg = <0x68 0 2>;
|
||||
clk-gate = <0x60 4>;
|
||||
};
|
||||
|
||||
dbg_clk: dbg_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&dbg_base_clk>;
|
||||
div-reg = <0x68 2 2>;
|
||||
clk-gate = <0x60 5>;
|
||||
};
|
||||
|
||||
dbg_trace_clk: dbg_trace_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&dbg_base_clk>;
|
||||
div-reg = <0x6C 0 3>;
|
||||
clk-gate = <0x60 6>;
|
||||
};
|
||||
|
||||
dbg_timer_clk: dbg_timer_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&dbg_base_clk>;
|
||||
clk-gate = <0x60 7>;
|
||||
};
|
||||
|
||||
cfg_clk: cfg_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&cfg_h2f_usr0_clk>;
|
||||
clk-gate = <0x60 8>;
|
||||
};
|
||||
|
||||
h2f_user0_clk: h2f_user0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&cfg_h2f_usr0_clk>;
|
||||
clk-gate = <0x60 9>;
|
||||
};
|
||||
|
||||
emac_0_clk: emac_0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&emac0_clk>;
|
||||
clk-gate = <0xa0 0>;
|
||||
};
|
||||
|
||||
emac_1_clk: emac_1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&emac1_clk>;
|
||||
clk-gate = <0xa0 1>;
|
||||
};
|
||||
|
||||
usb_mp_clk: usb_mp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&per_base_clk>;
|
||||
clk-gate = <0xa0 2>;
|
||||
div-reg = <0xa4 0 3>;
|
||||
};
|
||||
|
||||
spi_m_clk: spi_m_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&per_base_clk>;
|
||||
clk-gate = <0xa0 3>;
|
||||
div-reg = <0xa4 3 3>;
|
||||
};
|
||||
|
||||
can0_clk: can0_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&per_base_clk>;
|
||||
clk-gate = <0xa0 4>;
|
||||
div-reg = <0xa4 6 3>;
|
||||
};
|
||||
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&per_base_clk>;
|
||||
clk-gate = <0xa0 5>;
|
||||
div-reg = <0xa4 9 3>;
|
||||
};
|
||||
|
||||
gpio_db_clk: gpio_db_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&per_base_clk>;
|
||||
clk-gate = <0xa0 6>;
|
||||
div-reg = <0xa8 0 24>;
|
||||
};
|
||||
|
||||
h2f_user1_clk: h2f_user1_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&h2f_usr1_clk>;
|
||||
clk-gate = <0xa0 7>;
|
||||
};
|
||||
|
||||
sdmmc_clk: sdmmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 8>;
|
||||
parent-reg = <0xac 0 2>;
|
||||
};
|
||||
|
||||
nand_x_clk: nand_x_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 9>;
|
||||
};
|
||||
|
||||
nand_clk: nand_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
|
||||
clk-gate = <0xa0 10>;
|
||||
fixed-divider = <4>;
|
||||
parent-reg = <0xac 2 2>;
|
||||
};
|
||||
|
||||
qspi_clk: qspi_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "altr,socfpga-gate-clk";
|
||||
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
|
||||
clk-gate = <0xa0 11>;
|
||||
parent-reg = <0xac 4 2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gmac0: ethernet@ff700000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff700000 0x2000>;
|
||||
interrupts = <0 115 4>;
|
||||
interrupt-names = "macirq";
|
||||
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
||||
clocks = <&emac_0_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac1: ethernet@ff702000 {
|
||||
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
|
||||
reg = <0xff702000 0x2000>;
|
||||
interrupts = <0 120 4>;
|
||||
interrupt-names = "macirq";
|
||||
mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
|
||||
clocks = <&emac_1_clk>;
|
||||
clock-names = "stmmaceth";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@ff708000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff708000 0x1000>;
|
||||
interrupts = <0 164 4>;
|
||||
width = <29>;
|
||||
virtual_irq_start = <257>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&per_base_clk>;
|
||||
};
|
||||
|
||||
gpio1: gpio@ff709000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff709000 0x1000>;
|
||||
interrupts = <0 165 4>;
|
||||
width = <29>;
|
||||
virtual_irq_start = <286>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&per_base_clk>;
|
||||
};
|
||||
|
||||
gpio2: gpio@ff70a000 {
|
||||
compatible = "snps,dw-apb-gpio";
|
||||
reg = <0xff70a000 0x1000>;
|
||||
interrupts = <0 166 4>;
|
||||
width = <27>;
|
||||
virtual_irq_start = <315>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
clocks = <&per_base_clk>;
|
||||
};
|
||||
|
||||
L2: l2-cache@fffef000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0xfffef000 0x1000>;
|
||||
interrupts = <0 38 0x04>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
mmc: dwmmc0@ff704000 {
|
||||
compatible = "altr,socfpga-dw-mshc";
|
||||
reg = <0xff704000 0x1000>;
|
||||
interrupts = <0 139 4>;
|
||||
fifo-depth = <0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&l4_mp_clk>, <&sdmmc_clk>;
|
||||
clock-names = "biu", "ciu";
|
||||
dw-mshc-ciu-div = <3>;
|
||||
};
|
||||
|
||||
nand0: nand@ff900000 {
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
compatible = "denali,denali-nand-dt";
|
||||
reg = <0xff900000 0x100000>,
|
||||
<0xffb80000 0x10000>;
|
||||
reg-names = "nand_data", "denali_reg";
|
||||
interrupts = <0x0 0x90 0x4>;
|
||||
dma-mask = <0xffffffff>;
|
||||
clocks = <&nand_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@0xffc04000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc04000 0x1000>;
|
||||
clock-frequency = <400000000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 158 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@0xffc05000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc05000 0x1000>;
|
||||
clock-frequency = <100000000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 159 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@0xffc06000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc06000 0x1000>;
|
||||
clock-frequency = <100000000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 160 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@0xffc07000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "snps,designware-i2c";
|
||||
reg = <0xffc07000 0x1000>;
|
||||
clock-frequency = <100000000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
interrupts = <0 161 0x4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Local timer */
|
||||
timer@fffec600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xfffec600 0x100>;
|
||||
interrupts = <1 13 0xf04>;
|
||||
clocks = <&mpu_periph_clk>;
|
||||
};
|
||||
|
||||
timer@ffc08000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 167 4>;
|
||||
reg = <0xffc08000 0x1000>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
||||
timer@ffc09000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 168 4>;
|
||||
reg = <0xffc09000 0x1000>;
|
||||
clocks = <&osc>;
|
||||
};
|
||||
|
||||
timer@ffd00000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 169 4>;
|
||||
reg = <0xffd00000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
};
|
||||
|
||||
timer@ffd01000 {
|
||||
compatible = "snps,dw-apb-timer";
|
||||
interrupts = <0 170 4>;
|
||||
reg = <0xffd01000 0x1000>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
};
|
||||
|
||||
uart0: serial0@ffc02000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc02000 0x1000>;
|
||||
interrupts = <0 162 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
};
|
||||
|
||||
uart1: serial1@ffc03000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xffc03000 0x1000>;
|
||||
interrupts = <0 163 4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&l4_sp_clk>;
|
||||
};
|
||||
|
||||
rstmgr@ffd05000 {
|
||||
compatible = "altr,rst-mgr";
|
||||
reg = <0xffd05000 0x1000>;
|
||||
};
|
||||
|
||||
system_mgr: sysmgr@ffd08000 {
|
||||
compatible = "altr,sys-mgr", "syscon";
|
||||
reg = <0xffd08000 0x4000>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/include/ "socfpga.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
clkmgr@ffd04000 {
|
||||
clocks {
|
||||
osc1 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@ff702000 {
|
||||
phy-mode = "rgmii";
|
||||
snps,phy-addr = <0xffffffff>; /* probe for phy addr */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
dwmmc0@ff704000 {
|
||||
num-slots = <1>;
|
||||
supports-highspeed;
|
||||
broken-cd;
|
||||
altr,sysmgr = <&system_mgr>;
|
||||
altr,dw-mshc-sdr-timing = <0 3>;
|
||||
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@ffc08000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer@ffc09000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
timer@ffd00000 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
timer@ffd01000 {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
serial0@ffc02000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
serial1@ffc03000 {
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
sysmgr@ffd08000 {
|
||||
cpu1-start-addr = <0xffd080c4>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,11 @@
|
|||
if ARCH_SOCFPGA
|
||||
|
||||
config ARCH_SOCFPGA_XLOAD
|
||||
bool
|
||||
prompt "Build preloader image"
|
||||
|
||||
config ARCH_TEXT_BASE
|
||||
hex
|
||||
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
|
||||
|
||||
endif
|
|
@ -0,0 +1,4 @@
|
|||
obj-y += generic.o nic301.o bootsource.o reset-manager.o
|
||||
pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
|
||||
pbl-y += clock-manager.o iocsr-config-cyclone5.o
|
||||
obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <bootsource.h>
|
||||
#include <environment.h>
|
||||
#include <init.h>
|
||||
#include <io.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
#include <mach/system-manager.h>
|
||||
|
||||
#define SYSMGR_BOOTINFO 0x14
|
||||
|
||||
static int socfpga_boot_save_loc(void)
|
||||
{
|
||||
enum bootsource src = BOOTSOURCE_UNKNOWN;
|
||||
uint32_t val;
|
||||
|
||||
val = readl(CYCLONE5_SYSMGR_ADDRESS + SYSMGR_BOOTINFO);
|
||||
|
||||
switch (val & 0x7) {
|
||||
case 0:
|
||||
/* reserved */
|
||||
break;
|
||||
case 1:
|
||||
/* FPGA, currently not decoded */
|
||||
break;
|
||||
case 2:
|
||||
case 3:
|
||||
src = BOOTSOURCE_NAND;
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
src = BOOTSOURCE_MMC;
|
||||
break;
|
||||
case 6:
|
||||
case 7:
|
||||
src = BOOTSOURCE_SPI;
|
||||
break;
|
||||
}
|
||||
|
||||
bootsource_set(src);
|
||||
bootsource_set_instance(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(socfpga_boot_save_loc);
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/clock-manager.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
static inline void cm_wait_for_lock(void __iomem *cm, uint32_t mask)
|
||||
{
|
||||
while ((readl(cm + CLKMGR_INTER_ADDRESS) & mask) != mask);
|
||||
}
|
||||
|
||||
/* function to poll in the fsm busy bit */
|
||||
static inline void cm_wait4fsm(void __iomem *cm)
|
||||
{
|
||||
while (readl(cm + CLKMGR_STAT_ADDRESS) & 1);
|
||||
}
|
||||
|
||||
/*
|
||||
* function to write the bypass register which requires a poll of the
|
||||
* busy bit
|
||||
*/
|
||||
static inline void cm_write_bypass(void __iomem *cm, uint32_t val)
|
||||
{
|
||||
writel(val, cm + CLKMGR_BYPASS_ADDRESS);
|
||||
cm_wait4fsm(cm);
|
||||
}
|
||||
|
||||
/* function to write the ctrl register which requires a poll of the busy bit */
|
||||
static inline void cm_write_ctrl(void __iomem *cm, uint32_t val)
|
||||
{
|
||||
writel(val, cm + CLKMGR_CTRL_ADDRESS);
|
||||
cm_wait4fsm(cm);
|
||||
}
|
||||
|
||||
/* function to write a clock register that has phase information */
|
||||
static inline void cm_write_with_phase(uint32_t value,
|
||||
void __iomem *reg, uint32_t mask)
|
||||
{
|
||||
/* poll until phase is zero */
|
||||
while (readl(reg) & mask);
|
||||
|
||||
writel(value, reg);
|
||||
|
||||
while (readl(reg) & mask);
|
||||
}
|
||||
|
||||
/*
|
||||
* Setup clocks while making no assumptions of the
|
||||
* previous state of the clocks.
|
||||
*
|
||||
* - Start by being paranoid and gate all sw managed clocks
|
||||
* - Put all plls in bypass
|
||||
* - Put all plls VCO registers back to reset value (bgpwr dwn).
|
||||
* - Put peripheral and main pll src to reset value to avoid glitch.
|
||||
* - Delay 5 us.
|
||||
* - Deassert bg pwr dn and set numerator and denominator
|
||||
* - Start 7 us timer.
|
||||
* - set internal dividers
|
||||
* - Wait for 7 us timer.
|
||||
* - Enable plls
|
||||
* - Set external dividers while plls are locking
|
||||
* - Wait for pll lock
|
||||
* - Assert/deassert outreset all.
|
||||
* - Take all pll's out of bypass
|
||||
* - Clear safe mode
|
||||
* - set source main and peripheral clocks
|
||||
* - Ungate clocks
|
||||
*/
|
||||
void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg)
|
||||
{
|
||||
uint32_t mainvco, periphvco, val;
|
||||
void *cm = (void *)CYCLONE5_CLKMGR_ADDRESS;
|
||||
|
||||
/* Start by being paranoid and gate all sw managed clocks */
|
||||
|
||||
/*
|
||||
* We need to disable nandclk
|
||||
* and then do another apb access before disabling
|
||||
* gatting off the rest of the periperal clocks.
|
||||
*/
|
||||
val = readl(cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
|
||||
val &= ~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
|
||||
writel(val, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
|
||||
|
||||
/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
|
||||
writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
|
||||
CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
|
||||
CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
|
||||
CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
|
||||
CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
|
||||
CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
|
||||
cm + CLKMGR_MAINPLLGRP_EN_ADDRESS);
|
||||
|
||||
writel(0, cm + CLKMGR_SDRPLLGRP_EN_ADDRESS);
|
||||
|
||||
/* now we can gate off the rest of the peripheral clocks */
|
||||
writel(0, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
|
||||
|
||||
/* Put all plls in bypass */
|
||||
cm_write_bypass(cm,
|
||||
CLKMGR_BYPASS_PERPLL_SET(1) |
|
||||
CLKMGR_BYPASS_SDRPLL_SET(1) |
|
||||
CLKMGR_BYPASS_MAINPLL_SET(1));
|
||||
|
||||
/*
|
||||
* Put all plls VCO registers back to reset value.
|
||||
* Some code might have messed with them.
|
||||
*/
|
||||
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/*
|
||||
* The clocks to the flash devices and the L4_MAIN clocks can
|
||||
* glitch when coming out of safe mode if their source values
|
||||
* are different from their reset value. So the trick it to
|
||||
* put them back to their reset state, and change input
|
||||
* after exiting safe mode but before ungating the clocks.
|
||||
*/
|
||||
writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
|
||||
cm + CLKMGR_PERPLLGRP_SRC_ADDRESS);
|
||||
writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
|
||||
cm + CLKMGR_MAINPLLGRP_L4SRC_ADDRESS);
|
||||
|
||||
/* read back for the required 5 us delay. */
|
||||
readl(cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
readl(cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
readl(cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/*
|
||||
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
|
||||
* with numerator and denominator.
|
||||
*/
|
||||
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->peri_vco_base | CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->sdram_vco_base | CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
writel(cfg->mpuclk, cm + CLKMGR_MAINPLLGRP_MPUCLK_ADDRESS);
|
||||
writel(cfg->mainclk, cm + CLKMGR_MAINPLLGRP_MAINCLK_ADDRESS);
|
||||
writel(cfg->dbgatclk, cm + CLKMGR_MAINPLLGRP_DBGATCLK_ADDRESS);
|
||||
writel(cfg->cfg2fuser0clk, cm + CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_ADDRESS);
|
||||
writel(cfg->emac0clk, cm + CLKMGR_PERPLLGRP_EMAC0CLK_ADDRESS);
|
||||
writel(cfg->emac1clk, cm + CLKMGR_PERPLLGRP_EMAC1CLK_ADDRESS);
|
||||
writel(cfg->mainqspiclk, cm + CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS);
|
||||
writel(cfg->perqspiclk, cm + CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS);
|
||||
writel(cfg->pernandsdmmcclk, cm + CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS);
|
||||
writel(cfg->perbaseclk, cm + CLKMGR_PERPLLGRP_PERBASECLK_ADDRESS);
|
||||
writel(cfg->s2fuser1clk, cm + CLKMGR_PERPLLGRP_S2FUSER1CLK_ADDRESS);
|
||||
|
||||
/* 7 us must have elapsed before we can enable the VCO */
|
||||
__udelay(7);
|
||||
|
||||
/* Enable vco */
|
||||
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* setup dividers while plls are locking */
|
||||
|
||||
/* L3 MP and L3 SP */
|
||||
writel(cfg->maindiv, cm + CLKMGR_MAINPLLGRP_MAINDIV_ADDRESS);
|
||||
writel(cfg->dbgdiv, cm + CLKMGR_MAINPLLGRP_DBGDIV_ADDRESS);
|
||||
writel(cfg->tracediv, cm + CLKMGR_MAINPLLGRP_TRACEDIV_ADDRESS);
|
||||
|
||||
/* L4 MP, L4 SP, can0, and can1 */
|
||||
writel(cfg->perdiv, cm + CLKMGR_PERPLLGRP_DIV_ADDRESS);
|
||||
writel(cfg->gpiodiv, cm + CLKMGR_PERPLLGRP_GPIODIV_ADDRESS);
|
||||
|
||||
cm_wait_for_lock(cm, CLKMGR_INTER_SDRPLLLOCKED_MASK |
|
||||
CLKMGR_INTER_PERPLLLOCKED_MASK |
|
||||
CLKMGR_INTER_MAINPLLLOCKED_MASK);
|
||||
|
||||
/* write the sdram clock counters before toggling outreset all */
|
||||
writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS);
|
||||
|
||||
writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS);
|
||||
|
||||
writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS);
|
||||
|
||||
writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
|
||||
cm + CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS);
|
||||
|
||||
/*
|
||||
* after locking, but before taking out of bypass
|
||||
* assert/deassert outresetall
|
||||
*/
|
||||
mainvco = readl(cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* assert main outresetall */
|
||||
writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
|
||||
periphvco = readl(cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* assert pheriph outresetall */
|
||||
writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* assert sdram outresetall */
|
||||
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1) |
|
||||
CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* deassert main outresetall */
|
||||
writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
|
||||
cm + CLKMGR_MAINPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* deassert pheriph outresetall */
|
||||
writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
|
||||
cm + CLKMGR_PERPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/* deassert sdram outresetall */
|
||||
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN_SET(1),
|
||||
cm + CLKMGR_SDRPLLGRP_VCO_ADDRESS);
|
||||
|
||||
/*
|
||||
* now that we've toggled outreset all, all the clocks
|
||||
* are aligned nicely; so we can change any phase.
|
||||
*/
|
||||
cm_write_with_phase(cfg->ddrdqsclk,
|
||||
cm + CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS,
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
|
||||
|
||||
/* SDRAM DDR2XDQSCLK */
|
||||
cm_write_with_phase(cfg->ddr2xdqsclk,
|
||||
cm + CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS,
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
|
||||
|
||||
cm_write_with_phase(cfg->ddrdqclk,
|
||||
cm + CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS,
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
|
||||
|
||||
cm_write_with_phase(cfg->s2fuser2clk,
|
||||
cm + CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS,
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
|
||||
|
||||
/* Take all three PLLs out of bypass when safe mode is cleared. */
|
||||
cm_write_bypass(cm, 0);
|
||||
|
||||
/* clear safe mode */
|
||||
val = readl(cm + CLKMGR_CTRL_ADDRESS);
|
||||
val |= CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK);
|
||||
cm_write_ctrl(cm, val);
|
||||
|
||||
/*
|
||||
* now that safe mode is clear with clocks gated
|
||||
* it safe to change the source mux for the flashes the the L4_MAIN
|
||||
*/
|
||||
writel(cfg->persrc, cm + CLKMGR_PERPLLGRP_SRC_ADDRESS);
|
||||
writel(cfg->l4src, cm + CLKMGR_MAINPLLGRP_L4SRC_ADDRESS);
|
||||
|
||||
/* Now ungate non-hw-managed clocks */
|
||||
writel(~0, cm + CLKMGR_MAINPLLGRP_EN_ADDRESS);
|
||||
writel(~0, cm + CLKMGR_PERPLLGRP_EN_ADDRESS);
|
||||
writel(~0, cm + CLKMGR_SDRPLLGRP_EN_ADDRESS);
|
||||
}
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/generic.h>
|
||||
#include <mach/freeze-controller.h>
|
||||
|
||||
#define SYSMGR_FRZCTRL_LOOP_PARAM (1000)
|
||||
#define SYSMGR_FRZCTRL_DELAY_LOOP_PARAM (10)
|
||||
|
||||
/*
|
||||
* sys_mgr_frzctrl_freeze_req
|
||||
* Freeze HPS IOs
|
||||
*/
|
||||
int sys_mgr_frzctrl_freeze_req(enum frz_channel_id channel_id)
|
||||
{
|
||||
uint32_t reg, val;
|
||||
void *sm = (void *)CYCLONE5_SYSMGR_ADDRESS;
|
||||
|
||||
/* select software FSM */
|
||||
writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,
|
||||
(sm + SYSMGR_FRZCTRL_SRC_ADDRESS));
|
||||
|
||||
/* Freeze channel ID checking and base address */
|
||||
switch (channel_id) {
|
||||
case FREEZE_CHANNEL_0:
|
||||
case FREEZE_CHANNEL_1:
|
||||
case FREEZE_CHANNEL_2:
|
||||
reg = SYSMGR_FRZCTRL_VIOCTRL_ADDRESS + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT);
|
||||
|
||||
/*
|
||||
* Assert active low enrnsl, plniotri
|
||||
* and niotri signals
|
||||
*/
|
||||
val = readl(sm + reg);
|
||||
val &= ~(SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
|
||||
| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
|
||||
| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK);
|
||||
writel(val, sm + reg);
|
||||
|
||||
/*
|
||||
* Note: Delay for 20ns at min
|
||||
* Assert active low bhniotri signal and de-assert
|
||||
* active high csrdone
|
||||
*/
|
||||
val = readl(sm + reg);
|
||||
val &= ~(SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK | SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK);
|
||||
writel(val, sm + reg);
|
||||
|
||||
break;
|
||||
|
||||
case FREEZE_CHANNEL_3:
|
||||
/*
|
||||
* Assert active low enrnsl, plniotri and
|
||||
* niotri signals
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~(SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
|
||||
| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
|
||||
| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK);
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Note: Delay for 40ns at min
|
||||
* assert active low bhniotri & nfrzdrv signals,
|
||||
* de-assert active high csrdone and assert
|
||||
* active high frzreg and nfrzdrv signals
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~(SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
|
||||
| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
|
||||
| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Note: Delay for 40ns at min
|
||||
* assert active high reinit signal and de-assert
|
||||
* active high pllbiasen signals
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~(SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* sys_mgr_frzctrl_thaw_req
|
||||
* Unfreeze/Thaw HPS IOs
|
||||
*/
|
||||
int sys_mgr_frzctrl_thaw_req(enum frz_channel_id channel_id)
|
||||
{
|
||||
uint32_t reg, val;
|
||||
void *sm = (void *)CYCLONE5_SYSMGR_ADDRESS;
|
||||
|
||||
/* select software FSM */
|
||||
writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, sm + SYSMGR_FRZCTRL_SRC_ADDRESS);
|
||||
|
||||
/* Freeze channel ID checking and base address */
|
||||
switch (channel_id) {
|
||||
case FREEZE_CHANNEL_0:
|
||||
case FREEZE_CHANNEL_1:
|
||||
case FREEZE_CHANNEL_2:
|
||||
reg = SYSMGR_FRZCTRL_VIOCTRL_ADDRESS +
|
||||
(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT);
|
||||
|
||||
/*
|
||||
* Assert active low bhniotri signal and
|
||||
* de-assert active high csrdone
|
||||
*/
|
||||
val = readl(sm + reg);
|
||||
val |= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK |
|
||||
SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
|
||||
writel(val, sm + reg);
|
||||
|
||||
/*
|
||||
* Note: Delay for 20ns at min
|
||||
* de-assert active low plniotri and niotri signals
|
||||
*/
|
||||
val = readl(sm + reg);
|
||||
val |= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK |
|
||||
SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
|
||||
writel(val, sm + reg);
|
||||
|
||||
/*
|
||||
* Note: Delay for 20ns at min
|
||||
* de-assert active low enrnsl signal
|
||||
*/
|
||||
val = readl(sm + reg);
|
||||
val |= SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK;
|
||||
writel(val, sm + reg);
|
||||
|
||||
break;
|
||||
|
||||
case FREEZE_CHANNEL_3:
|
||||
/* de-assert active high reinit signal */
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Note: Delay for 40ns at min
|
||||
* assert active high pllbiasen signals
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Delay 1000 intosc. intosc is based on eosc1
|
||||
* At 25MHz this would be 40us. Play safe, we have time...
|
||||
*/
|
||||
__udelay(1000);
|
||||
|
||||
/*
|
||||
* de-assert active low bhniotri signals,
|
||||
* assert active high csrdone and nfrzdrv signal
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK |
|
||||
SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
|
||||
val &= ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/* Delay 33 intosc */
|
||||
__udelay(100);
|
||||
|
||||
/* de-assert active low plniotri and niotri signals */
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK |
|
||||
SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Note: Delay for 40ns at min
|
||||
* de-assert active high frzreg signal
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
/*
|
||||
* Note: Delay for 40ns at min
|
||||
* de-assert active low enrnsl signal
|
||||
*/
|
||||
val = readl(sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val |= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK;
|
||||
writel(val, sm + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,113 @@
|
|||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <envfs.h>
|
||||
#include <init.h>
|
||||
#include <io.h>
|
||||
#include <fs.h>
|
||||
#include <net/designware.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/stat.h>
|
||||
#include <asm/memory.h>
|
||||
#include <mach/system-manager.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
#include <mach/nic301.h>
|
||||
|
||||
#define SYSMGR_SDMMCGRP_CTRL_REG (CYCLONE5_SYSMGR_ADDRESS + 0x108)
|
||||
#define SYSMGR_SDMMC_CTRL_SMPLSEL(smplsel) (((smplsel) & 0x7) << 3)
|
||||
#define SYSMGR_SDMMC_CTRL_DRVSEL(drvsel) ((drvsel) & 0x7)
|
||||
|
||||
static int socfpga_detect_sdram(void)
|
||||
{
|
||||
void __iomem *base = (void *)CYCLONE5_SDR_ADDRESS;
|
||||
uint32_t dramaddrw, ctrlwidth, memsize;
|
||||
int colbits, rowbits, bankbits;
|
||||
int width_bytes;
|
||||
|
||||
dramaddrw = readl(base + 0x5000 + 0x2c);
|
||||
|
||||
colbits = dramaddrw & 0x1f;
|
||||
rowbits = (dramaddrw >> 5) & 0x1f;
|
||||
bankbits = (dramaddrw >> 10) & 0x7;
|
||||
|
||||
ctrlwidth = readl(base + 0x5000 + 0x60);
|
||||
|
||||
switch (ctrlwidth & 0x3) {
|
||||
default:
|
||||
case 0:
|
||||
width_bytes = 1;
|
||||
break;
|
||||
case 1:
|
||||
width_bytes = 2;
|
||||
break;
|
||||
case 2:
|
||||
width_bytes = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
memsize = (1 << colbits) * (1 << rowbits) * (1 << bankbits) * width_bytes;
|
||||
|
||||
pr_debug("%s: colbits: %d rowbits: %d bankbits: %d width: %d => memsize: 0x%08x\n",
|
||||
__func__, colbits, rowbits, bankbits, width_bytes, memsize);
|
||||
|
||||
arm_add_mem_device("ram0", 0x0, memsize);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int socfpga_init(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
/* Clearing emac0 PHY interface select to 0 */
|
||||
val = readl(CONFIG_SYSMGR_EMAC_CTRL);
|
||||
val &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB);
|
||||
val |= SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
|
||||
writel(val, CONFIG_SYSMGR_EMAC_CTRL);
|
||||
|
||||
writel(SYSMGR_SDMMC_CTRL_DRVSEL(3) | SYSMGR_SDMMC_CTRL_SMPLSEL(0),
|
||||
SYSMGR_SDMMCGRP_CTRL_REG);
|
||||
|
||||
nic301_slave_ns();
|
||||
|
||||
socfpga_detect_sdram();
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(socfpga_init);
|
||||
|
||||
#if defined(CONFIG_DEFAULT_ENVIRONMENT)
|
||||
static int socfpga_env_init(void)
|
||||
{
|
||||
struct stat s;
|
||||
char *diskdev, *partname;
|
||||
int ret;
|
||||
|
||||
diskdev = "mmc0";
|
||||
|
||||
device_detect_by_name(diskdev);
|
||||
|
||||
partname = asprintf("/dev/%s.1", diskdev);
|
||||
|
||||
ret = stat(partname, &s);
|
||||
|
||||
if (ret) {
|
||||
printf("no %s. using default env\n", diskdev);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
mkdir("/boot", 0666);
|
||||
ret = mount(partname, "fat", "/boot");
|
||||
if (ret) {
|
||||
printf("failed to mount %s\n", diskdev);
|
||||
goto out_free;
|
||||
}
|
||||
|
||||
default_environment_path = "/boot/barebox.env";
|
||||
|
||||
out_free:
|
||||
free(partname);
|
||||
return 0;
|
||||
}
|
||||
late_initcall(socfpga_env_init);
|
||||
#endif
|
|
@ -0,0 +1,188 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_MANAGER_H_
|
||||
#define _CLOCK_MANAGER_H_
|
||||
|
||||
struct socfpga_cm_config {
|
||||
/* main group */
|
||||
uint32_t main_vco_base;
|
||||
uint32_t mpuclk;
|
||||
uint32_t mainclk;
|
||||
uint32_t dbgatclk;
|
||||
uint32_t mainqspiclk;
|
||||
uint32_t mainnandsdmmcclk;
|
||||
uint32_t cfg2fuser0clk;
|
||||
uint32_t maindiv;
|
||||
uint32_t dbgdiv;
|
||||
uint32_t tracediv;
|
||||
uint32_t l4src;
|
||||
|
||||
/* peripheral group */
|
||||
uint32_t peri_vco_base;
|
||||
uint32_t emac0clk;
|
||||
uint32_t emac1clk;
|
||||
uint32_t perqspiclk;
|
||||
uint32_t pernandsdmmcclk;
|
||||
uint32_t perbaseclk;
|
||||
uint32_t s2fuser1clk;
|
||||
uint32_t perdiv;
|
||||
uint32_t gpiodiv;
|
||||
uint32_t persrc;
|
||||
|
||||
/* sdram pll group */
|
||||
uint32_t sdram_vco_base;
|
||||
uint32_t ddrdqsclk;
|
||||
uint32_t ddr2xdqsclk;
|
||||
uint32_t ddrdqclk;
|
||||
uint32_t s2fuser2clk;
|
||||
};
|
||||
|
||||
void socfpga_cm_basic_init(const struct socfpga_cm_config *cfg);
|
||||
|
||||
#define CLKMGR_CTRL_ADDRESS 0x0
|
||||
#define CLKMGR_BYPASS_ADDRESS 0x4
|
||||
#define CLKMGR_INTER_ADDRESS 0x8
|
||||
#define CLKMGR_INTREN_ADDRESS 0xc
|
||||
#define CLKMGR_DBCTRL_ADDRESS 0x10
|
||||
#define CLKMGR_STAT_ADDRESS 0x14
|
||||
#define CLKMGR_MAINPLLGRP_ADDRESS 0x40
|
||||
#define CLKMGR_MAINPLLGRP_VCO_ADDRESS 0x40
|
||||
#define CLKMGR_MAINPLLGRP_MISC_ADDRESS 0x44
|
||||
#define CLKMGR_MAINPLLGRP_MPUCLK_ADDRESS 0x48
|
||||
#define CLKMGR_MAINPLLGRP_MAINCLK_ADDRESS 0x4c
|
||||
#define CLKMGR_MAINPLLGRP_DBGATCLK_ADDRESS 0x50
|
||||
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_ADDRESS 0x54
|
||||
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_ADDRESS 0x58
|
||||
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_ADDRESS 0x5c
|
||||
#define CLKMGR_MAINPLLGRP_EN_ADDRESS 0x60
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_ADDRESS 0x64
|
||||
#define CLKMGR_MAINPLLGRP_DBGDIV_ADDRESS 0x68
|
||||
#define CLKMGR_MAINPLLGRP_TRACEDIV_ADDRESS 0x6c
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_ADDRESS 0x70
|
||||
#define CLKMGR_PERPLLGRP_ADDRESS 0x80
|
||||
#define CLKMGR_PERPLLGRP_VCO_ADDRESS 0x80
|
||||
#define CLKMGR_PERPLLGRP_MISC_ADDRESS 0x84
|
||||
#define CLKMGR_PERPLLGRP_EMAC0CLK_ADDRESS 0x88
|
||||
#define CLKMGR_PERPLLGRP_EMAC1CLK_ADDRESS 0x8c
|
||||
#define CLKMGR_PERPLLGRP_PERQSPICLK_ADDRESS 0x90
|
||||
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_ADDRESS 0x94
|
||||
#define CLKMGR_PERPLLGRP_PERBASECLK_ADDRESS 0x98
|
||||
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_ADDRESS 0x9c
|
||||
#define CLKMGR_PERPLLGRP_EN_ADDRESS 0xa0
|
||||
#define CLKMGR_PERPLLGRP_DIV_ADDRESS 0xa4
|
||||
#define CLKMGR_PERPLLGRP_GPIODIV_ADDRESS 0xa8
|
||||
#define CLKMGR_PERPLLGRP_SRC_ADDRESS 0xac
|
||||
#define CLKMGR_SDRPLLGRP_ADDRESS 0xc0
|
||||
#define CLKMGR_SDRPLLGRP_VCO_ADDRESS 0xc0
|
||||
#define CLKMGR_SDRPLLGRP_CTRL_ADDRESS 0xc4
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_ADDRESS 0xc8
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_ADDRESS 0xcc
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_ADDRESS 0xd0
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_ADDRESS 0xd4
|
||||
#define CLKMGR_SDRPLLGRP_EN_ADDRESS 0xd8
|
||||
|
||||
#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020
|
||||
#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010
|
||||
#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004
|
||||
#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(x) (((x) << 4) & 0x00000070)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(x) (((x) << 7) & 0x00000380)
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_PERPLLGRP_SRC_QSPI_SET(x) (((x) << 4) & 0x00000030)
|
||||
#define CLKMGR_PERPLLGRP_SRC_NAND_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_PERPLLGRP_SRC_SDMMC_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(x) (((x) << 2) & 0x00000004)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_EN_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_PERPLLGRP_VCO_PSRC_SET(x) (((x) << 22) & 0x00c00000)
|
||||
#define CLKMGR_PERPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_PERPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(x) (((x) << 25) & 0x7e000000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_SSRC_SET(x) (((x) << 22) & 0x00c00000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_DENOM_SET(x) (((x) << 16) & 0x003f0000)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_NUMER_SET(x) (((x) << 3) & 0x0000fff8)
|
||||
#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(x) (((x) << 0) & 0x00000007)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(x) (((x) << 0) & 0x00000003)
|
||||
#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(x) (((x) << 2) & 0x0000000c)
|
||||
#define CLKMGR_BYPASS_PERPLL_SET(x) (((x) << 3) & 0x00000008)
|
||||
#define CLKMGR_BYPASS_SDRPLL_SET(x) (((x) << 1) & 0x00000002)
|
||||
#define CLKMGR_BYPASS_MAINPLL_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_PERPLLGRP_DIV_USBCLK_SET(x) (((x) << 0) & 0x00000007)
|
||||
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
|
||||
#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(x) (((x) << 6) & 0x000001c0)
|
||||
#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(x) (((x) << 9) & 0x00000e00)
|
||||
#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100
|
||||
#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080
|
||||
#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040
|
||||
#define CLKMGR_CTRL_SAFEMODE_MASK 0x00000001
|
||||
#define CLKMGR_CTRL_SAFEMODE_SET(x) (((x) << 0) & 0x00000001)
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000
|
||||
#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(x) (((x) << 24) & 0x01000000)
|
||||
#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(x) (((x) << 0) & 0x000001ff)
|
||||
#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(x) (((x) << 3) & 0x00000038)
|
||||
#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x00ffffff)
|
||||
#define CLKMGR_BYPASS_PERPLLSRC_SET(x) (((x) << 4) & 0x00000010)
|
||||
#define CLKMGR_BYPASS_SDRPLLSRC_SET(x) (((x) << 2) & 0x00000004)
|
||||
#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015
|
||||
#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000
|
||||
#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x001ffe00
|
||||
#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
|
||||
#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
|
||||
#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff
|
||||
#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff
|
||||
|
||||
#endif /* _CLOCK_MANAGER_H_ */
|
|
@ -0,0 +1,55 @@
|
|||
#ifndef __MACH_DEBUG_LL_H__
|
||||
#define __MACH_DEBUG_LL_H__
|
||||
|
||||
#include <io.h>
|
||||
|
||||
#define UART_BASE 0xffc02000
|
||||
|
||||
#define LSR_THRE 0x20 /* Xmit holding register empty */
|
||||
#define LSR (5 << 2)
|
||||
#define THR (0 << 2)
|
||||
|
||||
#define LCR_BKSE 0x80 /* Bank select enable */
|
||||
#define LSR (5 << 2)
|
||||
#define THR (0 << 2)
|
||||
#define DLL (0 << 2)
|
||||
#define IER (1 << 2)
|
||||
#define DLM (1 << 2)
|
||||
#define FCR (2 << 2)
|
||||
#define LCR (3 << 2)
|
||||
#define MCR (4 << 2)
|
||||
#define MDR (8 << 2)
|
||||
|
||||
static inline unsigned int ns16550_calc_divisor(unsigned int clk,
|
||||
unsigned int baudrate)
|
||||
{
|
||||
return (clk / 16 / baudrate);
|
||||
}
|
||||
|
||||
static inline void INIT_LL(void)
|
||||
{
|
||||
unsigned int clk = 100000000;
|
||||
unsigned int divisor = clk / 16 / 115200;
|
||||
|
||||
writeb(0x00, UART_BASE + LCR);
|
||||
writeb(0x00, UART_BASE + IER);
|
||||
writeb(0x07, UART_BASE + MDR);
|
||||
writeb(LCR_BKSE, UART_BASE + LCR);
|
||||
writeb(divisor & 0xff, UART_BASE + DLL);
|
||||
writeb(divisor >> 8, UART_BASE + DLM);
|
||||
writeb(0x03, UART_BASE + LCR);
|
||||
writeb(0x03, UART_BASE + MCR);
|
||||
writeb(0x07, UART_BASE + FCR);
|
||||
writeb(0x00, UART_BASE + MDR);
|
||||
}
|
||||
|
||||
static inline void PUTC_LL(char c)
|
||||
{
|
||||
/* Wait until there is space in the FIFO */
|
||||
while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
|
||||
/* Send the character */
|
||||
writeb(c, UART_BASE + THR);
|
||||
/* Wait to make sure it hits the line, in case we die too soon. */
|
||||
while ((readb(UART_BASE + LSR) & LSR_THRE) == 0);
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _FREEZE_CONTROLLER_H_
|
||||
#define _FREEZE_CONTROLLER_H_
|
||||
|
||||
#include <mach/socfpga-regs.h>
|
||||
|
||||
#define SYSMGR_FRZCTRL_ADDRESS 0x40
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_ADDRESS 0x40
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_ADDRESS 0x50
|
||||
#define SYSMGR_FRZCTRL_SRC_ADDRESS 0x54
|
||||
#define SYSMGR_FRZCTRL_HWCTRL_ADDRESS 0x58
|
||||
|
||||
#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
|
||||
#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
|
||||
#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
|
||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
|
||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
|
||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
|
||||
|
||||
#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_GET(x) (((x) & 0x00000006) >> 1)
|
||||
|
||||
/*
|
||||
* FreezeChannelSelect
|
||||
* Definition of enum for freeze channel
|
||||
*/
|
||||
enum frz_channel_id {
|
||||
FREEZE_CHANNEL_0 = 0, /* EMAC_IO & MIXED2_IO */
|
||||
FREEZE_CHANNEL_1, /* MIXED1_IO and FLASH_IO */
|
||||
FREEZE_CHANNEL_2, /* General IO */
|
||||
FREEZE_CHANNEL_3, /* DDR IO */
|
||||
};
|
||||
|
||||
/* Shift count needed to calculte for FRZCTRL VIO control register offset */
|
||||
#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT (2)
|
||||
|
||||
/*
|
||||
* Freeze HPS IOs
|
||||
*
|
||||
* FreezeChannelSelect [in] - Freeze channel ID
|
||||
* FreezeControllerFSMSelect [in] - To use hardware or software state machine
|
||||
* If FREEZE_CONTROLLER_FSM_HW is selected for FSM select then the
|
||||
* the freeze channel id is input is ignored. It is default to channel 1
|
||||
*/
|
||||
int sys_mgr_frzctrl_freeze_req(enum frz_channel_id channel_id);
|
||||
|
||||
/*
|
||||
* Unfreeze/Thaw HPS IOs
|
||||
*
|
||||
* FreezeChannelSelect [in] - Freeze channel ID
|
||||
* FreezeControllerFSMSelect [in] - To use hardware or software state machine
|
||||
* If FREEZE_CONTROLLER_FSM_HW is selected for FSM select then the
|
||||
* the freeze channel id is input is ignored. It is default to channel 1
|
||||
*/
|
||||
int sys_mgr_frzctrl_thaw_req(enum frz_channel_id channel_id);
|
||||
|
||||
#endif /* _FREEZE_CONTROLLER_H_ */
|
|
@ -0,0 +1,16 @@
|
|||
#ifndef __MACH_SOCFPGA_GENERIC_H
|
||||
#define __MACH_SOCFPGA_GENERIC_H
|
||||
|
||||
struct socfpga_cm_config;
|
||||
|
||||
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
|
||||
unsigned long *pinmux, int num_pinmux);
|
||||
|
||||
static inline void __udelay(unsigned us)
|
||||
{
|
||||
volatile unsigned int i;
|
||||
|
||||
for (i = 0; i < us * 3; i++);
|
||||
}
|
||||
|
||||
#endif /* __MACH_SOCFPGA_GENERIC_H */
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _NIC301_H_
|
||||
#define _NIC301_H_
|
||||
|
||||
void nic301_slave_ns(void);
|
||||
|
||||
#define L3REGS_SECGRP_LWHPS2FPGAREGS_ADDRESS 0x20
|
||||
#define L3REGS_SECGRP_HPS2FPGAREGS_ADDRESS 0x90
|
||||
#define L3REGS_SECGRP_ACP_ADDRESS 0x94
|
||||
#define L3REGS_SECGRP_ROM_ADDRESS 0x98
|
||||
#define L3REGS_SECGRP_OCRAM_ADDRESS 0x9c
|
||||
#define L3REGS_SECGRP_SDRDATA_ADDRESS 0xa0
|
||||
|
||||
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x00000010
|
||||
#define L3REGS_REMAP_HPS2FPGA_MASK 0x00000008
|
||||
#define L3REGS_REMAP_OCRAM_MASK 0x00000001
|
||||
|
||||
#endif /* _NIC301_H_ */
|
|
@ -0,0 +1,53 @@
|
|||
|
||||
#include <mach/clock-manager.h>
|
||||
|
||||
static struct socfpga_cm_config cm_default_cfg = {
|
||||
/* main group */
|
||||
.main_vco_base = (CLKMGR_MAINPLLGRP_VCO_DENOM_SET(CONFIG_HPS_MAINPLLGRP_VCO_DENOM) |
|
||||
CLKMGR_MAINPLLGRP_VCO_NUMER_SET(CONFIG_HPS_MAINPLLGRP_VCO_NUMER)),
|
||||
.mpuclk = CLKMGR_MAINPLLGRP_MPUCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT),
|
||||
.mainclk = CLKMGR_MAINPLLGRP_MAINCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT),
|
||||
.dbgatclk = CLKMGR_MAINPLLGRP_DBGATCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT),
|
||||
.mainqspiclk = CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT),
|
||||
.mainnandsdmmcclk = CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT),
|
||||
.cfg2fuser0clk = CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_SET(CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT),
|
||||
.maindiv = CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK) |
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK) |
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK) |
|
||||
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_SET(CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK),
|
||||
.dbgdiv = CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_SET(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK) |
|
||||
CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_SET(CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK),
|
||||
.tracediv = CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_SET(CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK),
|
||||
.l4src = CLKMGR_MAINPLLGRP_L4SRC_L4MP_SET(CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP) |
|
||||
CLKMGR_MAINPLLGRP_L4SRC_L4SP_SET(CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP),
|
||||
/* peripheral group */
|
||||
.peri_vco_base = (CLKMGR_PERPLLGRP_VCO_PSRC_SET(CONFIG_HPS_PERPLLGRP_VCO_PSRC) |
|
||||
CLKMGR_PERPLLGRP_VCO_DENOM_SET(CONFIG_HPS_PERPLLGRP_VCO_DENOM) |
|
||||
CLKMGR_PERPLLGRP_VCO_NUMER_SET(CONFIG_HPS_PERPLLGRP_VCO_NUMER)),
|
||||
.emac0clk = CLKMGR_PERPLLGRP_EMAC0CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT),
|
||||
.emac1clk = CLKMGR_PERPLLGRP_EMAC1CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT),
|
||||
.perqspiclk = CLKMGR_PERPLLGRP_PERQSPICLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT),
|
||||
.pernandsdmmcclk = CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT),
|
||||
.perbaseclk = CLKMGR_PERPLLGRP_PERBASECLK_CNT_SET(CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT),
|
||||
.s2fuser1clk = CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_SET(CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT),
|
||||
.perdiv = CLKMGR_PERPLLGRP_DIV_USBCLK_SET(CONFIG_HPS_PERPLLGRP_DIV_USBCLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_SPIMCLK_SET(CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_CAN0CLK_SET(CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK) |
|
||||
CLKMGR_PERPLLGRP_DIV_CAN1CLK_SET(CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK),
|
||||
.gpiodiv = CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_SET(CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK),
|
||||
.persrc = CLKMGR_PERPLLGRP_SRC_QSPI_SET(CONFIG_HPS_PERPLLGRP_SRC_QSPI) |
|
||||
CLKMGR_PERPLLGRP_SRC_NAND_SET(CONFIG_HPS_PERPLLGRP_SRC_NAND) |
|
||||
CLKMGR_PERPLLGRP_SRC_SDMMC_SET(CONFIG_HPS_PERPLLGRP_SRC_SDMMC),
|
||||
/* sdram pll group */
|
||||
.sdram_vco_base = (CLKMGR_SDRPLLGRP_VCO_SSRC_SET(CONFIG_HPS_SDRPLLGRP_VCO_SSRC) |
|
||||
CLKMGR_SDRPLLGRP_VCO_DENOM_SET(CONFIG_HPS_SDRPLLGRP_VCO_DENOM) |
|
||||
CLKMGR_SDRPLLGRP_VCO_NUMER_SET(CONFIG_HPS_SDRPLLGRP_VCO_NUMER)),
|
||||
.ddrdqsclk = CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT),
|
||||
.ddr2xdqsclk = CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT),
|
||||
.ddrdqclk = CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT),
|
||||
.s2fuser2clk = CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE) |
|
||||
CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_SET(CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT),
|
||||
};
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _RESET_MANAGER_H_
|
||||
#define _RESET_MANAGER_H_
|
||||
|
||||
#define RESET_MGR_STATUS_OFS 0x0
|
||||
#define RESET_MGR_CTRL_OFS 0x4
|
||||
#define RESET_MGR_COUNTS_OFS 0x8
|
||||
#define RESET_MGR_MPU_MOD_RESET_OFS 0x10
|
||||
#define RESET_MGR_PER_MOD_RESET_OFS 0x14
|
||||
#define RESET_MGR_PER2_MOD_RESET_OFS 0x18
|
||||
#define RESET_MGR_BRG_MOD_RESET_OFS 0x1c
|
||||
|
||||
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
|
||||
#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8
|
||||
|
||||
#define RSTMGR_PERMODRST_EMAC0_LSB 0
|
||||
#define RSTMGR_PERMODRST_EMAC1_LSB 1
|
||||
#define RSTMGR_PERMODRST_L4WD0_LSB 6
|
||||
#define RSTMGR_PERMODRST_SDR_LSB 29
|
||||
#define RSTMGR_BRGMODRST_HPS2FPGA_MASK 0x00000001
|
||||
#define RSTMGR_BRGMODRST_LWHPS2FPGA_MASK 0x00000002
|
||||
#define RSTMGR_BRGMODRST_FPGA2HPS_MASK 0x00000004
|
||||
|
||||
/* Warm Reset mask */
|
||||
#define RSTMGR_STAT_L4WD1RST_MASK 0x00008000
|
||||
#define RSTMGR_STAT_L4WD0RST_MASK 0x00004000
|
||||
#define RSTMGR_STAT_MPUWD1RST_MASK 0x00002000
|
||||
#define RSTMGR_STAT_MPUWD0RST_MASK 0x00001000
|
||||
#define RSTMGR_STAT_SWWARMRST_MASK 0x00000400
|
||||
#define RSTMGR_STAT_FPGAWARMRST_MASK 0x00000200
|
||||
#define RSTMGR_STAT_NRSTPINRST_MASK 0x00000100
|
||||
#define RSTMGR_WARMRST_MASK 0x0000f700
|
||||
|
||||
#define RSTMGR_CTRL_SDRSELFREFEN_MASK 0x00000010
|
||||
#define RSTMGR_CTRL_FPGAHSEN_MASK 0x00010000
|
||||
#define RSTMGR_CTRL_ETRSTALLEN_MASK 0x00100000
|
||||
|
||||
#define RSTMGR_PERMODRST_EMAC0 (1 << 0)
|
||||
#define RSTMGR_PERMODRST_EMAC1 (1 << 1)
|
||||
#define RSTMGR_PERMODRST_USB0 (1 << 2)
|
||||
#define RSTMGR_PERMODRST_USB1 (1 << 3)
|
||||
#define RSTMGR_PERMODRST_NAND (1 << 4)
|
||||
#define RSTMGR_PERMODRST_QSPI (1 << 5)
|
||||
#define RSTMGR_PERMODRST_L4WD0 (1 << 6)
|
||||
#define RSTMGR_PERMODRST_L4WD1 (1 << 7)
|
||||
#define RSTMGR_PERMODRST_OSC1TIMER1 (1 << 9)
|
||||
#define RSTMGR_PERMODRST_SPTIMER0 (1 << 10)
|
||||
#define RSTMGR_PERMODRST_SPTIMER1 (1 << 11)
|
||||
#define RSTMGR_PERMODRST_I2C0 (1 << 12)
|
||||
#define RSTMGR_PERMODRST_I2C1 (1 << 13)
|
||||
#define RSTMGR_PERMODRST_I2C2 (1 << 14)
|
||||
#define RSTMGR_PERMODRST_I2C3 (1 << 15)
|
||||
#define RSTMGR_PERMODRST_UART0 (1 << 16)
|
||||
#define RSTMGR_PERMODRST_UART1 (1 << 17)
|
||||
#define RSTMGR_PERMODRST_SPIM0 (1 << 18)
|
||||
#define RSTMGR_PERMODRST_SPIM1 (1 << 19)
|
||||
#define RSTMGR_PERMODRST_SPIS0 (1 << 20)
|
||||
#define RSTMGR_PERMODRST_SPIS1 (1 << 21)
|
||||
#define RSTMGR_PERMODRST_SDMMC (1 << 22)
|
||||
#define RSTMGR_PERMODRST_CAN0 (1 << 23)
|
||||
#define RSTMGR_PERMODRST_CAN1 (1 << 24)
|
||||
#define RSTMGR_PERMODRST_GPIO0 (1 << 25)
|
||||
#define RSTMGR_PERMODRST_GPIO1 (1 << 26)
|
||||
#define RSTMGR_PERMODRST_GPIO2 (1 << 27)
|
||||
#define RSTMGR_PERMODRST_DMA (1 << 28)
|
||||
#define RSTMGR_PERMODRST_SDR (1 << 29)
|
||||
|
||||
#define RSTMGR_PER2MODRST_DMAIF0 (1 << 0)
|
||||
#define RSTMGR_PER2MODRST_DMAIF1 (1 << 1)
|
||||
#define RSTMGR_PER2MODRST_DMAIF2 (1 << 2)
|
||||
#define RSTMGR_PER2MODRST_DMAIF3 (1 << 3)
|
||||
#define RSTMGR_PER2MODRST_DMAIF4 (1 << 4)
|
||||
#define RSTMGR_PER2MODRST_DMAIF5 (1 << 5)
|
||||
#define RSTMGR_PER2MODRST_DMAIF6 (1 << 6)
|
||||
#define RSTMGR_PER2MODRST_DMAIF7 (1 << 7)
|
||||
|
||||
#endif /* _RESET_MANAGER_H_ */
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _SCAN_MANAGER_H_
|
||||
#define _SCAN_MANAGER_H_
|
||||
|
||||
#include <io.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
|
||||
/***********************************************************
|
||||
* *
|
||||
* Cyclone5 specific stuff. Get rid of this. *
|
||||
* *
|
||||
***********************************************************/
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955)
|
||||
#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766)
|
||||
|
||||
typedef unsigned long Scan_mgr_entry_t;
|
||||
|
||||
#define NUM_OF_CHAINS (4)
|
||||
#define SHIFT_COUNT_32BIT (5)
|
||||
#define MASK_COUNT_32BIT (0x1F)
|
||||
|
||||
#define SCANMGR_STAT_ADDRESS 0x0
|
||||
#define SCANMGR_EN_ADDRESS 0x4
|
||||
#define SCANMGR_FIFOSINGLEBYTE_ADDRESS 0x10
|
||||
#define SCANMGR_FIFODOUBLEBYTE_ADDRESS 0x14
|
||||
#define SCANMGR_FIFOQUADBYTE_ADDRESS 0x1c
|
||||
|
||||
#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
|
||||
#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
|
||||
|
||||
enum io_scan_chain {
|
||||
IO_SCAN_CHAIN_0 = 0, /* EMAC_IO and MIXED2_IO */
|
||||
IO_SCAN_CHAIN_1, /* MIXED1_IO and FLASH_IO */
|
||||
IO_SCAN_CHAIN_2, /* General IO */
|
||||
IO_SCAN_CHAIN_3, /* DDR IO */
|
||||
IO_SCAN_CHAIN_UNDEFINED
|
||||
};
|
||||
|
||||
#define IO_SCAN_CHAIN_NUM NUM_OF_CHAINS
|
||||
/* Maximum number of IO scan chains */
|
||||
|
||||
#define IO_SCAN_CHAIN_128BIT_SHIFT (7)
|
||||
/*
|
||||
* Shift count to get number of IO scan chain data in granularity
|
||||
* of 128-bit ( N / 128 )
|
||||
*/
|
||||
|
||||
#define IO_SCAN_CHAIN_128BIT_MASK (0x7F)
|
||||
/*
|
||||
* Mask to get residual IO scan chain data in
|
||||
* granularity of 128-bit ( N mod 128 )
|
||||
*/
|
||||
|
||||
#define IO_SCAN_CHAIN_32BIT_SHIFT SHIFT_COUNT_32BIT
|
||||
/*
|
||||
* Shift count to get number of IO scan chain
|
||||
* data in granularity of 32-bit ( N / 32 )
|
||||
*/
|
||||
|
||||
#define IO_SCAN_CHAIN_32BIT_MASK MASK_COUNT_32BIT
|
||||
/*
|
||||
* Mask to get residual IO scan chain data in
|
||||
* granularity of 32-bit ( N mod 32 )
|
||||
*/
|
||||
|
||||
#define IO_SCAN_CHAIN_BYTE_MASK (0xFF)
|
||||
/* Byte mask */
|
||||
|
||||
#define IO_SCAN_CHAIN_PAYLOAD_24BIT (24)
|
||||
/* 24-bits (3 bytes) IO scan chain payload definition */
|
||||
|
||||
#define TDI_TDO_MAX_PAYLOAD (127)
|
||||
/*
|
||||
* Maximum length of TDI_TDO packet payload is 128 bits,
|
||||
* represented by (length - 1) in TDI_TDO header
|
||||
*/
|
||||
|
||||
#define TDI_TDO_HEADER_FIRST_BYTE (0x80)
|
||||
/* TDI_TDO packet header for IO scan chain program */
|
||||
|
||||
#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT (8)
|
||||
/* Position of second command byte for TDI_TDO packet */
|
||||
|
||||
#define MAX_WAITING_DELAY_IO_SCAN_ENGINE (100)
|
||||
/*
|
||||
* Maximum polling loop to wait for IO scan chain engine
|
||||
* becomes idle to prevent infinite loop
|
||||
*/
|
||||
|
||||
/*
|
||||
* scan_mgr_io_scan_chain_prg
|
||||
*
|
||||
* Program HPS IO Scan Chain
|
||||
*
|
||||
* io_scan_chain_id @ref IOScanChainSelect [in] - IO scan chain ID with
|
||||
* range of enumIOScanChainSelect *
|
||||
* io_scan_chain_len_in_bits uint32_t [in] - IO scan chain length in bits
|
||||
* *iocsr_scan_chain @ref Scan_mgr_entry_t [in] - IO scan chain table
|
||||
*/
|
||||
int scan_mgr_io_scan_chain_prg(enum io_scan_chain io_scan_chain_id,
|
||||
uint32_t io_scan_chain_len_in_bits,
|
||||
const unsigned long *iocsr_scan_chain);
|
||||
|
||||
extern const unsigned long iocsr_scan_chain0_table[
|
||||
((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)];
|
||||
extern const unsigned long iocsr_scan_chain1_table[
|
||||
((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)];
|
||||
extern const unsigned long iocsr_scan_chain2_table[
|
||||
((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)];
|
||||
extern const unsigned long iocsr_scan_chain3_table[
|
||||
((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
|
||||
|
||||
#endif /* _SCAN_MANAGER_H_ */
|
|
@ -0,0 +1,399 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _SDRAM_H_
|
||||
#define _SDRAM_H_
|
||||
|
||||
/* Group: sdr.phygrp.sccgrp */
|
||||
#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
|
||||
/* Group: sdr.phygrp.phymgrgrp */
|
||||
#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
|
||||
/* Group: sdr.phygrp.rwmgrgrp */
|
||||
#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
|
||||
/* Group: sdr.phygrp.datamgrgrp */
|
||||
#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
|
||||
/* Group: sdr.phygrp.regfilegrp */
|
||||
#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
|
||||
/* Group: sdr.ctrlgrp */
|
||||
#define SDR_CTRLGRP_ADDRESS 0x5000
|
||||
/* Register: sdr.ctrlgrp.ctrlcfg */
|
||||
#define SDR_CTRLGRP_CTRLCFG_ADDRESS 0x5000
|
||||
/* Register: sdr.ctrlgrp.dramtiming1 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_ADDRESS 0x5004
|
||||
/* Register: sdr.ctrlgrp.dramtiming2 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_ADDRESS 0x5008
|
||||
/* Register: sdr.ctrlgrp.dramtiming3 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_ADDRESS 0x500c
|
||||
/* Register: sdr.ctrlgrp.dramtiming4 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_ADDRESS 0x5010
|
||||
/* Register: sdr.ctrlgrp.lowpwrtiming */
|
||||
#define SDR_CTRLGRP_LOWPWRTIMING_ADDRESS 0x5014
|
||||
/* Register: sdr.ctrlgrp.dramodt */
|
||||
#define SDR_CTRLGRP_DRAMODT_ADDRESS 0x5018
|
||||
/* Register: sdr.ctrlgrp.dramaddrw */
|
||||
#define SDR_CTRLGRP_DRAMADDRW_ADDRESS 0x502c
|
||||
/* Register: sdr.ctrlgrp.dramifwidth */
|
||||
#define SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS 0x5030
|
||||
/* Register: sdr.ctrlgrp.dramdevwidth */
|
||||
#define SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS 0x5034
|
||||
/* Register: sdr.ctrlgrp.dramsts */
|
||||
#define SDR_CTRLGRP_DRAMSTS_ADDRESS 0x5038
|
||||
/* Register: sdr.ctrlgrp.dramintr */
|
||||
#define SDR_CTRLGRP_DRAMINTR_ADDRESS 0x503c
|
||||
/* Register: sdr.ctrlgrp.sbecount */
|
||||
#define SDR_CTRLGRP_SBECOUNT_ADDRESS 0x5040
|
||||
/* Register: sdr.ctrlgrp.dbecount */
|
||||
#define SDR_CTRLGRP_DBECOUNT_ADDRESS 0x5044
|
||||
/* Register: sdr.ctrlgrp.erraddr */
|
||||
#define SDR_CTRLGRP_ERRADDR_ADDRESS 0x5048
|
||||
/* Register: sdr.ctrlgrp.dropcount */
|
||||
#define SDR_CTRLGRP_DROPCOUNT_ADDRESS 0x504c
|
||||
/* Register: sdr.ctrlgrp.dropaddr */
|
||||
#define SDR_CTRLGRP_DROPADDR_ADDRESS 0x5050
|
||||
/* Register: sdr.ctrlgrp.staticcfg */
|
||||
#define SDR_CTRLGRP_STATICCFG_ADDRESS 0x505c
|
||||
/* Register: sdr.ctrlgrp.ctrlwidth */
|
||||
#define SDR_CTRLGRP_CTRLWIDTH_ADDRESS 0x5060
|
||||
/* Register: sdr.ctrlgrp.cportwidth */
|
||||
#define SDR_CTRLGRP_CPORTWIDTH_ADDRESS 0x5064
|
||||
/* Register: sdr.ctrlgrp.cportwmap */
|
||||
#define SDR_CTRLGRP_CPORTWMAP_ADDRESS 0x5068
|
||||
/* Register: sdr.ctrlgrp.cportrmap */
|
||||
#define SDR_CTRLGRP_CPORTRMAP_ADDRESS 0x506c
|
||||
/* Register: sdr.ctrlgrp.rfifocmap */
|
||||
#define SDR_CTRLGRP_RFIFOCMAP_ADDRESS 0x5070
|
||||
/* Register: sdr.ctrlgrp.wfifocmap */
|
||||
#define SDR_CTRLGRP_WFIFOCMAP_ADDRESS 0x5074
|
||||
/* Register: sdr.ctrlgrp.cportrdwr */
|
||||
#define SDR_CTRLGRP_CPORTRDWR_ADDRESS 0x5078
|
||||
/* Register: sdr.ctrlgrp.portcfg */
|
||||
#define SDR_CTRLGRP_PORTCFG_ADDRESS 0x507c
|
||||
/* Register: sdr.ctrlgrp.fpgaportrst */
|
||||
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
|
||||
/* Register: sdr.ctrlgrp.fifocfg */
|
||||
#define SDR_CTRLGRP_FIFOCFG_ADDRESS 0x5088
|
||||
/* Register: sdr.ctrlgrp.mppriority */
|
||||
#define SDR_CTRLGRP_MPPRIORITY_ADDRESS 0x50ac
|
||||
/* Wide Register: sdr.ctrlgrp.mpweight */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_ADDRESS 0x50b0
|
||||
/* Register: sdr.ctrlgrp.mpweight.mpweight_0 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS 0x50b0
|
||||
/* Register: sdr.ctrlgrp.mpweight.mpweight_1 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS 0x50b4
|
||||
/* Register: sdr.ctrlgrp.mpweight.mpweight_2 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS 0x50b8
|
||||
/* Register: sdr.ctrlgrp.mpweight.mpweight_3 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS 0x50bc
|
||||
/* Register: sdr.ctrlgrp.mppacing.mppacing_0 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS 0x50c0
|
||||
/* Register: sdr.ctrlgrp.mppacing.mppacing_1 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS 0x50c4
|
||||
/* Register: sdr.ctrlgrp.mppacing.mppacing_2 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS 0x50c8
|
||||
/* Register: sdr.ctrlgrp.mppacing.mppacing_3 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS 0x50cc
|
||||
/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_0 */
|
||||
#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS 0x50d0
|
||||
/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_1 */
|
||||
#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS 0x50d4
|
||||
/* Register: sdr.ctrlgrp.mpthresholdrst.mpthresholdrst_2 */
|
||||
#define SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS 0x50d8
|
||||
/* Wide Register: sdr.ctrlgrp.phyctrl */
|
||||
#define SDR_CTRLGRP_PHYCTRL_ADDRESS 0x5150
|
||||
/* Register: sdr.ctrlgrp.phyctrl.phyctrl_0 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS 0x5150
|
||||
/* Register: sdr.ctrlgrp.phyctrl.phyctrl_1 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_ADDRESS 0x5154
|
||||
/* Register: sdr.ctrlgrp.phyctrl.phyctrl_2 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_ADDRESS 0x5158
|
||||
/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_0 */
|
||||
/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_0 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
|
||||
/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_1 */
|
||||
/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_1 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
|
||||
/* Register instance: sdr::ctrlgrp::phyctrl.phyctrl_2 */
|
||||
/* Register template referenced: sdr::ctrlgrp::phyctrl::phyctrl_2 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
|
||||
|
||||
/* Register template: sdr::ctrlgrp::ctrlcfg */
|
||||
#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_LSB 26
|
||||
#define SDR_CTRLGRP_CTRLCFG_OUTPUTREG_MASK 0x04000000
|
||||
#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_LSB 25
|
||||
#define SDR_CTRLGRP_CTRLCFG_BURSTTERMEN_MASK 0x02000000
|
||||
#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_LSB 24
|
||||
#define SDR_CTRLGRP_CTRLCFG_BURSTINTREN_MASK 0x01000000
|
||||
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
|
||||
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
|
||||
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
|
||||
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
|
||||
#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
|
||||
#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
|
||||
#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
|
||||
#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
|
||||
#define SDR_CTRLGRP_CTRLCFG_GENDBE_LSB 14
|
||||
#define SDR_CTRLGRP_CTRLCFG_GENDBE_MASK 0x00004000
|
||||
#define SDR_CTRLGRP_CTRLCFG_GENSBE_LSB 13
|
||||
#define SDR_CTRLGRP_CTRLCFG_GENSBE_MASK 0x00002000
|
||||
#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_LSB 12
|
||||
#define SDR_CTRLGRP_CTRLCFG_CFG_ENABLE_ECC_CODE_OVERWRITES_MASK 0x00001000
|
||||
#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
|
||||
#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
|
||||
#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
|
||||
#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
|
||||
#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
|
||||
#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
|
||||
#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
|
||||
#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
|
||||
#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
|
||||
#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
|
||||
/* Register template: sdr::ctrlgrp::dramtiming1 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
|
||||
/* Register template: sdr::ctrlgrp::dramtiming2 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
|
||||
/* Register template: sdr::ctrlgrp::dramtiming3 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
|
||||
/* Register template: sdr::ctrlgrp::dramtiming4 */
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
|
||||
/* Register template: sdr::ctrlgrp::lowpwrtiming */
|
||||
#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
|
||||
#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
|
||||
#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
|
||||
#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
|
||||
/* Register template: sdr::ctrlgrp::dramaddrw */
|
||||
#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
|
||||
#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
|
||||
#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
|
||||
#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
|
||||
#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
|
||||
#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
|
||||
#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
|
||||
/* Register template: sdr::ctrlgrp::dramifwidth */
|
||||
#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
|
||||
/* Register template: sdr::ctrlgrp::dramdevwidth */
|
||||
#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
|
||||
/* Register template: sdr::ctrlgrp::dramintr */
|
||||
#define SDR_CTRLGRP_DRAMINTR_INTRCLR_LSB 4
|
||||
#define SDR_CTRLGRP_DRAMINTR_INTRCLR_MASK 0x00000010
|
||||
#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_LSB 3
|
||||
#define SDR_CTRLGRP_DRAMINTR_CORRDROPMASK_MASK 0x00000008
|
||||
#define SDR_CTRLGRP_DRAMINTR_DBEMASK_LSB 2
|
||||
#define SDR_CTRLGRP_DRAMINTR_DBEMASK_MASK 0x00000004
|
||||
#define SDR_CTRLGRP_DRAMINTR_SBEMASK_LSB 1
|
||||
#define SDR_CTRLGRP_DRAMINTR_SBEMASK_MASK 0x00000002
|
||||
#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
|
||||
/* Register template: sdr::ctrlgrp::sbecount */
|
||||
#define SDR_CTRLGRP_SBECOUNT_COUNT_LSB 0
|
||||
#define SDR_CTRLGRP_SBECOUNT_COUNT_MASK 0x000000ff
|
||||
/* Register template: sdr::ctrlgrp::dbecount */
|
||||
#define SDR_CTRLGRP_DBECOUNT_COUNT_LSB 0
|
||||
#define SDR_CTRLGRP_DBECOUNT_COUNT_MASK 0x000000ff
|
||||
/* Register template: sdr::ctrlgrp::staticcfg */
|
||||
#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
|
||||
#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
|
||||
#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
|
||||
#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
|
||||
#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
|
||||
#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
|
||||
/* Register template: sdr::ctrlgrp::ctrlwidth */
|
||||
#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
|
||||
#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
|
||||
/* Register template: sdr::ctrlgrp::cportwidth */
|
||||
#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
|
||||
#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
|
||||
/* Register template: sdr::ctrlgrp::cportwmap */
|
||||
#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
|
||||
#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
|
||||
/* Register template: sdr::ctrlgrp::cportrmap */
|
||||
#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
|
||||
#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
|
||||
/* Register template: sdr::ctrlgrp::rfifocmap */
|
||||
#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
|
||||
#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
|
||||
/* Register template: sdr::ctrlgrp::wfifocmap */
|
||||
#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
|
||||
#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
|
||||
/* Register template: sdr::ctrlgrp::cportrdwr */
|
||||
#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
|
||||
#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
|
||||
/* Register template: sdr::ctrlgrp::portcfg */
|
||||
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
|
||||
#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
|
||||
#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
|
||||
#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
|
||||
/* Register template: sdr::ctrlgrp::fifocfg */
|
||||
#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
|
||||
#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
|
||||
#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
|
||||
#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
|
||||
/* Register template: sdr::ctrlgrp::mppriority */
|
||||
#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
|
||||
#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
|
||||
/* Wide Register template: sdr::ctrlgrp::mpweight */
|
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
|
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
|
||||
#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
|
||||
/* Wide Register template: sdr::ctrlgrp::mppacing */
|
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
|
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
|
||||
#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
|
||||
/* Wide Register template: sdr::ctrlgrp::mpthresholdrst */
|
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
|
||||
0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
|
||||
0xffffffff
|
||||
/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
|
||||
#define \
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
|
||||
0x0000ffff
|
||||
/* Register template: sdr::ctrlgrp::remappriority */
|
||||
#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
|
||||
#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
|
||||
/* Wide Register template: sdr::ctrlgrp::phyctrl */
|
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_MASK 0xfffff000
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
|
||||
(((x) << 12) & 0xfffff000)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_LSB 10
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_MASK 0x00000c00
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
|
||||
(((x) << 10) & 0x00000c00)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_LSB 9
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_MASK 0x00000200
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
|
||||
(((x) << 9) & 0x00000200)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_LSB 8
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_MASK 0x00000100
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
|
||||
(((x) << 8) & 0x00000100)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_LSB 6
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_MASK 0x000000c0
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
|
||||
(((x) << 6) & 0x000000c0)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_LSB 4
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_MASK 0x00000030
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
|
||||
(((x) << 4) & 0x00000030)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_LSB 2
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_MASK 0x0000000c
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
|
||||
(((x) << 2) & 0x0000000c)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_LSB 0
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_MASK 0x00000003
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
|
||||
(((x) << 0) & 0x00000003)
|
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_LSB 12
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_MASK 0xfffff000
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
|
||||
(((x) << 12) & 0xfffff000)
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_LSB 0
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_MASK 0x00000fff
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
|
||||
(((x) << 0) & 0x00000fff)
|
||||
/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_LSB 0
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_MASK 0x00000fff
|
||||
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
|
||||
(((x) << 0) & 0x00000fff)
|
||||
/* Register template: sdr::ctrlgrp::dramodt */
|
||||
#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
|
||||
#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
|
||||
#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
|
||||
#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
|
||||
/* Register template: sdr::ctrlgrp::fpgaportrst */
|
||||
#define SDR_CTRLGRP_FPGAPORTRST_READ_PORT_0_LSB 0
|
||||
#define SDR_CTRLGRP_FPGAPORTRST_WRITE_PORT_0_LSB 4
|
||||
#define SDR_CTRLGRP_FPGAPORTRST_COMMAND_PORT_0_LSB 8
|
||||
/* Field instance: sdr::ctrlgrp::dramsts */
|
||||
#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
|
||||
#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
|
||||
|
||||
#endif /* _SDRAM_H_ */
|
|
@ -0,0 +1,161 @@
|
|||
#ifndef __MACH_SDRAM_CONFIG_H
|
||||
#define __MACH_SDRAM_CONFIG_H
|
||||
|
||||
#include <mach/sdram.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
#include <mach/system-manager.h>
|
||||
|
||||
static inline void sdram_write(unsigned register_offset, unsigned val)
|
||||
{
|
||||
debug("0x%08x Data 0x%08x\n",
|
||||
(CYCLONE5_SDR_ADDRESS + register_offset), val);
|
||||
/* Write to register */
|
||||
writel(val, (CYCLONE5_SDR_ADDRESS + register_offset));
|
||||
}
|
||||
|
||||
static inline void socfpga_sdram_mmr_init(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << SDR_CTRLGRP_CTRLCFG_MEMBL_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << SDR_CTRLGRP_CTRLCFG_ECCEN_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CTRLCFG_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << SDR_CTRLGRP_DRAMTIMING1_TAL_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << SDR_CTRLGRP_DRAMTIMING1_TCL_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMTIMING1_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << SDR_CTRLGRP_DRAMTIMING2_TRP_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << SDR_CTRLGRP_DRAMTIMING2_TWR_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMTIMING2_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << SDR_CTRLGRP_DRAMTIMING3_TRC_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMTIMING3_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMTIMING4_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB;
|
||||
sdram_write(SDR_CTRLGRP_LOWPWRTIMING_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMADDRW_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMIFWIDTH_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMDEVWIDTH_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << SDR_CTRLGRP_DRAMINTR_INTREN_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMINTR_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << SDR_CTRLGRP_STATICCFG_MEMBL_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB;
|
||||
sdram_write(SDR_CTRLGRP_STATICCFG_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CTRLWIDTH_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB;
|
||||
sdram_write(SDR_CTRLGRP_PORTCFG_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB;
|
||||
sdram_write(SDR_CTRLGRP_FIFOCFG_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPPRIORITY_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_0_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
|
||||
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_1_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_2_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPPACING_MPPACING_3_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_0_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_1_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
|
||||
SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB;
|
||||
sdram_write(SDR_CTRLGRP_MPTHRESHOLDRST_MPTHRESHOLDRST_2_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0;
|
||||
sdram_write(SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CPORTWIDTH_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CPORTWMAP_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CPORTRMAP_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB;
|
||||
sdram_write(SDR_CTRLGRP_RFIFOCMAP_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB;
|
||||
sdram_write(SDR_CTRLGRP_WFIFOCMAP_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB;
|
||||
sdram_write(SDR_CTRLGRP_CPORTRDWR_ADDRESS, val);
|
||||
|
||||
val = CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << SDR_CTRLGRP_DRAMODT_READ_LSB |
|
||||
CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB;
|
||||
sdram_write(SDR_CTRLGRP_DRAMODT_ADDRESS, val);
|
||||
|
||||
val = readl(CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_STATICCFG_ADDRESS);
|
||||
val &= ~(SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK);
|
||||
val |= 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB;
|
||||
writel(val, (CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_STATICCFG_ADDRESS));
|
||||
}
|
||||
#endif /* __MACH_SDRAM_CONFIG_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,448 @@
|
|||
#ifndef _SEQUENCER_H_
|
||||
#define _SEQUENCER_H_
|
||||
|
||||
/*
|
||||
Copyright (c) 2012, Altera Corporation
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of Altera Corporation nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define MRS_MIRROR_PING_PONG_ATSO 0
|
||||
#define DYNAMIC_CALIBRATION_MODE 0
|
||||
#define STATIC_QUICK_CALIBRATION 0
|
||||
#define DISABLE_GUARANTEED_READ 0
|
||||
#define STATIC_SKIP_CALIBRATION 0
|
||||
|
||||
#if ENABLE_ASSERT
|
||||
#define ERR_IE_TEXT "Internal Error: Sub-system: %s, File: %s, Line: %d\n%s%s"
|
||||
|
||||
#define ALTERA_INTERNAL_ERROR(string) \
|
||||
{err_report_internal_error(string, "SEQ", __FILE__, __LINE__); \
|
||||
exit(-1); }
|
||||
|
||||
#define ALTERA_ASSERT(condition) \
|
||||
if (!(condition)) {\
|
||||
ALTERA_INTERNAL_ERROR(#condition); }
|
||||
#define ALTERA_INFO_ASSERT(condition, text) \
|
||||
if (!(condition)) {\
|
||||
ALTERA_INTERNAL_ERROR(text); }
|
||||
|
||||
#else
|
||||
|
||||
#define ALTERA_ASSERT(condition)
|
||||
#define ALTERA_INFO_ASSERT(condition, text)
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if RLDRAMII
|
||||
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (1)
|
||||
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (1)
|
||||
#else
|
||||
#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
|
||||
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
|
||||
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#endif
|
||||
|
||||
#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
|
||||
|
||||
#define RW_MGR_RUN_SINGLE_GROUP BASE_RW_MGR
|
||||
#define RW_MGR_RUN_ALL_GROUPS BASE_RW_MGR + 0x0400
|
||||
|
||||
#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
|
||||
|
||||
#if DDR3
|
||||
#define DDR3_MR1_ODT_MASK 0xFFFFFD99
|
||||
#define DDR3_MR2_ODT_MASK 0xFFFFF9FF
|
||||
#define DDR3_AC_MIRR_MASK 0x020A8
|
||||
#endif /* DDR3 */
|
||||
|
||||
#define RW_MGR_LOAD_CNTR_0 BASE_RW_MGR + 0x0800
|
||||
#define RW_MGR_LOAD_CNTR_1 BASE_RW_MGR + 0x0804
|
||||
#define RW_MGR_LOAD_CNTR_2 BASE_RW_MGR + 0x0808
|
||||
#define RW_MGR_LOAD_CNTR_3 BASE_RW_MGR + 0x080C
|
||||
|
||||
#define RW_MGR_LOAD_JUMP_ADD_0 BASE_RW_MGR + 0x0C00
|
||||
#define RW_MGR_LOAD_JUMP_ADD_1 BASE_RW_MGR + 0x0C04
|
||||
#define RW_MGR_LOAD_JUMP_ADD_2 BASE_RW_MGR + 0x0C08
|
||||
#define RW_MGR_LOAD_JUMP_ADD_3 BASE_RW_MGR + 0x0C0C
|
||||
|
||||
#define RW_MGR_RESET_READ_DATAPATH BASE_RW_MGR + 0x1000
|
||||
#define RW_MGR_SOFT_RESET BASE_RW_MGR + 0x2000
|
||||
|
||||
#define RW_MGR_SET_CS_AND_ODT_MASK BASE_RW_MGR + 0x1400
|
||||
#define RW_MGR_SET_ACTIVE_RANK BASE_RW_MGR + 0x2400
|
||||
|
||||
#define RW_MGR_LOOPBACK_MODE BASE_RW_MGR + 0x0200
|
||||
|
||||
#define RW_MGR_RANK_NONE 0xFF
|
||||
#define RW_MGR_RANK_ALL 0x00
|
||||
|
||||
#define RW_MGR_ODT_MODE_OFF 0
|
||||
#define RW_MGR_ODT_MODE_READ_WRITE 1
|
||||
|
||||
#define NUM_CALIB_REPEAT 1
|
||||
|
||||
#define NUM_READ_TESTS 7
|
||||
#define NUM_READ_PB_TESTS 7
|
||||
#define NUM_WRITE_TESTS 15
|
||||
#define NUM_WRITE_PB_TESTS 31
|
||||
|
||||
#define PASS_ALL_BITS 1
|
||||
#define PASS_ONE_BIT 0
|
||||
|
||||
/* calibration stages */
|
||||
|
||||
#define CAL_STAGE_NIL 0
|
||||
#define CAL_STAGE_VFIFO 1
|
||||
#define CAL_STAGE_WLEVEL 2
|
||||
#define CAL_STAGE_LFIFO 3
|
||||
#define CAL_STAGE_WRITES 4
|
||||
#define CAL_STAGE_FULLTEST 5
|
||||
#define CAL_STAGE_REFRESH 6
|
||||
#define CAL_STAGE_CAL_SKIPPED 7
|
||||
#define CAL_STAGE_CAL_ABORTED 8
|
||||
#define CAL_STAGE_VFIFO_AFTER_WRITES 9
|
||||
|
||||
/* calibration substages */
|
||||
|
||||
#define CAL_SUBSTAGE_NIL 0
|
||||
#define CAL_SUBSTAGE_GUARANTEED_READ 1
|
||||
#define CAL_SUBSTAGE_DQS_EN_PHASE 2
|
||||
#define CAL_SUBSTAGE_VFIFO_CENTER 3
|
||||
#define CAL_SUBSTAGE_WORKING_DELAY 1
|
||||
#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
|
||||
#define CAL_SUBSTAGE_WLEVEL_COPY 3
|
||||
#define CAL_SUBSTAGE_WRITES_CENTER 1
|
||||
#define CAL_SUBSTAGE_READ_LATENCY 1
|
||||
#define CAL_SUBSTAGE_REFRESH 1
|
||||
|
||||
#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
|
||||
#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
|
||||
RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
|
||||
RW_MGR_MEM_IF_READ_DQS_WIDTH)
|
||||
#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
|
||||
#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
|
||||
|
||||
/* length of VFIFO, from SW_MACROS */
|
||||
#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
|
||||
|
||||
/* Memory for data transfer between TCL scripts and NIOS.
|
||||
*
|
||||
* - First word is a command request.
|
||||
* - The remaining words are part of the transfer.
|
||||
*/
|
||||
|
||||
#define BASE_PTR_MGR SEQUENCER_PTR_MGR_INST_BASE
|
||||
#define BASE_PHY_MGR SDR_PHYGRP_PHYMGRGRP_ADDRESS
|
||||
#define BASE_RW_MGR SDR_PHYGRP_RWMGRGRP_ADDRESS
|
||||
#define BASE_DATA_MGR SDR_PHYGRP_DATAMGRGRP_ADDRESS
|
||||
#define BASE_SCC_MGR SDR_PHYGRP_SCCGRP_ADDRESS
|
||||
#define BASE_REG_FILE SDR_PHYGRP_REGFILEGRP_ADDRESS
|
||||
#define BASE_TIMER SEQUENCER_TIMER_INST_BASE
|
||||
#define BASE_MMR SDR_CTRLGRP_ADDRESS
|
||||
#define BASE_TRK_MGR (0x000D0000)
|
||||
|
||||
/* Register file addresses. */
|
||||
#define REG_FILE_SIGNATURE (BASE_REG_FILE + 0x0000)
|
||||
#define REG_FILE_DEBUG_DATA_ADDR (BASE_REG_FILE + 0x0004)
|
||||
#define REG_FILE_CUR_STAGE (BASE_REG_FILE + 0x0008)
|
||||
#define REG_FILE_FOM (BASE_REG_FILE + 0x000C)
|
||||
#define REG_FILE_FAILING_STAGE (BASE_REG_FILE + 0x0010)
|
||||
#define REG_FILE_DEBUG1 (BASE_REG_FILE + 0x0014)
|
||||
#define REG_FILE_DEBUG2 (BASE_REG_FILE + 0x0018)
|
||||
|
||||
#define REG_FILE_DTAPS_PER_PTAP (BASE_REG_FILE + 0x001C)
|
||||
#define REG_FILE_TRK_SAMPLE_COUNT (BASE_REG_FILE + 0x0020)
|
||||
#define REG_FILE_TRK_LONGIDLE (BASE_REG_FILE + 0x0024)
|
||||
#define REG_FILE_DELAYS (BASE_REG_FILE + 0x0028)
|
||||
#define REG_FILE_TRK_RW_MGR_ADDR (BASE_REG_FILE + 0x002C)
|
||||
#define REG_FILE_TRK_READ_DQS_WIDTH (BASE_REG_FILE + 0x0030)
|
||||
#define REG_FILE_TRK_RFSH (BASE_REG_FILE + 0x0034)
|
||||
|
||||
/* PHY manager configuration registers. */
|
||||
|
||||
#define PHY_MGR_PHY_RLAT (BASE_PHY_MGR + 0x40 + 0x00)
|
||||
#define PHY_MGR_RESET_MEM_STBL (BASE_PHY_MGR + 0x40 + 0x04)
|
||||
#define PHY_MGR_MUX_SEL (BASE_PHY_MGR + 0x40 + 0x08)
|
||||
#define PHY_MGR_CAL_STATUS (BASE_PHY_MGR + 0x40 + 0x0c)
|
||||
#define PHY_MGR_CAL_DEBUG_INFO (BASE_PHY_MGR + 0x40 + 0x10)
|
||||
#define PHY_MGR_VFIFO_RD_EN_OVRD (BASE_PHY_MGR + 0x40 + 0x14)
|
||||
#if CALIBRATE_BIT_SLIPS
|
||||
#define PHY_MGR_FR_SHIFT (BASE_PHY_MGR + 0x40 + 0x20)
|
||||
#if MULTIPLE_AFI_WLAT
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x20 + 4 * \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
|
||||
#else
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
|
||||
#endif
|
||||
#else
|
||||
#define PHY_MGR_AFI_WLAT (BASE_PHY_MGR + 0x40 + 0x18)
|
||||
#endif
|
||||
#define PHY_MGR_AFI_RLAT (BASE_PHY_MGR + 0x40 + 0x1c)
|
||||
|
||||
#define PHY_MGR_CAL_RESET (0)
|
||||
#define PHY_MGR_CAL_SUCCESS (1)
|
||||
#define PHY_MGR_CAL_FAIL (2)
|
||||
|
||||
/* PHY manager command addresses. */
|
||||
|
||||
#define PHY_MGR_CMD_INC_VFIFO_FR (BASE_PHY_MGR + 0x0000)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_HR (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_HARD_PHY (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_CMD_FIFO_RESET (BASE_PHY_MGR + 0x0008)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_FR_HR (BASE_PHY_MGR + 0x000C)
|
||||
#define PHY_MGR_CMD_INC_VFIFO_QR (BASE_PHY_MGR + 0x0010)
|
||||
|
||||
/* PHY manager parameters. */
|
||||
|
||||
#define PHY_MGR_MAX_RLAT_WIDTH (BASE_PHY_MGR + 0x0000)
|
||||
#define PHY_MGR_MAX_AFI_WLAT_WIDTH (BASE_PHY_MGR + 0x0004)
|
||||
#define PHY_MGR_MAX_AFI_RLAT_WIDTH (BASE_PHY_MGR + 0x0008)
|
||||
#define PHY_MGR_CALIB_SKIP_STEPS (BASE_PHY_MGR + 0x000c)
|
||||
#define PHY_MGR_CALIB_VFIFO_OFFSET (BASE_PHY_MGR + 0x0010)
|
||||
#define PHY_MGR_CALIB_LFIFO_OFFSET (BASE_PHY_MGR + 0x0014)
|
||||
#define PHY_MGR_RDIMM (BASE_PHY_MGR + 0x0018)
|
||||
#define PHY_MGR_MEM_T_WL (BASE_PHY_MGR + 0x001c)
|
||||
#define PHY_MGR_MEM_T_RL (BASE_PHY_MGR + 0x0020)
|
||||
|
||||
/* Data Manager */
|
||||
#define DATA_MGR_DRAM_CFG (BASE_DATA_MGR + 0x0000)
|
||||
#define DATA_MGR_MEM_T_WL (BASE_DATA_MGR + 0x0004)
|
||||
#define DATA_MGR_MEM_T_ADD (BASE_DATA_MGR + 0x0008)
|
||||
#define DATA_MGR_MEM_T_RL (BASE_DATA_MGR + 0x000C)
|
||||
#define DATA_MGR_MEM_T_RFC (BASE_DATA_MGR + 0x0010)
|
||||
#define DATA_MGR_MEM_T_REFI (BASE_DATA_MGR + 0x0014)
|
||||
#define DATA_MGR_MEM_T_WR (BASE_DATA_MGR + 0x0018)
|
||||
#define DATA_MGR_MEM_T_MRD (BASE_DATA_MGR + 0x001C)
|
||||
#define DATA_MGR_COL_WIDTH (BASE_DATA_MGR + 0x0020)
|
||||
#define DATA_MGR_ROW_WIDTH (BASE_DATA_MGR + 0x0024)
|
||||
#define DATA_MGR_BANK_WIDTH (BASE_DATA_MGR + 0x0028)
|
||||
#define DATA_MGR_CS_WIDTH (BASE_DATA_MGR + 0x002C)
|
||||
#define DATA_MGR_ITF_WIDTH (BASE_DATA_MGR + 0x0030)
|
||||
#define DATA_MGR_DVC_WIDTH (BASE_DATA_MGR + 0x0034)
|
||||
|
||||
#define MEM_T_WL_ADD DATA_MGR_MEM_T_WL
|
||||
#define MEM_T_RL_ADD DATA_MGR_MEM_T_RL
|
||||
|
||||
#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
|
||||
#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
|
||||
#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
|
||||
#define CALIB_SKIP_VFIFO (1 << 3)
|
||||
#define CALIB_SKIP_LFIFO (1 << 4)
|
||||
#define CALIB_SKIP_WLEVEL (1 << 5)
|
||||
#define CALIB_SKIP_WRITES (1 << 6)
|
||||
#define CALIB_SKIP_FULL_TEST (1 << 7)
|
||||
#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
|
||||
CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
|
||||
CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
|
||||
#define CALIB_IN_RTL_SIM (1 << 8)
|
||||
|
||||
/* Scan chain manager command addresses */
|
||||
|
||||
#define WRITE_SCC_DQS_IN_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_DQS_EN_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2, (delay) \
|
||||
+ IO_DQS_EN_DELAY_OFFSET)
|
||||
#define WRITE_SCC_DQS_EN_PHASE(group, phase) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_DQDQS_OUT_PHASE(group, phase) \
|
||||
IOWR_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2, phase)
|
||||
#define WRITE_SCC_OCT_OUT1_DELAY(group, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, (group) << 2, delay)
|
||||
#define WRITE_SCC_OCT_OUT2_DELAY(group, delay)
|
||||
#define WRITE_SCC_DQS_BYPASS(group, bypass)
|
||||
|
||||
#define WRITE_SCC_DQ_OUT1_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_OUT2_DELAY(pin, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_IN_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQ_BYPASS(pin, bypass)
|
||||
|
||||
#define WRITE_SCC_RFIFO_MODE(pin, mode)
|
||||
|
||||
#define WRITE_SCC_HHP_EXTRAS(value) \
|
||||
IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_EXTRAS_OFFSET, value)
|
||||
#define WRITE_SCC_HHP_DQSE_MAP(value) \
|
||||
IOWR_32DIRECT(SCC_MGR_HHP_GLOBALS, SCC_MGR_HHP_DQSE_MAP_OFFSET, value)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_OUT1_DELAY(delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_OUT2_DELAY(delay)
|
||||
|
||||
#define WRITE_SCC_DQS_IO_IN_DELAY(delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_OUT1_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_OUT2_DELAY(pin, delay)
|
||||
|
||||
#define WRITE_SCC_DM_IO_IN_DELAY(pin, delay) \
|
||||
IOWR_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2, delay)
|
||||
|
||||
#define WRITE_SCC_DM_BYPASS(pin, bypass)
|
||||
|
||||
#define READ_SCC_DQS_IN_DELAY(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQS_IN_DELAY, (group) << 2)
|
||||
#define READ_SCC_DQS_EN_DELAY(group) \
|
||||
(IORD_32DIRECT(SCC_MGR_DQS_EN_DELAY, (group) << 2) \
|
||||
- IO_DQS_EN_DELAY_OFFSET)
|
||||
#define READ_SCC_DQS_EN_PHASE(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQS_EN_PHASE, (group) << 2)
|
||||
#define READ_SCC_DQDQS_OUT_PHASE(group) \
|
||||
IORD_32DIRECT(SCC_MGR_DQDQS_OUT_PHASE, (group) << 2)
|
||||
#define READ_SCC_OCT_OUT1_DELAY(group) \
|
||||
IORD_32DIRECT(SCC_MGR_OCT_OUT1_DELAY, \
|
||||
(group * RW_MGR_MEM_IF_READ_DQS_WIDTH / \
|
||||
RW_MGR_MEM_IF_WRITE_DQS_WIDTH) << 2)
|
||||
#define READ_SCC_OCT_OUT2_DELAY(group) 0
|
||||
#define READ_SCC_DQS_BYPASS(group) 0
|
||||
#define READ_SCC_DQS_BYPASS(group) 0
|
||||
|
||||
#define READ_SCC_DQ_OUT1_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_OUT2_DELAY(pin) 0
|
||||
#define READ_SCC_DQ_IN_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, (pin) << 2)
|
||||
#define READ_SCC_DQ_BYPASS(pin) 0
|
||||
#define READ_SCC_RFIFO_MODE(pin) 0
|
||||
|
||||
#define READ_SCC_DQS_IO_OUT1_DELAY() \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
#define READ_SCC_DQS_IO_OUT2_DELAY() 0
|
||||
#define READ_SCC_DQS_IO_IN_DELAY() \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS) << 2)
|
||||
|
||||
#define READ_SCC_DM_IO_OUT1_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_OUT1_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_IO_OUT2_DELAY(pin) 0
|
||||
#define READ_SCC_DM_IO_IN_DELAY(pin) \
|
||||
IORD_32DIRECT(SCC_MGR_IO_IN_DELAY, \
|
||||
(RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + pin) << 2)
|
||||
#define READ_SCC_DM_BYPASS(pin) 0
|
||||
|
||||
|
||||
#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
|
||||
#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
|
||||
#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
|
||||
#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
|
||||
#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
|
||||
#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
|
||||
#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
|
||||
#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
|
||||
|
||||
|
||||
/* HHP-HPS-specific versions of some commands */
|
||||
#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
|
||||
#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
|
||||
#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
|
||||
#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
|
||||
|
||||
/* HHP-HPS-specific values */
|
||||
#define SCC_MGR_HHP_EXTRAS_OFFSET 0
|
||||
#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
|
||||
|
||||
#define SCC_MGR_DQS_ENA (BASE_SCC_MGR + 0x0E00)
|
||||
#define SCC_MGR_DQS_IO_ENA (BASE_SCC_MGR + 0x0E04)
|
||||
#define SCC_MGR_DQ_ENA (BASE_SCC_MGR + 0x0E08)
|
||||
#define SCC_MGR_DM_ENA (BASE_SCC_MGR + 0x0E0C)
|
||||
#define SCC_MGR_UPD (BASE_SCC_MGR + 0x0E20)
|
||||
#define SCC_MGR_ACTIVE_RANK (BASE_SCC_MGR + 0x0E40)
|
||||
#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
|
||||
|
||||
/* PHY Debug mode flag constants */
|
||||
#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
|
||||
#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
|
||||
#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
|
||||
#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
|
||||
#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
|
||||
#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
|
||||
|
||||
/* Bitfield type changes depending on protocol */
|
||||
typedef uint32_t t_btfld;
|
||||
|
||||
#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
|
||||
#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
|
||||
|
||||
/* parameter variable holder */
|
||||
|
||||
typedef struct param_type {
|
||||
t_btfld read_correct_mask;
|
||||
t_btfld read_correct_mask_vg;
|
||||
t_btfld write_correct_mask;
|
||||
t_btfld write_correct_mask_vg;
|
||||
|
||||
/* set a particular entry to 1 if we need to skip a particular group */
|
||||
} param_t;
|
||||
|
||||
/* global variable holder */
|
||||
|
||||
typedef struct gbl_type {
|
||||
|
||||
uint32_t phy_debug_mode_flags;
|
||||
|
||||
/* current read latency */
|
||||
|
||||
uint32_t curr_read_lat;
|
||||
|
||||
/* current write latency */
|
||||
|
||||
uint32_t curr_write_lat;
|
||||
|
||||
/* error code */
|
||||
|
||||
uint32_t error_substage;
|
||||
uint32_t error_stage;
|
||||
uint32_t error_group;
|
||||
|
||||
/* figure-of-merit in, figure-of-merit out */
|
||||
|
||||
uint32_t fom_in;
|
||||
uint32_t fom_out;
|
||||
|
||||
/*USER Number of RW Mgr NOP cycles between
|
||||
write command and write data */
|
||||
#if MULTIPLE_AFI_WLAT
|
||||
uint32_t rw_wl_nop_cycles_per_group[RW_MGR_MEM_IF_WRITE_DQS_WIDTH];
|
||||
#endif
|
||||
uint32_t rw_wl_nop_cycles;
|
||||
} gbl_t;
|
||||
#endif
|
|
@ -0,0 +1,18 @@
|
|||
#ifndef __MACH_SOCFPGA_REGS_H
|
||||
#define __MACH_SOCFPGA_REGS_H
|
||||
|
||||
#define CYCLONE5_SDMMC_ADDRESS 0xff704000
|
||||
#define CYCLONE5_GPIO0_BASE 0xff708000
|
||||
#define CYCLONE5_GPIO1_BASE 0xff709000
|
||||
#define CYCLONE5_GPIO2_BASE 0xff70A000
|
||||
#define CYCLONE5_L3REGS_ADDRESS 0xff800000
|
||||
#define CYCLONE5_UART0_ADDRESS 0xffc02000
|
||||
#define CYCLONE5_UART1_ADDRESS 0xffc03000
|
||||
#define CYCLONE5_SDR_ADDRESS 0xffc20000
|
||||
#define CYCLONE5_CLKMGR_ADDRESS 0xffd04000
|
||||
#define CYCLONE5_RSTMGR_ADDRESS 0xffd05000
|
||||
#define CYCLONE5_SYSMGR_ADDRESS 0xffd08000
|
||||
#define CYCLONE5_SCANMGR_ADDRESS 0xfff02000
|
||||
#define CYCLONE5_SMP_TWD_ADDRESS 0xfffec600
|
||||
|
||||
#endif /* __MACH_SOCFPGA_REGS_H */
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_MANAGER_H_
|
||||
#define _SYSTEM_MANAGER_H_
|
||||
|
||||
void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num);
|
||||
|
||||
/* address */
|
||||
#define CONFIG_SYSMGR_ROMCODEGRP_CTRL (CYCLONE5_SYSMGR_ADDRESS + 0xc0)
|
||||
|
||||
/* FPGA interface group */
|
||||
#define SYSMGR_FPGAINTF_MODULE (CYCLONE5_SYSMGR_ADDRESS + 0x28)
|
||||
/* EMAC interface selection */
|
||||
#define CONFIG_SYSMGR_EMAC_CTRL (CYCLONE5_SYSMGR_ADDRESS + 0x60)
|
||||
|
||||
#define ISWGRP_HANDOFF_AXIBRIDGE SYSMGR_ISWGRP_HANDOFF0
|
||||
#define ISWGRP_HANDOFF_L3REMAP SYSMGR_ISWGRP_HANDOFF1
|
||||
#define ISWGRP_HANDOFF_FPGAINTF SYSMGR_ISWGRP_HANDOFF2
|
||||
#define ISWGRP_HANDOFF_FPGA2SDR SYSMGR_ISWGRP_HANDOFF3
|
||||
|
||||
/* pin mux */
|
||||
#define SYSMGR_PINMUXGRP (CYCLONE5_SYSMGR_ADDRESS + 0x400)
|
||||
#define SYSMGR_PINMUXGRP_NANDUSEFPGA (SYSMGR_PINMUXGRP + 0x2F0)
|
||||
#define SYSMGR_PINMUXGRP_EMAC1USEFPGA (SYSMGR_PINMUXGRP + 0x2F8)
|
||||
#define SYSMGR_PINMUXGRP_SDMMCUSEFPGA (SYSMGR_PINMUXGRP + 0x308)
|
||||
#define SYSMGR_PINMUXGRP_EMAC0USEFPGA (SYSMGR_PINMUXGRP + 0x314)
|
||||
#define SYSMGR_PINMUXGRP_SPIM1USEFPGA (SYSMGR_PINMUXGRP + 0x330)
|
||||
#define SYSMGR_PINMUXGRP_SPIM0USEFPGA (SYSMGR_PINMUXGRP + 0x338)
|
||||
|
||||
/* bit fields */
|
||||
#define CONFIG_SYSMGR_PINMUXGRP_OFFSET (0x400)
|
||||
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1<<0)
|
||||
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1<<1)
|
||||
#define SYSMGR_ECC_OCRAM_EN (1<<0)
|
||||
#define SYSMGR_ECC_OCRAM_SERR (1<<3)
|
||||
#define SYSMGR_ECC_OCRAM_DERR (1<<4)
|
||||
#define SYSMGR_FPGAINTF_USEFPGA 0x1
|
||||
#define SYSMGR_FPGAINTF_SPIM0 (1<<0)
|
||||
#define SYSMGR_FPGAINTF_SPIM1 (1<<1)
|
||||
#define SYSMGR_FPGAINTF_EMAC0 (1<<2)
|
||||
#define SYSMGR_FPGAINTF_EMAC1 (1<<3)
|
||||
#define SYSMGR_FPGAINTF_NAND (1<<4)
|
||||
#define SYSMGR_FPGAINTF_SDMMC (1<<5)
|
||||
|
||||
/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum */
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
|
||||
#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
|
||||
|
||||
#endif /* _SYSTEM_MANAGER_H_ */
|
|
@ -0,0 +1,58 @@
|
|||
#include <debug_ll.h>
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <io.h>
|
||||
#include <mach/freeze-controller.h>
|
||||
#include <mach/system-manager.h>
|
||||
#include <mach/clock-manager.h>
|
||||
#include <mach/reset-manager.h>
|
||||
#include <mach/scan-manager.h>
|
||||
#include <mach/generic.h>
|
||||
|
||||
void socfpga_lowlevel_init(struct socfpga_cm_config *cm_config,
|
||||
unsigned long *pinmux, int num_pinmux)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = 0xffffffff;
|
||||
val &= ~(1 << RSTMGR_PERMODRST_L4WD0_LSB);
|
||||
val &= ~(1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
|
||||
writel(val, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
|
||||
/* freeze all IO banks */
|
||||
sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_0);
|
||||
sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_1);
|
||||
sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_2);
|
||||
sys_mgr_frzctrl_freeze_req(FREEZE_CHANNEL_3);
|
||||
|
||||
writel(~0, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_BRG_MOD_RESET_OFS);
|
||||
|
||||
debug("Reconfigure Clock Manager\n");
|
||||
|
||||
/* reconfigure the PLLs */
|
||||
socfpga_cm_basic_init(cm_config);
|
||||
|
||||
debug("Configure IOCSR\n");
|
||||
/* configure the IOCSR through scan chain */
|
||||
scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_0, CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
|
||||
scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_1, CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
|
||||
scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_2, CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
|
||||
scan_mgr_io_scan_chain_prg(IO_SCAN_CHAIN_3, CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
|
||||
|
||||
/* configure the pin muxing through system manager */
|
||||
socfpga_sysmgr_pinmux_init(pinmux, num_pinmux);
|
||||
|
||||
writel(RSTMGR_PERMODRST_L4WD0 | RSTMGR_PERMODRST_L4WD1,
|
||||
CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
|
||||
/* unfreeze / thaw all IO banks */
|
||||
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_0);
|
||||
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_1);
|
||||
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_2);
|
||||
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_3);
|
||||
|
||||
writel(0x18, CYCLONE5_L3REGS_ADDRESS);
|
||||
writel(0x1, 0xfffefc00);
|
||||
|
||||
INIT_LL();
|
||||
}
|
|
@ -0,0 +1,649 @@
|
|||
/* This file is generated by Preloader Generator */
|
||||
|
||||
#include <common.h>
|
||||
#include <mach/scan-manager.h>
|
||||
|
||||
const unsigned long iocsr_scan_chain0_table[((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = {
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0xC0000000,
|
||||
0x0000003F,
|
||||
0x00008000,
|
||||
0x00004824,
|
||||
0x01209000,
|
||||
0x82400000,
|
||||
0x00018004,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00002412,
|
||||
0x00904800,
|
||||
0x41200000,
|
||||
0x80000002,
|
||||
0x00000904,
|
||||
0x00002000,
|
||||
0x00001209,
|
||||
0x00482400,
|
||||
0x20900000,
|
||||
0x40000001,
|
||||
0x00000482,
|
||||
0x00001000,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain1_table[((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = {
|
||||
0x00009048,
|
||||
0x02412000,
|
||||
0x048000C0,
|
||||
0x00000009,
|
||||
0x00002412,
|
||||
0x00008000,
|
||||
0x00004824,
|
||||
0x01209000,
|
||||
0x82400000,
|
||||
0x00000004,
|
||||
0x00001209,
|
||||
0x00004000,
|
||||
0x00002412,
|
||||
0x00904800,
|
||||
0x41200000,
|
||||
0x80000002,
|
||||
0x00000904,
|
||||
0x00002000,
|
||||
0x06001209,
|
||||
0x00482400,
|
||||
0x01FE0000,
|
||||
0xF8000000,
|
||||
0x00000007,
|
||||
0x80001000,
|
||||
0x00000904,
|
||||
0x00241200,
|
||||
0x90480000,
|
||||
0x20003000,
|
||||
0x00000241,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x48240000,
|
||||
0x90000000,
|
||||
0x00000120,
|
||||
0x00000400,
|
||||
0x00000000,
|
||||
0x00090480,
|
||||
0x00000003,
|
||||
0x00000000,
|
||||
0x00000000,
|
||||
0x90000200,
|
||||
0x00600120,
|
||||
0x00000000,
|
||||
0x12090000,
|
||||
0x24000600,
|
||||
0x00000048,
|
||||
0x48000100,
|
||||
0x00300090,
|
||||
0xC0024120,
|
||||
0x09048000,
|
||||
0x12000300,
|
||||
0x000C0024,
|
||||
0x00000080,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain2_table[((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = {
|
||||
0x30009048,
|
||||
0x00000000,
|
||||
0x0FF00000,
|
||||
0x00000000,
|
||||
0x0C002412,
|
||||
0x00008000,
|
||||
0x18004824,
|
||||
0x00000000,
|
||||
0x82400000,
|
||||
0x00018004,
|
||||
0x06001209,
|
||||
0x00004000,
|
||||
0x20002412,
|
||||
0x00904800,
|
||||
0x00000030,
|
||||
0x80000000,
|
||||
0x03000904,
|
||||
0x00002000,
|
||||
0x10001209,
|
||||
0x00482400,
|
||||
0x20900000,
|
||||
0x40010001,
|
||||
0x00000482,
|
||||
0x80001000,
|
||||
0x00000904,
|
||||
0x00000000,
|
||||
0x90480000,
|
||||
0x20008000,
|
||||
0x00C00241,
|
||||
0x00000800,
|
||||
};
|
||||
|
||||
const unsigned long iocsr_scan_chain3_table[((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = {
|
||||
0x0CC20D80,
|
||||
0x0C3000FF,
|
||||
0x0A804001,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000000,
|
||||
0x00000021,
|
||||
0x82000004,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x04010000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x00000001,
|
||||
0x40000002,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x6068030C,
|
||||
0xCF034059,
|
||||
0x1E781A03,
|
||||
0x8030C0D0,
|
||||
0x34059606,
|
||||
0x01A03CF0,
|
||||
0x0C0D0000,
|
||||
0x59606803,
|
||||
0x03CF0340,
|
||||
0xD000001A,
|
||||
0x068030C0,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x0A800001,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x0A800000,
|
||||
0x07900000,
|
||||
0x08020000,
|
||||
0x00100000,
|
||||
0x20430000,
|
||||
0x0C003001,
|
||||
0x00C00481,
|
||||
0x00000FF0,
|
||||
0x4810C000,
|
||||
0x80000C00,
|
||||
0x05400000,
|
||||
0x02480000,
|
||||
0x04000000,
|
||||
0x00080000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x05400000,
|
||||
0x03C80000,
|
||||
0x90218000,
|
||||
0x86001800,
|
||||
0x00600240,
|
||||
0x80090218,
|
||||
0x24086001,
|
||||
0x40000600,
|
||||
0x02A00040,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x02A00000,
|
||||
0x01E40000,
|
||||
0x4810C000,
|
||||
0x43000C00,
|
||||
0x00300120,
|
||||
0xC004810C,
|
||||
0x12043000,
|
||||
0x20000300,
|
||||
0x00040000,
|
||||
0x50670000,
|
||||
0x00000010,
|
||||
0x24590000,
|
||||
0x00001000,
|
||||
0xA0000034,
|
||||
0x0D000001,
|
||||
0x6068030C,
|
||||
0xCF034059,
|
||||
0x1E781A03,
|
||||
0x8030C0D0,
|
||||
0x34059606,
|
||||
0x01A00040,
|
||||
0x0C0D0002,
|
||||
0x59606803,
|
||||
0x03CF0340,
|
||||
0xD01E781A,
|
||||
0x068030C0,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x10040000,
|
||||
0x00200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x15000000,
|
||||
0x0F200000,
|
||||
0x01FE0000,
|
||||
0x18000000,
|
||||
0x01800902,
|
||||
0x00240860,
|
||||
0x007F8006,
|
||||
0x00000000,
|
||||
0x99300001,
|
||||
0x34343400,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x000001C1,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D408,
|
||||
0x00000000,
|
||||
0x2043090C,
|
||||
0x00003001,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC255F80,
|
||||
0xF1C71C71,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0xC9247A06,
|
||||
0xDBCF23D0,
|
||||
0xF71E791E,
|
||||
0x0350E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x01860680,
|
||||
0xD0C9247A,
|
||||
0x1EDBCF23,
|
||||
0x88F71E79,
|
||||
0x000350E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875021,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x00003FC2,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D408,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x00015000,
|
||||
0x0000F200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x86120800,
|
||||
0x00600240,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC255F80,
|
||||
0xF1C71C71,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0xC9247A06,
|
||||
0xDBCF23D0,
|
||||
0xF71E791E,
|
||||
0x0350E388,
|
||||
0x821A02CB,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD0C9247A,
|
||||
0x1EDBCF23,
|
||||
0x88F71E79,
|
||||
0x000350E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875021,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x0002A000,
|
||||
0x0001E400,
|
||||
0x5506A000,
|
||||
0x00E1D408,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00203000,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x00120800,
|
||||
0x00002000,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC255F80,
|
||||
0xF1C71C71,
|
||||
0x14F3690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0xC9247A06,
|
||||
0xDBCF23D0,
|
||||
0xF71E791E,
|
||||
0x0350E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD0C9247A,
|
||||
0x1EDBCF23,
|
||||
0x88F71E79,
|
||||
0x000350E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875021,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0xAA0D4000,
|
||||
0x01C3A810,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0xAA0D4000,
|
||||
0x01C3A808,
|
||||
0x00040100,
|
||||
0x00000800,
|
||||
0x00000000,
|
||||
0x00001208,
|
||||
0x00482000,
|
||||
0x00008000,
|
||||
0x00000000,
|
||||
0x00410482,
|
||||
0x0006A000,
|
||||
0x0001B400,
|
||||
0x00020000,
|
||||
0x00000400,
|
||||
0x00020080,
|
||||
0x00000400,
|
||||
0x5506A000,
|
||||
0x00E1D408,
|
||||
0x00000000,
|
||||
0x0000090C,
|
||||
0x00000010,
|
||||
0x90400000,
|
||||
0x00000000,
|
||||
0x2020C243,
|
||||
0x2A835000,
|
||||
0x0070EA04,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x2A835000,
|
||||
0x0070EA02,
|
||||
0x00010040,
|
||||
0x00000200,
|
||||
0x00000000,
|
||||
0x00000482,
|
||||
0x40120800,
|
||||
0x00000070,
|
||||
0x80000000,
|
||||
0x00104120,
|
||||
0x00000200,
|
||||
0xAC255F80,
|
||||
0xF1C71C71,
|
||||
0x14F1690D,
|
||||
0x1A041414,
|
||||
0x00D00000,
|
||||
0x18864000,
|
||||
0xC9247A06,
|
||||
0xDBCF23D0,
|
||||
0xF71E791E,
|
||||
0x0350E388,
|
||||
0x821A0000,
|
||||
0x0000D000,
|
||||
0x00000680,
|
||||
0xD0C9247A,
|
||||
0x1EDBCF23,
|
||||
0x88F71E79,
|
||||
0x000350E3,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x00080200,
|
||||
0x00001000,
|
||||
0x000A8000,
|
||||
0x00075000,
|
||||
0x541A8000,
|
||||
0x03875021,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x0080C000,
|
||||
0x41000000,
|
||||
0x04000002,
|
||||
0x00820000,
|
||||
0x00489800,
|
||||
0x801A1A1A,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x80000004,
|
||||
0x00000200,
|
||||
0x00000004,
|
||||
0x00040000,
|
||||
0x10000000,
|
||||
0x00000000,
|
||||
0x00000040,
|
||||
0x00010000,
|
||||
0x40002000,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x40000002,
|
||||
0x00000100,
|
||||
0x00000002,
|
||||
0x00020000,
|
||||
0x08000000,
|
||||
0x00000000,
|
||||
0x00000020,
|
||||
0x00008000,
|
||||
0x20001000,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x20000001,
|
||||
0x00000080,
|
||||
0x00000001,
|
||||
0x00010000,
|
||||
0x04000000,
|
||||
0x00FF0000,
|
||||
0x00000000,
|
||||
0x00004000,
|
||||
0x00000800,
|
||||
0xC0000001,
|
||||
0x00041419,
|
||||
0x40000000,
|
||||
0x04000816,
|
||||
0x000D0000,
|
||||
0x00006800,
|
||||
0x00000340,
|
||||
0xD000001A,
|
||||
0x06800000,
|
||||
0x00340000,
|
||||
0x0001A000,
|
||||
0x00000D00,
|
||||
0x40000068,
|
||||
0x1A000003,
|
||||
0x00D00000,
|
||||
0x00068000,
|
||||
0x00003400,
|
||||
0x000001A0,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x00000008,
|
||||
0x00000401,
|
||||
0x80000008,
|
||||
0x0000007F,
|
||||
0x20000000,
|
||||
0x00000000,
|
||||
0xE0000080,
|
||||
0x0000001F,
|
||||
0x00004000,
|
||||
};
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/nic301.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
|
||||
/*
|
||||
* Convert all slave from secure to non secure
|
||||
*/
|
||||
void nic301_slave_ns(void)
|
||||
{
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_LWHPS2FPGAREGS_ADDRESS));
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_HPS2FPGAREGS_ADDRESS));
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_ACP_ADDRESS));
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_ROM_ADDRESS));
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_OCRAM_ADDRESS));
|
||||
writel(0x1, (CYCLONE5_L3REGS_ADDRESS +
|
||||
L3REGS_SECGRP_SDRDATA_ADDRESS));
|
||||
}
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
#include <mach/reset-manager.h>
|
||||
|
||||
/* Disable the watchdog (toggle reset to watchdog) */
|
||||
void watchdog_disable(void)
|
||||
{
|
||||
void __iomem *rm = (void *)CYCLONE5_RSTMGR_ADDRESS;
|
||||
uint32_t val;
|
||||
|
||||
/* assert reset for watchdog */
|
||||
val = readl(rm + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
val |= 1 << RSTMGR_PERMODRST_L4WD0_LSB;
|
||||
writel(val, rm + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
|
||||
/* deassert watchdog from reset (watchdog in not running state) */
|
||||
val = readl(rm + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
val &= ~(1 << RSTMGR_PERMODRST_L4WD0_LSB);
|
||||
writel(val, rm + RESET_MGR_PER_MOD_RESET_OFS);
|
||||
}
|
||||
|
||||
/* Write the reset manager register to cause reset */
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* request a warm reset */
|
||||
writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
|
||||
CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_CTRL_OFS);
|
||||
/*
|
||||
* infinite loop here as watchdog will trigger and reset
|
||||
* the processor
|
||||
*/
|
||||
while (1);
|
||||
}
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/freeze-controller.h>
|
||||
#include <mach/scan-manager.h>
|
||||
|
||||
/*
|
||||
* @fn scan_mgr_io_scan_chain_engine_is_idle
|
||||
*
|
||||
* @brief function to check IO scan chain engine status and wait if the
|
||||
* engine is active. Poll the IO scan chain engine till maximum iteration
|
||||
* reached.
|
||||
*
|
||||
* @param max_iter uint32_t [in] - maximum polling loop to revent infinite loop
|
||||
*/
|
||||
static int scan_mgr_io_scan_chain_engine_is_idle(uint32_t max_iter)
|
||||
{
|
||||
uint32_t scanmgr_status;
|
||||
|
||||
scanmgr_status = readl(SCANMGR_STAT_ADDRESS +
|
||||
CYCLONE5_SCANMGR_ADDRESS);
|
||||
|
||||
/* Poll the engine until the scan engine is inactive */
|
||||
while (SCANMGR_STAT_ACTIVE_GET(scanmgr_status)
|
||||
|| (SCANMGR_STAT_WFIFOCNT_GET(scanmgr_status) > 0)) {
|
||||
|
||||
max_iter--;
|
||||
|
||||
if (max_iter > 0) {
|
||||
scanmgr_status = readl(
|
||||
CYCLONE5_SCANMGR_ADDRESS +
|
||||
SCANMGR_STAT_ADDRESS);
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* scan_mgr_io_scan_chain_prg
|
||||
* Program HPS IO Scan Chain
|
||||
*/
|
||||
int scan_mgr_io_scan_chain_prg(enum io_scan_chain io_scan_chain_id,
|
||||
uint32_t io_scan_chain_len_in_bits,
|
||||
const unsigned long *iocsr_scan_chain)
|
||||
{
|
||||
uint16_t tdi_tdo_header;
|
||||
uint32_t io_program_iter;
|
||||
uint32_t io_scan_chain_data_residual;
|
||||
uint32_t residual;
|
||||
uint32_t i;
|
||||
uint32_t index = 0;
|
||||
uint32_t val;
|
||||
int ret;
|
||||
void __iomem *sysmgr = (void *)CYCLONE5_SYSMGR_ADDRESS;
|
||||
void __iomem *scanmgr = (void *)CYCLONE5_SCANMGR_ADDRESS;
|
||||
|
||||
/* De-assert reinit if the IO scan chain is intended for HIO */
|
||||
if (io_scan_chain_id == IO_SCAN_CHAIN_3) {
|
||||
val = readl(sysmgr + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
val &= ~SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
|
||||
writel(val, sysmgr + SYSMGR_FRZCTRL_HIOCTRL_ADDRESS);
|
||||
} /* if (HIO) */
|
||||
|
||||
/*
|
||||
* Check if the scan chain engine is inactive and the
|
||||
* WFIFO is empty before enabling the IO scan chain
|
||||
*/
|
||||
if (!scan_mgr_io_scan_chain_engine_is_idle(MAX_WAITING_DELAY_IO_SCAN_ENGINE))
|
||||
return -EBUSY;
|
||||
|
||||
/*
|
||||
* Enable IO Scan chain based on scan chain id
|
||||
* Note: only one chain can be enabled at a time
|
||||
*/
|
||||
val = readl(scanmgr + SCANMGR_EN_ADDRESS);
|
||||
val |= 1 << io_scan_chain_id;
|
||||
writel(val, scanmgr + SCANMGR_EN_ADDRESS);
|
||||
|
||||
/*
|
||||
* Calculate number of iteration needed for
|
||||
* full 128-bit (4 x32-bits) bits shifting.
|
||||
* Each TDI_TDO packet can shift in maximum 128-bits
|
||||
*/
|
||||
io_program_iter = io_scan_chain_len_in_bits >> IO_SCAN_CHAIN_128BIT_SHIFT;
|
||||
io_scan_chain_data_residual = io_scan_chain_len_in_bits & IO_SCAN_CHAIN_128BIT_MASK;
|
||||
|
||||
/*
|
||||
* Construct TDI_TDO packet for
|
||||
* 128-bit IO scan chain (2 bytes)
|
||||
*/
|
||||
tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
|
||||
(TDI_TDO_MAX_PAYLOAD << TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
|
||||
|
||||
/* Program IO scan chain in 128-bit iteration */
|
||||
for (i = 0; i < io_program_iter; i++) {
|
||||
|
||||
/* write TDI_TDO packet header to scan manager */
|
||||
writel(tdi_tdo_header, (scanmgr + SCANMGR_FIFODOUBLEBYTE_ADDRESS));
|
||||
|
||||
/* calculate array index */
|
||||
index = i * 4;
|
||||
|
||||
/*
|
||||
* write 4 successive 32-bit IO scan
|
||||
* chain data into WFIFO
|
||||
*/
|
||||
writel(iocsr_scan_chain[index], (scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
writel(iocsr_scan_chain[index + 1], (scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
writel(iocsr_scan_chain[index + 2], (scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
writel(iocsr_scan_chain[index + 3], (scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
|
||||
/*
|
||||
* Check if the scan chain engine has completed the
|
||||
* IO scan chain data shifting
|
||||
*/
|
||||
if (!scan_mgr_io_scan_chain_engine_is_idle(MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
|
||||
ret = -EBUSY;
|
||||
goto out_disable;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate array index for final TDI_TDO packet */
|
||||
index = io_program_iter * 4;
|
||||
|
||||
/* Final TDI_TDO packet if any */
|
||||
if (0 != io_scan_chain_data_residual) {
|
||||
/*
|
||||
* Calculate number of quad bytes FIFO write
|
||||
* needed for the final TDI_TDO packet
|
||||
*/
|
||||
io_program_iter = io_scan_chain_data_residual >> IO_SCAN_CHAIN_32BIT_SHIFT;
|
||||
|
||||
/*
|
||||
* Construct TDI_TDO packet for remaining IO
|
||||
* scan chain (2 bytes)
|
||||
*/
|
||||
tdi_tdo_header = TDI_TDO_HEADER_FIRST_BYTE |
|
||||
((io_scan_chain_data_residual - 1) << TDI_TDO_HEADER_SECOND_BYTE_SHIFT);
|
||||
|
||||
/*
|
||||
* Program the last part of IO scan chain
|
||||
* write TDI_TDO packet header (2 bytes) to
|
||||
* scan manager
|
||||
*/
|
||||
writel(tdi_tdo_header, (scanmgr + SCANMGR_FIFODOUBLEBYTE_ADDRESS));
|
||||
|
||||
for (i = 0; i < io_program_iter; i++) {
|
||||
|
||||
/*
|
||||
* write remaining scan chain data into scan
|
||||
* manager WFIFO with 4 bytes write
|
||||
*/
|
||||
writel(iocsr_scan_chain[index + i],
|
||||
(scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
}
|
||||
|
||||
index += io_program_iter;
|
||||
residual = io_scan_chain_data_residual & IO_SCAN_CHAIN_32BIT_MASK;
|
||||
|
||||
if (IO_SCAN_CHAIN_PAYLOAD_24BIT < residual) {
|
||||
/*
|
||||
* write the last 4B scan chain data
|
||||
* into scan manager WFIFO
|
||||
*/
|
||||
writel(iocsr_scan_chain[index],
|
||||
(scanmgr + SCANMGR_FIFOQUADBYTE_ADDRESS));
|
||||
} else {
|
||||
/*
|
||||
* write the remaining 1 - 3 bytes scan chain
|
||||
* data into scan manager WFIFO byte by byte
|
||||
* to prevent JTAG engine shifting unused data
|
||||
* from the FIFO and mistaken the data as a
|
||||
* valid command (even though unused bits are
|
||||
* set to 0, but just to prevent hardware
|
||||
* glitch)
|
||||
*/
|
||||
for (i = 0; i < residual; i += 8) {
|
||||
writel(((iocsr_scan_chain[index] >> i) & IO_SCAN_CHAIN_BYTE_MASK),
|
||||
(scanmgr + SCANMGR_FIFOSINGLEBYTE_ADDRESS));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Check if the scan chain engine has completed the
|
||||
* IO scan chain data shifting
|
||||
*/
|
||||
if (!scan_mgr_io_scan_chain_engine_is_idle(MAX_WAITING_DELAY_IO_SCAN_ENGINE)) {
|
||||
ret = -EBUSY;
|
||||
goto out_disable;
|
||||
}
|
||||
} /* if (io_scan_chain_data_residual) */
|
||||
|
||||
ret = 0;
|
||||
|
||||
out_disable:
|
||||
/* Disable IO Scan chain when configuration done*/
|
||||
val = readl(scanmgr + SCANMGR_EN_ADDRESS);
|
||||
val &= ~(1 << io_scan_chain_id);
|
||||
writel(val, scanmgr + SCANMGR_EN_ADDRESS);
|
||||
|
||||
return ret;
|
||||
}
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <io.h>
|
||||
#include <mach/system-manager.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
|
||||
void socfpga_sysmgr_pinmux_init(unsigned long *sys_mgr_init_table, int num)
|
||||
{
|
||||
unsigned long offset = CONFIG_SYSMGR_PINMUXGRP_OFFSET;
|
||||
const unsigned long *pval = sys_mgr_init_table;
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
writel(*pval++, CYCLONE5_SYSMGR_ADDRESS + offset);
|
||||
offset += sizeof(uint32_t);
|
||||
}
|
||||
}
|
|
@ -0,0 +1,97 @@
|
|||
#include <platform_data/dw_mmc.h>
|
||||
#include <bootsource.h>
|
||||
#include <bootstrap.h>
|
||||
#include <ns16550.h>
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <init.h>
|
||||
#include <envfs.h>
|
||||
#include <sizes.h>
|
||||
#include <fs.h>
|
||||
#include <io.h>
|
||||
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/stat.h>
|
||||
#include <linux/clk.h>
|
||||
|
||||
#include <mach/system-manager.h>
|
||||
#include <mach/socfpga-regs.h>
|
||||
|
||||
enum socfpga_clks {
|
||||
timer, mmc, uart, clk_max
|
||||
};
|
||||
|
||||
static struct clk *clks[clk_max];
|
||||
|
||||
static struct dw_mmc_platform_data mmc_pdata = {
|
||||
.ciu_div = 3,
|
||||
};
|
||||
|
||||
static void socfpga_mmc_init(void)
|
||||
{
|
||||
clks[mmc] = clk_fixed("mmc", 400000000);
|
||||
clkdev_add_physbase(clks[mmc], CYCLONE5_SDMMC_ADDRESS, NULL);
|
||||
add_generic_device("dw_mmc", 0, NULL, CYCLONE5_SDMMC_ADDRESS, SZ_4K,
|
||||
IORESOURCE_MEM, &mmc_pdata);
|
||||
}
|
||||
|
||||
static struct NS16550_plat uart_pdata = {
|
||||
.clock = 100000000,
|
||||
.shift = 2,
|
||||
};
|
||||
|
||||
static void socfpga_uart_init(void)
|
||||
{
|
||||
clks[uart] = clk_fixed("uart", 100000000);
|
||||
clkdev_add_physbase(clks[uart], CYCLONE5_UART0_ADDRESS, NULL);
|
||||
clkdev_add_physbase(clks[uart], CYCLONE5_UART1_ADDRESS, NULL);
|
||||
add_ns16550_device(0, 0xffc02000, 1024, IORESOURCE_MEM_8BIT,
|
||||
&uart_pdata);
|
||||
}
|
||||
|
||||
static void socfpga_timer_init(void)
|
||||
{
|
||||
clks[timer] = clk_fixed("timer", 200000000);
|
||||
clkdev_add_physbase(clks[timer], CYCLONE5_SMP_TWD_ADDRESS, NULL);
|
||||
add_generic_device("smp_twd", 0, NULL, CYCLONE5_SMP_TWD_ADDRESS, 0x100,
|
||||
IORESOURCE_MEM, NULL);
|
||||
}
|
||||
|
||||
static __noreturn int socfpga_xload(void)
|
||||
{
|
||||
enum bootsource bootsource = bootsource_get();
|
||||
void *buf;
|
||||
|
||||
switch (bootsource) {
|
||||
case BOOTSOURCE_MMC:
|
||||
buf = bootstrap_read_disk("disk0.1", "fat");
|
||||
break;
|
||||
default:
|
||||
pr_err("unknown bootsource %d\n", bootsource);
|
||||
hang();
|
||||
}
|
||||
|
||||
if (!buf) {
|
||||
pr_err("failed to load barebox.bin\n");
|
||||
hang();
|
||||
}
|
||||
|
||||
pr_info("starting bootloader...\n");
|
||||
|
||||
bootstrap_boot(buf, 0);
|
||||
|
||||
hang();
|
||||
}
|
||||
|
||||
static int socfpga_devices_init(void)
|
||||
{
|
||||
barebox_set_model("SoCFPGA");
|
||||
socfpga_timer_init();
|
||||
socfpga_uart_init();
|
||||
socfpga_mmc_init();
|
||||
|
||||
barebox_main = socfpga_xload;
|
||||
|
||||
return 0;
|
||||
}
|
||||
coredevice_initcall(socfpga_devices_init);
|
|
@ -7,6 +7,7 @@
|
|||
*.src
|
||||
*.kwbimg
|
||||
*.kwbuartimg
|
||||
*.socfpgaimg
|
||||
pbl.lds
|
||||
barebox.x
|
||||
barebox.z
|
||||
|
|
|
@ -108,6 +108,7 @@ $(obj)/%.img: $(obj)/$$(FILE_$$(@F))
|
|||
|
||||
include $(srctree)/images/Makefile.imx
|
||||
include $(srctree)/images/Makefile.mvebu
|
||||
include $(srctree)/images/Makefile.socfpga
|
||||
|
||||
targets += $(image-y) pbl.lds barebox.x barebox.z
|
||||
targets += $(patsubst %,%.pblx,$(pblx-y))
|
||||
|
@ -122,5 +123,5 @@ images: $(addprefix $(obj)/, $(image-y)) FORCE
|
|||
@echo "images built:\n" $(patsubst %,%\\n,$(image-y))
|
||||
|
||||
clean-files := *.pbl *.pblb *.pblx *.map start_*.imximg *.img barebox.z start_*.kwbimg \
|
||||
start_*.kwbuartimg
|
||||
start_*.kwbuartimg *.socfpgaimg
|
||||
clean-files += pbl.lds
|
||||
|
|
|
@ -0,0 +1,19 @@
|
|||
#
|
||||
# barebox image generation Makefile for Altera socfpga
|
||||
#
|
||||
|
||||
# %.socfpga - convert into socfpga image
|
||||
# ----------------------------------------------------------------
|
||||
quiet_cmd_socfpga_image = SOCFPGA-IMG $@
|
||||
cmd_socfpga_image = scripts/socfpga_mkimage -b -o $@ $<
|
||||
|
||||
$(obj)/%.socfpgaimg: $(obj)/% FORCE
|
||||
$(call if_changed,socfpga_image)
|
||||
|
||||
# ----------------------- Cyclone5 based boards ---------------------------
|
||||
|
||||
ifdef CONFIG_ARCH_SOCFPGA_XLOAD
|
||||
image-y += $(xload-y)
|
||||
else
|
||||
image-y += $(barebox-y)
|
||||
endif
|
Loading…
Reference in New Issue