eukrea_cpuimx25: update board support
- support NAND external boot - enable only used clocks - LCD fix in /env/bin/init - I2C support - SDCard support - USB Host 1 support - DFU support on OTG port - update defconfig Signed-off-by: Eric Bénard <eric@eukrea.com>
This commit is contained in:
Eric Bénard
parent
9f93d939ef
commit
5eaffc4326
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@ -14,9 +14,11 @@ fi
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if [ -f /env/logo.bmp ]; then
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bmp /env/logo.bmp
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fb0.enable=1
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elif [ -f /env/logo.bmp.lzo ]; then
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unlzo /env/logo.bmp.lzo /logo.bmp
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bmp /logo.bmp
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fb0.enable=1
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fi
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if [ -z $eth0.ethaddr ]; then
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@ -40,6 +40,8 @@
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#include <nand.h>
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#include <mach/imx-flash-header.h>
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#include <mach/iomux-mx25.h>
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#include <i2c/i2c.h>
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#include <usb/fsl_usb2.h>
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extern unsigned long _stext;
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extern void exception_vectors(void);
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@ -151,6 +153,70 @@ static struct device_d imxfb_dev = {
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.platform_data = &eukrea_cpuimx25_fb_data,
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};
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static struct device_d i2c_dev = {
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.id = -1,
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.name = "i2c-imx",
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.map_base = IMX_I2C1_BASE,
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};
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static struct device_d esdhc_dev = {
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.name = "imx-esdhc",
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.map_base = 0x53fb4000,
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};
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#ifdef CONFIG_USB
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#define MX35_H1_SIC_SHIFT 21
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#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
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#define MX35_H1_PM_BIT (1 << 8)
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#define MX35_H1_IPPUE_UP_BIT (1 << 7)
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#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX35_H1_TLL_BIT (1 << 5)
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#define MX35_H1_USBTE_BIT (1 << 4)
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#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0)
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static void imx25_usb_init(void)
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{
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unsigned int tmp;
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/* Host 1 */
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tmp = readl(IMX_OTG_BASE + 0x600);
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tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
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MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
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tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT;
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tmp |= MX35_H1_USBTE_BIT;
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tmp |= MX35_H1_IPPUE_DOWN_BIT;
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writel(tmp, IMX_OTG_BASE + 0x600);
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tmp = readl(IMX_OTG_BASE + 0x584);
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tmp |= 3 << 30;
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writel(tmp, IMX_OTG_BASE + 0x584);
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/* Set to Host mode */
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tmp = readl(IMX_OTG_BASE + 0x5a8);
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writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8);
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}
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static struct device_d usbh2_dev = {
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.id = -1,
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.name = "ehci",
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.map_base = IMX_OTG_BASE + 0x400,
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.size = 0x200,
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};
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#endif
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static struct fsl_usb2_platform_data usb_pdata = {
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.operating_mode = FSL_USB2_DR_DEVICE,
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.phy_mode = FSL_USB2_PHY_UTMI,
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};
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static struct device_d usbotg_dev = {
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.name = "fsl-udc",
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.map_base = IMX_OTG_BASE,
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.size = 0x200,
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.platform_data = &usb_pdata,
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};
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#ifdef CONFIG_MMU
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static void eukrea_cpuimx25_mmu_init(void)
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{
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@ -209,6 +275,16 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
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MX25_PAD_HSYNC__LCDC_HSYN,
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/* BACKLIGHT CONTROL */
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MX25_PAD_PWM__GPIO26,
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/* I2C */
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MX25_PAD_I2C1_CLK__SCL,
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MX25_PAD_I2C1_DAT__SDA,
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/* SDCard */
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MX25_PAD_SD1_CLK__CLK,
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MX25_PAD_SD1_CMD__CMD,
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MX25_PAD_SD1_DATA0__DAT0,
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MX25_PAD_SD1_DATA1__DAT1,
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MX25_PAD_SD1_DATA2__DAT2,
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MX25_PAD_SD1_DATA3__DAT3,
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};
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static int eukrea_cpuimx25_devices_init(void)
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@ -217,6 +293,7 @@ static int eukrea_cpuimx25_devices_init(void)
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mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
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ARRAY_SIZE(eukrea_cpuimx25_pads));
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register_device(&fec_dev);
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nand_info.width = 1;
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@ -238,6 +315,15 @@ static int eukrea_cpuimx25_devices_init(void)
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register_device(&imxfb_dev);
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register_device(&i2c_dev);
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register_device(&esdhc_dev);
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#ifdef CONFIG_USB
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imx25_usb_init();
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register_device(&usbh2_dev);
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#endif
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register_device(&usbotg_dev);
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armlinux_add_dram(&sdram0_dev);
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armlinux_set_bootparams((void *)0x80000100);
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armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX25);
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@ -256,7 +342,6 @@ static struct device_d eukrea_cpuimx25_serial_device = {
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static int eukrea_cpuimx25_console_init(void)
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{
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writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3);
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register_device(&eukrea_cpuimx25_serial_device);
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return 0;
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}
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@ -270,10 +355,17 @@ void __bare_init nand_boot(void)
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}
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#endif
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static int eukrea_cpuimx25_core_setup(void)
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{
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writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2);
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return 0;
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static int eukrea_cpuimx25_core_init(void) {
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/* enable UART1, FEC, SDHC, USB & I2C clock */
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writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23)
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| (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28),
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IMX_CCM_BASE + CCM_CGCR0);
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writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15)
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| (1 << 13), IMX_CCM_BASE + CCM_CGCR1);
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writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14),
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IMX_CCM_BASE + CCM_CGCR2);
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return 0;
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}
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core_initcall(eukrea_cpuimx25_core_setup);
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core_initcall(eukrea_cpuimx25_core_init);
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@ -26,13 +26,13 @@
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#include <mach/imx-regs.h>
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#include <mach/imx-pll.h>
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#include <mach/esdctl.h>
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#include <asm/cache-l2x0.h>
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#include <asm/io.h>
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#include <mach/imx-nand.h>
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#include <asm/barebox-arm.h>
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#include <asm-generic/memory_layout.h>
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#include <asm/system.h>
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#ifdef CONFIG_NAND_IMX_BOOT
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static void __bare_init __naked insdram(void)
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{
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uint32_t r;
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@ -45,17 +45,32 @@ static void __bare_init __naked insdram(void)
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board_init_lowlevel_return();
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}
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#define MX25_CCM_MCR 0x64
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#define MX25_CCM_CGR0 0x0c
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#define MX25_CCM_CGR1 0x10
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#define MX25_CCM_CGR2 0x14
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#endif
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void __bare_init __naked board_init_lowlevel(void)
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{
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uint32_t r;
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#ifdef CONFIG_NAND_IMX_BOOT
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unsigned int *trg, *src;
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int i;
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#endif
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register uint32_t loops = 0x20000;
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/* restart the MPLL and wait until it's stable */
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writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27),
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IMX_CCM_BASE + CCM_CCTL);
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while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {};
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/* Configure dividers and ARM clock source
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* ARM @ 400 MHz
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* AHB @ 133 MHz
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*/
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writel(0x20034000, IMX_CCM_BASE + CCM_CCTL);
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/* Enable UART1 / FEC / */
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/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0);
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writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1);
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writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/
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/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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@ -102,23 +117,46 @@ void __bare_init __naked board_init_lowlevel(void)
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*/
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writel(0x1, 0xb8003000);
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/* enable all the clocks */
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writel(0x038A81A2, IMX_CCM_BASE + MX25_CCM_CGR0);
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writel(0x24788F00, IMX_CCM_BASE + MX25_CCM_CGR1);
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writel(0x00004438, IMX_CCM_BASE + MX25_CCM_CGR2);
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writel(0x00, IMX_CCM_BASE + MX25_CCM_MCR);
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/* Speed up NAND controller by adjusting the NFC divider */
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r = readl(IMX_CCM_BASE + CCM_PCDR2);
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r &= ~0xf;
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r |= 0x1;
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writel(r, IMX_CCM_BASE + CCM_PCDR2);
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/* Skip SDRAM initialization if we run from RAM */
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r = get_pc();
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if (r > 0x80000000 && r < 0x90000000)
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board_init_lowlevel_return();
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/* Init Mobile DDR */
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writel(0x0000000E, ESDMISC);
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writel(0x00000004, ESDMISC);
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0" (loops));
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writel(0x0029572B, ESDCFG0);
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writel(0x92210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0 + 0x400);
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writel(0xA2210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0);
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writeb(0xda, IMX_SDRAM_CS0);
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writel(0xB2210000, ESDCTL0);
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writeb(0xda, IMX_SDRAM_CS0 + 0x33);
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writeb(0xda, IMX_SDRAM_CS0 + 0x1000000);
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writel(0x82216080, ESDCTL0);
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#ifdef CONFIG_NAND_IMX_BOOT
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/* skip NAND boot if not running from NFC space */
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r = get_pc();
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if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000)
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if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
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board_init_lowlevel_return();
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src = (unsigned int *)IMX_NFC_BASE;
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trg = (unsigned int *)TEXT_BASE;
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/* Move ourselves out of NFC SRAM */
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for (i = 0; i < 0x1000 / sizeof(int); i++)
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for (i = 0; i < 0x800 / sizeof(int); i++)
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*trg++ = *src++;
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/* Jump to SDRAM */
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@ -9,6 +9,7 @@ CONFIG_LONGHELP=y
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CONFIG_GLOB=y
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CONFIG_PROMPT_HUSH_PS2="cpuimx25>"
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CONFIG_HUSH_FANCY_PROMPT=y
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CONFIG_HUSH_GETOPT=y
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CONFIG_CMDLINE_EDITING=y
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CONFIG_AUTO_COMPLETE=y
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CONFIG_PARTITION=y
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@ -23,6 +24,7 @@ CONFIG_CMD_READLINE=y
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CONFIG_CMD_ECHO_E=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_CRC=y
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CONFIG_CMD_CRC_CMP=y
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CONFIG_CMD_MTEST=y
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CONFIG_CMD_FLASH=y
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CONFIG_CMD_BOOTM_ZLIB=y
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@ -35,15 +37,23 @@ CONFIG_CMD_PARTITION=y
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CONFIG_CMD_BMP=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_UNLZO=y
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CONFIG_CMD_I2C=y
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CONFIG_NET=y
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CONFIG_NET_DHCP=y
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CONFIG_NET_PING=y
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CONFIG_NET_TFTP=y
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CONFIG_DRIVER_NET_FEC_IMX=y
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# CONFIG_SPI is not set
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CONFIG_I2C=y
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CONFIG_I2C_IMX=y
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CONFIG_MTD=y
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CONFIG_NAND=y
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CONFIG_NAND_IMX=y
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CONFIG_NAND_IMX_BOOT=y
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CONFIG_USB=y
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CONFIG_USB_EHCI=y
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CONFIG_USB_GADGET=y
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CONFIG_VIDEO=y
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CONFIG_DRIVER_VIDEO_IMX=y
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CONFIG_MCI=y
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CONFIG_MCI_IMX_ESDHC=y
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CONFIG_MCI_IMX_ESDHC_PIO=y
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