tegra: add SDMMC controller driver
Confirmed working on Tegra 2, may need some small adjustments for Tegra 3. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach
Sascha Hauer
parent
3504f23ed8
commit
5f9dea93a1
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@ -108,6 +108,13 @@ config MCI_MMCI
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Enable this entry to add support to read and write SD cards on a
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ARM AMBA PL180.
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config MCI_TEGRA
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bool "Tegra SD/MMC"
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depends on ARCH_TEGRA
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help
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Enable this to support SD and MMC card read/write on a Tegra based
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systems.
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config MCI_SPI
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bool "MMC/SD over SPI"
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select CRC7
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@ -7,6 +7,7 @@ obj-$(CONFIG_MCI_MXS) += mxs.o
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obj-$(CONFIG_MCI_OMAP_HSMMC) += omap_hsmmc.o
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obj-$(CONFIG_MCI_PXA) += pxamci.o
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obj-$(CONFIG_MCI_S3C) += s3c.o
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obj-$(CONFIG_MCI_TEGRA) += tegra-sdmmc.o
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obj-$(CONFIG_MCI_SPI) += mci_spi.o
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obj-$(CONFIG_MCI_DW) += dw_mmc.o
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obj-$(CONFIG_MCI_MMCI) += mmci.o
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@ -0,0 +1,464 @@
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/*
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* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
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*
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* Partly based on code (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <asm/mmu.h>
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#include <common.h>
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#include <clock.h>
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#include <driver.h>
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#include <gpio.h>
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#include <init.h>
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#include <io.h>
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#include <malloc.h>
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#include <mci.h>
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#include <of_gpio.h>
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#include <linux/clk.h>
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#include "sdhci.h"
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#define TEGRA_SDMMC_PRESENT_STATE 0x024
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#define TEGRA_SDMMC_PRESENT_STATE_CMD_INHIBIT_CMD (1 << 0)
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#define TEGRA_SDMMC_PRESENT_STATE_CMD_INHIBIT_DAT (1 << 1)
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#define TEGRA_SDMMC_PWR_CNTL 0x028
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#define TEGRA_SDMMC_PWR_CNTL_SD_BUS (1 << 8)
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#define TEGRA_SDMMC_PWR_CNTL_33_V (7 << 9)
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#define TEGRA_SDMMC_CLK_CNTL 0x02c
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#define TEGRA_SDMMC_CLK_CNTL_SW_RESET_FOR_ALL (1 << 24)
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#define TEGRA_SDMMC_CLK_CNTL_SD_CLOCK_EN (1 << 2)
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#define TEGRA_SDMMC_CLK_INTERNAL_CLOCK_STABLE (1 << 1)
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#define TEGRA_SDMMC_CLK_CNTL_INTERNAL_CLOCK_EN (1 << 0)
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#define TEGRA_SDMMC_INTERRUPT_STATUS_ERR_INTERRUPT (1 << 15)
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#define TEGRA_SDMMC_INTERRUPT_STATUS_CMD_TIMEOUT (1 << 16)
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#define TEGRA_SDMMC_INT_STAT_EN 0x034
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#define TEGRA_SDMMC_INT_STAT_EN_CMD_COMPLETE (1 << 0)
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#define TEGRA_SDMMC_INT_STAT_EN_XFER_COMPLETE (1 << 1)
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#define TEGRA_SDMMC_INT_STAT_EN_DMA_INTERRUPT (1 << 3)
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#define TEGRA_SDMMC_INT_STAT_EN_BUFFER_WRITE_READY (1 << 4)
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#define TEGRA_SDMMC_INT_STAT_EN_BUFFER_READ_READY (1 << 5)
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#define TEGRA_SDMMC_INT_SIG_EN 0x038
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#define TEGRA_SDMMC_INT_SIG_EN_XFER_COMPLETE (1 << 1)
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struct tegra_sdmmc_host {
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struct mci_host mci;
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void __iomem *regs;
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struct clk *clk;
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int gpio_cd, gpio_pwr;
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};
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#define to_tegra_sdmmc_host(mci) container_of(mci, struct tegra_sdmmc_host, mci)
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static int tegra_sdmmc_wait_inhibit(struct tegra_sdmmc_host *host,
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struct mci_cmd *cmd, struct mci_data *data,
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unsigned int timeout)
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{
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u32 val = TEGRA_SDMMC_PRESENT_STATE_CMD_INHIBIT_CMD;
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/*
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* We shouldn't wait for data inhibit for stop commands, even
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* though they might use busy signaling
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*/
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if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
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val |= TEGRA_SDMMC_PRESENT_STATE_CMD_INHIBIT_DAT;
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wait_on_timeout(timeout * MSECOND,
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!(readl(host->regs + TEGRA_SDMMC_PRESENT_STATE) & val));
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return 0;
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}
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static int tegra_sdmmc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
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struct mci_data *data)
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{
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struct tegra_sdmmc_host *host = to_tegra_sdmmc_host(mci);
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u32 val = 0;
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int ret;
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ret = tegra_sdmmc_wait_inhibit(host, cmd, data, 10);
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if (ret < 0)
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return ret;
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/* Set up for a data transfer if we have one */
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if (data) {
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if (data->flags & MMC_DATA_WRITE) {
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dma_flush_range((unsigned long)data->src,
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(unsigned long)(data->src +
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data->blocks * 512));
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writel((u32)data->src, host->regs + SDHCI_DMA_ADDRESS);
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} else {
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dma_clean_range((unsigned long)data->src,
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(unsigned long)(data->src +
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data->blocks * 512));
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writel((u32)data->dest, host->regs + SDHCI_DMA_ADDRESS);
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}
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writel((7 << 12) | data->blocks << 16 | data->blocksize,
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host->regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT);
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}
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writel(cmd->cmdarg, host->regs + SDHCI_ARGUMENT);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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if (data) {
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if (data->blocks > 1)
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val |= TRANSFER_MODE_MSBSEL;
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if (data->flags & MMC_DATA_READ)
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val |= TRANSFER_MODE_DTDSEL;
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val |= TRANSFER_MODE_DMAEN | TRANSFER_MODE_BCEN;
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}
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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val |= COMMAND_RSPTYP_NONE;
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else if (cmd->resp_type & MMC_RSP_136)
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val |= COMMAND_RSPTYP_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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val |= COMMAND_RSPTYP_48_BUSY;
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else
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val |= COMMAND_RSPTYP_48;
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if (cmd->resp_type & MMC_RSP_CRC)
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val |= COMMAND_CCCEN;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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val |= COMMAND_CICEN;
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if (data)
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val |= COMMAND_DPSEL;
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writel(COMMAND_CMD(cmd->cmdidx) | val,
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host->regs + SDHCI_TRANSFER_MODE__COMMAND);
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ret = wait_on_timeout(100 * MSECOND,
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(val = readl(host->regs + SDHCI_INT_STATUS))
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& IRQSTAT_CC);
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if (ret) {
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writel(val, host->regs + SDHCI_INT_STATUS);
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return ret;
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}
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if ((val & IRQSTAT_CC) && !data)
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writel(val, host->regs + SDHCI_INT_STATUS);
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if (val & TEGRA_SDMMC_INTERRUPT_STATUS_CMD_TIMEOUT) {
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/* Timeout Error */
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dev_dbg(mci->hw_dev, "timeout: %08x cmd %d\n", val, cmd->cmdidx);
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writel(val, host->regs + SDHCI_INT_STATUS);
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return -ETIMEDOUT;
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} else if (val & TEGRA_SDMMC_INTERRUPT_STATUS_ERR_INTERRUPT) {
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/* Error Interrupt */
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dev_dbg(mci->hw_dev, "error: %08x cmd %d\n", val, cmd->cmdidx);
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writel(val, host->regs + SDHCI_INT_STATUS);
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return -EIO;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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u32 cmdrsp[4];
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cmdrsp[3] = readl(host->regs + SDHCI_RESPONSE_3);
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cmdrsp[2] = readl(host->regs + SDHCI_RESPONSE_2);
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cmdrsp[1] = readl(host->regs + SDHCI_RESPONSE_1);
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cmdrsp[0] = readl(host->regs + SDHCI_RESPONSE_0);
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cmd->response[0] = (cmdrsp[3] << 8) | (cmdrsp[2] >> 24);
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cmd->response[1] = (cmdrsp[2] << 8) | (cmdrsp[1] >> 24);
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cmd->response[2] = (cmdrsp[1] << 8) | (cmdrsp[0] >> 24);
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cmd->response[3] = (cmdrsp[0] << 8);
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} else if (cmd->resp_type & MMC_RSP_BUSY) {
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ret = wait_on_timeout(100 * MSECOND,
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readl(host->regs + TEGRA_SDMMC_PRESENT_STATE)
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& (1 << 20));
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if (ret) {
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dev_err(mci->hw_dev, "card is still busy\n");
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writel(val, host->regs + SDHCI_INT_STATUS);
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return ret;
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}
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cmd->response[0] = readl(host->regs + SDHCI_RESPONSE_0);
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} else {
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cmd->response[0] = readl(host->regs + SDHCI_RESPONSE_0);
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}
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}
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if (data) {
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uint64_t start = get_time_ns();
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while (1) {
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val = readl(host->regs + SDHCI_INT_STATUS);
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if (val & TEGRA_SDMMC_INTERRUPT_STATUS_ERR_INTERRUPT) {
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/* Error Interrupt */
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writel(val, host->regs + SDHCI_INT_STATUS);
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dev_err(mci->hw_dev,
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"error during transfer: 0x%08x\n", val);
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return -EIO;
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} else if (val & IRQSTAT_DINT) {
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/*
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* DMA Interrupt, restart the transfer where
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* it was interrupted.
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*/
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u32 address = readl(host->regs +
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SDHCI_DMA_ADDRESS);
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writel(IRQSTAT_DINT,
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host->regs + SDHCI_INT_STATUS);
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writel(address, host->regs + SDHCI_DMA_ADDRESS);
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} else if (val & IRQSTAT_TC) {
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/* Transfer Complete */;
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break;
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} else if (is_timeout(start, 2 * SECOND)) {
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writel(val, host->regs + SDHCI_INT_STATUS);
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dev_err(mci->hw_dev, "MMC Timeout\n"
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" Interrupt status 0x%08x\n"
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" Interrupt status enable 0x%08x\n"
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" Interrupt signal enable 0x%08x\n"
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" Present status 0x%08x\n",
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val,
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readl(host->regs + SDHCI_INT_ENABLE),
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readl(host->regs + SDHCI_SIGNAL_ENABLE),
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readl(host->regs + SDHCI_PRESENT_STATE));
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return -ETIMEDOUT;
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}
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}
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writel(val, host->regs + SDHCI_INT_STATUS);
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if (data->flags & MMC_DATA_READ) {
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dma_inv_range((unsigned long)data->dest,
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(unsigned long)(data->dest +
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data->blocks * 512));
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}
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}
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return 0;
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}
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static void tegra_sdmmc_set_clock(struct tegra_sdmmc_host *host, u32 clock)
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{
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u32 prediv = 1, adjusted_clock = clock, val;
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while (adjusted_clock < 3200000) {
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prediv *= 2;
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adjusted_clock = clock * prediv * 2;
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}
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/* clear clock related bits */
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val = readl(host->regs + TEGRA_SDMMC_CLK_CNTL);
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val &= 0xffff0000;
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writel(val, host->regs + TEGRA_SDMMC_CLK_CNTL);
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/* set new frequency */
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val |= prediv << 8;
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val |= TEGRA_SDMMC_CLK_CNTL_INTERNAL_CLOCK_EN;
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writel(val, host->regs + TEGRA_SDMMC_CLK_CNTL);
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clk_set_rate(host->clk, adjusted_clock);
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/* wait for controller to settle */
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wait_on_timeout(10 * MSECOND,
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!(readl(host->regs + TEGRA_SDMMC_CLK_CNTL) &
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TEGRA_SDMMC_CLK_INTERNAL_CLOCK_STABLE));
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/* enable card clock */
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val |= TEGRA_SDMMC_CLK_CNTL_SD_CLOCK_EN;
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writel(val, host->regs + TEGRA_SDMMC_CLK_CNTL);
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}
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static void tegra_sdmmc_set_ios(struct mci_host *mci, struct mci_ios *ios)
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{
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struct tegra_sdmmc_host *host = to_tegra_sdmmc_host(mci);
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u32 val;
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/* set clock */
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if (ios->clock)
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tegra_sdmmc_set_clock(host, ios->clock);
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/* set bus width */
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val = readl(host->regs + TEGRA_SDMMC_PWR_CNTL);
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val &= ~(0x21);
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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val |= (1 << 5);
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else if (ios->bus_width == MMC_BUS_WIDTH_4)
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val |= (1 << 1);
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writel(val, host->regs + TEGRA_SDMMC_PWR_CNTL);
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}
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static int tegra_sdmmc_init(struct mci_host *mci, struct device_d *dev)
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{
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struct tegra_sdmmc_host *host = to_tegra_sdmmc_host(mci);
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void __iomem *regs = host->regs;
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u32 val;
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int ret;
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/* reset controller */
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writel(TEGRA_SDMMC_CLK_CNTL_SW_RESET_FOR_ALL,
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regs + TEGRA_SDMMC_CLK_CNTL);
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ret = wait_on_timeout(100 * MSECOND,
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!(readl(regs + TEGRA_SDMMC_CLK_CNTL) &
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TEGRA_SDMMC_CLK_CNTL_SW_RESET_FOR_ALL));
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if (ret) {
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dev_err(dev, "timeout while reset\n");
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return ret;
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}
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/* set power */
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val = readl(regs + TEGRA_SDMMC_PWR_CNTL);
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val &= ~(0xff << 8);
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val |= TEGRA_SDMMC_PWR_CNTL_33_V | TEGRA_SDMMC_PWR_CNTL_SD_BUS;
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writel(val, regs + TEGRA_SDMMC_PWR_CNTL);
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/* setup signaling */
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writel(0xffffffff, regs + TEGRA_SDMMC_INT_STAT_EN);
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writel(0xffffffff, regs + TEGRA_SDMMC_INT_SIG_EN);
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writel(0xe << 16, regs + TEGRA_SDMMC_CLK_CNTL);
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val = readl(regs + TEGRA_SDMMC_INT_STAT_EN);
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val &= ~(0xffff);
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val = (TEGRA_SDMMC_INT_STAT_EN_CMD_COMPLETE |
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TEGRA_SDMMC_INT_STAT_EN_XFER_COMPLETE |
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TEGRA_SDMMC_INT_STAT_EN_DMA_INTERRUPT |
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TEGRA_SDMMC_INT_STAT_EN_BUFFER_WRITE_READY |
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TEGRA_SDMMC_INT_STAT_EN_BUFFER_READ_READY);
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writel(val, regs + TEGRA_SDMMC_INT_STAT_EN);
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val = readl(regs + TEGRA_SDMMC_INT_SIG_EN);
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val &= ~(0xffff);
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val = TEGRA_SDMMC_INT_SIG_EN_XFER_COMPLETE;
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writel(val, regs + TEGRA_SDMMC_INT_SIG_EN);
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tegra_sdmmc_set_clock(host, 400000);
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return 0;
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}
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static int tegra_sdmmc_card_present(struct mci_host *mci)
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{
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struct tegra_sdmmc_host *host = to_tegra_sdmmc_host(mci);
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int ret;
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if (gpio_is_valid(host->gpio_cd)) {
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ret = gpio_direction_input(host->gpio_cd);
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if (ret)
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return 0;
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return gpio_get_value(host->gpio_cd) ? 0 : 1;
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}
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return !(readl(host->regs + SDHCI_PRESENT_STATE) & PRSSTAT_WPSPL);
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}
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static int tegra_sdmmc_detect(struct device_d *dev)
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{
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struct tegra_sdmmc_host *host = dev->priv;
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return mci_detect_card(&host->mci);
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}
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static void tegra_sdmmc_parse_dt(struct tegra_sdmmc_host *host)
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{
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struct device_node *np = host->mci.hw_dev->device_node;
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host->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0);
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host->gpio_pwr = of_get_named_gpio(np, "power-gpios", 0);
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mci_of_parse(&host->mci);
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}
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static int tegra_sdmmc_probe(struct device_d *dev)
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{
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struct tegra_sdmmc_host *host;
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struct mci_host *mci;
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int ret;
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|
||||
host = xzalloc(sizeof(*host));
|
||||
mci = &host->mci;
|
||||
|
||||
host->clk = clk_get(dev, NULL);
|
||||
if (IS_ERR(host->clk))
|
||||
return PTR_ERR(host->clk);
|
||||
|
||||
host->regs = dev_request_mem_region(dev, 0);
|
||||
if (!host->regs) {
|
||||
dev_err(dev, "could not get iomem region\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mci->hw_dev = dev;
|
||||
mci->f_max = 48000000;
|
||||
mci->f_min = 375000;
|
||||
tegra_sdmmc_parse_dt(host);
|
||||
|
||||
if (gpio_is_valid(host->gpio_pwr)) {
|
||||
ret = gpio_request(host->gpio_pwr, "tegra_sdmmc_power");
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to allocate power gpio\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
gpio_direction_output(host->gpio_pwr, 1);
|
||||
}
|
||||
|
||||
if (gpio_is_valid(host->gpio_cd)) {
|
||||
ret = gpio_request(host->gpio_cd, "tegra_sdmmc_cd");
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to allocate cd gpio\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
gpio_direction_input(host->gpio_cd);
|
||||
}
|
||||
|
||||
clk_enable(host->clk);
|
||||
|
||||
mci->init = tegra_sdmmc_init;
|
||||
mci->card_present = tegra_sdmmc_card_present;
|
||||
mci->set_ios = tegra_sdmmc_set_ios;
|
||||
mci->send_cmd = tegra_sdmmc_send_cmd;
|
||||
mci->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
|
||||
mci->host_caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED_52MHZ |
|
||||
MMC_CAP_SD_HIGHSPEED;
|
||||
|
||||
dev->priv = host;
|
||||
dev->detect = tegra_sdmmc_detect;
|
||||
|
||||
return mci_register(&host->mci);
|
||||
}
|
||||
|
||||
static __maybe_unused struct of_device_id tegra_sdmmc_compatible[] = {
|
||||
{
|
||||
.compatible = "nvidia,tegra30-sdhci",
|
||||
}, {
|
||||
.compatible = "nvidia,tegra20-sdhci",
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct driver_d tegra_sdmmc_driver = {
|
||||
.name = "tegra-sdmmc",
|
||||
.probe = tegra_sdmmc_probe,
|
||||
.of_compatible = DRV_OF_COMPAT(tegra_sdmmc_compatible),
|
||||
};
|
||||
device_platform_driver(tegra_sdmmc_driver);
|
||||
Loading…
Reference in New Issue