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at91: sync with the kernel address base 

add non AT91_SYS_BASE offset base address define

This will prepare for multi arch support

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD 2012-12-28 20:16:07 +01:00 committed by Sascha Hauer
parent a23017d350
commit 64c94fcd76
7 changed files with 171 additions and 59 deletions
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21
arch/arm/mach-at91/include/mach/at91rm9200.h
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@ -78,20 +78,31 @@
#define AT91RM9200_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals
*/
#define AT91RM9200_BASE_DBGU AT91_BASE_DBGU0 /* Debug Unit */
#define AT91RM9200_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91_BASE_PIOA 0xfffff400 /* PIO Controller A */
#define AT91_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91_BASE_PIOD 0xfffffa00 /* PIO Controller D */
#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA /* PIO Controller A */
#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB /* PIO Controller B */
#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC /* PIO Controller C */
#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD /* PIO Controller D */
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1

28
arch/arm/mach-at91/include/mach/at91sam9260.h
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@ -77,6 +77,24 @@
#define AT91SAM9260_BASE_ADC 0xfffe0000
#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals
*/
#define AT91SAM9260_BASE_ECC 0xffffe800
#define AT91SAM9260_BASE_SDRAMC 0xffffea00
#define AT91SAM9260_BASE_SMC 0xffffec00
#define AT91SAM9260_BASE_MATRIX 0xffffee00
#define AT91SAM9260_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800
#define AT91SAM9260_BASE_RSTC 0xfffffd00
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91SAM9260_BASE_GPBR 0xfffffd50
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
@ -84,19 +102,15 @@
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff400
#define AT91_BASE_PIOB 0xfffff600
#define AT91_BASE_PIOC 0xfffff800
#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
#define AT91_USART0 AT91SAM9260_BASE_US0
#define AT91_USART1 AT91SAM9260_BASE_US1

26
arch/arm/mach-at91/include/mach/at91sam9261.h
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@ -65,24 +65,38 @@
#define AT91_BASE_SYS 0xffffea00
/*
* System Peripherals
*/
#define AT91SAM9261_BASE_SMC 0xffffec00
#define AT91SAM9261_BASE_MATRIX 0xffffee00
#define AT91SAM9261_BASE_SDRAMC 0xffffea00
#define AT91SAM9261_BASE_DBGU AT91_BASE_DBGU0
#define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800
#define AT91SAM9261_BASE_RSTC 0xfffffd00
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
#define AT91SAM9261_BASE_WDT 0xfffffd40
#define AT91SAM9261_BASE_GPBR 0xfffffd50
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff400
#define AT91_BASE_PIOB 0xfffff600
#define AT91_BASE_PIOC 0xfffff800
#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
#define AT91_USART0 AT91SAM9261_BASE_US0
#define AT91_USART1 AT91SAM9261_BASE_US1

43
arch/arm/mach-at91/include/mach/at91sam9263.h
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@ -74,32 +74,49 @@
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals
*/
#define AT91SAM9263_BASE_ECC0 0xffffe000
#define AT91SAM9263_BASE_SDRAMC0 0xffffe200
#define AT91SAM9263_BASE_SMC0 0xffffe400
#define AT91SAM9263_BASE_ECC1 0xffffe600
#define AT91SAM9263_BASE_SDRAMC1 0xffffe800
#define AT91SAM9263_BASE_SMC1 0xffffea00
#define AT91SAM9263_BASE_MATRIX 0xffffec00
#define AT91SAM9263_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9263_BASE_PIOA 0xfffff200
#define AT91SAM9263_BASE_PIOB 0xfffff400
#define AT91SAM9263_BASE_PIOC 0xfffff600
#define AT91SAM9263_BASE_PIOD 0xfffff800
#define AT91SAM9263_BASE_PIOE 0xfffffa00
#define AT91SAM9263_BASE_RSTC 0xfffffd00
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
#define AT91SAM9263_BASE_WDT 0xfffffd40
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91SAM9263_BASE_GPBR 0xfffffd60
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff200
#define AT91_BASE_PIOB 0xfffff400
#define AT91_BASE_PIOC 0xfffff600
#define AT91_BASE_PIOD 0xfffff800
#define AT91_BASE_PIOE 0xfffffa00
#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
#define AT91_BASE_PIOD AT91SAM9263_BASE_PIOD
#define AT91_BASE_PIOE AT91SAM9263_BASE_PIOE
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1

38
arch/arm/mach-at91/include/mach/at91sam9g45.h
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@ -86,6 +86,29 @@
#define AT91SAM9G45_BASE_TC5 0xfffd4080
#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals
*/
#define AT91SAM9G45_BASE_ECC 0xffffe200
#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400
#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600
#define AT91SAM9G45_BASE_DMA 0xffffec00
#define AT91SAM9G45_BASE_SMC 0xffffe800
#define AT91SAM9G45_BASE_MATRIX 0xffffea00
#define AT91SAM9G45_BASE_DBGU AT91_BASE_DBGU1
#define AT91SAM9G45_BASE_PIOA 0xfffff200
#define AT91SAM9G45_BASE_PIOB 0xfffff400
#define AT91SAM9G45_BASE_PIOC 0xfffff600
#define AT91SAM9G45_BASE_PIOD 0xfffff800
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
#define AT91SAM9G45_BASE_RSTC 0xfffffd00
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
#define AT91SAM9G45_BASE_WDT 0xfffffd40
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
@ -94,22 +117,17 @@
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff200
#define AT91_BASE_PIOB 0xfffff400
#define AT91_BASE_PIOC 0xfffff600
#define AT91_BASE_PIOD 0xfffff800
#define AT91_BASE_PIOE 0xfffffa00
#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD
#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE
#define AT91_USART0 AT91SAM9G45_BASE_US0
#define AT91_USART1 AT91SAM9G45_BASE_US1

37
arch/arm/mach-at91/include/mach/at91sam9n12.h
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@ -81,29 +81,48 @@
#define AT91SAM9N12_BASE_ADC 0xf804c000
#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
*/
#define AT91SAM9N12_BASE_FUSE 0xffffdc00
#define AT91SAM9N12_BASE_MATRIX 0xffffde00
#define AT91SAM9N12_BASE_PMECC 0xffffe000
#define AT91SAM9N12_BASE_PMERRLOC 0xffffe600
#define AT91SAM9N12_BASE_DDRSDRC0 0xffffe800
#define AT91SAM9N12_BASE_SMC 0xffffea00
#define AT91SAM9N12_BASE_DMA 0xffffec00
#define AT91SAM9N12_BASE_AIC 0xfffff000
#define AT91SAM9N12_BASE_DBGU 0xfffff200
#define AT91SAM9N12_BASE_PIOA 0xfffff400
#define AT91SAM9N12_BASE_PIOB 0xfffff600
#define AT91SAM9N12_BASE_PIOC 0xfffff800
#define AT91SAM9N12_BASE_PIOD 0xfffffa00
#define AT91SAM9N12_BASE_PMC 0xfffffc00
#define AT91SAM9N12_BASE_RSTC 0xfffffe00
#define AT91SAM9N12_BASE_SHDWC 0xfffffe10
#define AT91SAM9N12_BASE_PIT 0xfffffe30
#define AT91SAM9N12_BASE_WDT 0xfffffe40
#define AT91SAM9N12_BASE_GPBR 0xfffffe60
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_FUSE (0xffffdc00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff400
#define AT91_BASE_PIOB 0xfffff600
#define AT91_BASE_PIOC 0xfffff800
#define AT91_BASE_PIOD 0xfffffa00
#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD
#define AT91_USART0 AT91SAM9X5_BASE_US0
#define AT91_USART1 AT91SAM9X5_BASE_US1

37
arch/arm/mach-at91/include/mach/at91sam9x5.h
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@ -88,6 +88,30 @@
#define AT91SAM9X5_BASE_ADC 0xf804c000
#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
*/
#define AT91SAM9X5_BASE_MATRIX 0xffffde00
#define AT9SAM9X5_BASE1_PMECC 0xffffe000
#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
#define AT91SAM9X5_BASE_SMC 0xffffea00
#define AT91SAM9X5_BASE_DMA0 0xffffec00
#define AT91SAM9X5_BASE_DMA1 0xffffee00
#define AT91SAM9X5_BASE_AIC 0xfffff000
#define AT91SAM9X5_BASE_DBGU 0xfffff200
#define AT91SAM9X5_BASE_PIOA 0xfffff400
#define AT91SAM9X5_BASE_PIOB 0xfffff600
#define AT91SAM9X5_BASE_PIOC 0xfffff800
#define AT91SAM9X5_BASE_PIOD 0xfffffa00
#define AT91SAM9X5_BASE_PMC 0xfffffc00
#define AT91SAM9X5_BASE_RSTC 0xfffffe00
#define AT91SAM9X5_BASE_SHDWC 0xfffffe10
#define AT91SAM9X5_BASE_PIT 0xfffffe30
#define AT91SAM9X5_BASE_WDT 0xfffffe40
#define AT91SAM9X5_BASE_GPBR 0xfffffe60
#define AT91SAM9X5_BASE_RTC 0xfffffeb0
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
@ -96,21 +120,16 @@
#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_DMA0 (0xffffec00 - AT91_BASE_SYS)
#define AT91_DMA1 (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffe30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffe40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS)
#define AT91_RTC (0xfffffeb0 - AT91_BASE_SYS)
#define AT91_BASE_PIOA 0xfffff400
#define AT91_BASE_PIOB 0xfffff600
#define AT91_BASE_PIOC 0xfffff800
#define AT91_BASE_PIOD 0xfffffa00
#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD
#define AT91_USART0 AT91SAM9X5_BASE_US0
#define AT91_USART1 AT91SAM9X5_BASE_US1