common: DDR3 SPD verification support
Add DDR3 SPD verification support for use by the PPC 8xxx DDR driver. This is based on the equivalent files from U-Boot version git-be937b5. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
df188547a9
commit
64e38721cd
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@ -57,6 +57,7 @@ config MPC8544
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config DDR_SPD
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bool
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select CRC16
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default y
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config FSL_DDR2
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@ -7,6 +7,7 @@
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*/
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#include <common.h>
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#include <crc.h>
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#include <ddr_spd.h>
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uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd)
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@ -37,3 +38,26 @@ uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd)
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error:
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return 1;
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}
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uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd)
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{
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char crc_lsb, crc_msb;
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int csum16, len;
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/*
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* SPD byte0[7] - CRC coverage
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* 0 = CRC covers bytes 0~125
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* 1 = CRC covers bytes 0~116
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*/
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len = !(spd->info_size_crc & 0x80) ? 126 : 117;
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csum16 = cyg_crc16((char *)spd, len);
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crc_lsb = (char) (csum16 & 0xff);
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crc_msb = (char) (csum16 >> 8);
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if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb)
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return 1;
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return 0;
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}
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@ -114,13 +114,126 @@ struct ddr2_spd_eeprom_s {
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uint8_t mdate[2]; /* 93 Manufacturing Date */
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uint8_t sernum[4]; /* 95 Assembly Serial Number */
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uint8_t mspec[27]; /* 99-127 Manufacturer Specific Data */
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};
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struct ddr3_spd_eeprom_s {
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/* General Section: Bytes 0-59 */
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uint8_t info_size_crc; /* 0 # bytes written into serial memory,
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CRC coverage */
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uint8_t spd_rev; /* 1 Total # bytes of SPD mem device */
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uint8_t mem_type; /* 2 Key Byte / Fundamental mem type */
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uint8_t module_type; /* 3 Key Byte / Module Type */
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uint8_t density_banks; /* 4 SDRAM Density and Banks */
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uint8_t addressing; /* 5 SDRAM Addressing */
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uint8_t module_vdd; /* 6 Module nominal voltage, VDD */
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uint8_t organization; /* 7 Module Organization */
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uint8_t bus_width; /* 8 Module Memory Bus Width */
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uint8_t ftb_div; /* 9 Fine Timebase (FTB)
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Dividend / Divisor */
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uint8_t mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */
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uint8_t mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */
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uint8_t tck_min; /* 12 SDRAM Minimum Cycle Time */
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uint8_t res_13; /* 13 Reserved */
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uint8_t caslat_lsb; /* 14 CAS Latencies Supported,
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Least Significant Byte */
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uint8_t caslat_msb; /* 15 CAS Latencies Supported,
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Most Significant Byte */
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uint8_t taa_min; /* 16 Min CAS Latency Time */
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uint8_t twr_min; /* 17 Min Write REcovery Time */
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uint8_t trcd_min; /* 18 Min RAS# to CAS# Delay Time */
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uint8_t trrd_min; /* 19 Min Row Active to
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Row Active Delay Time */
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uint8_t trp_min; /* 20 Min Row Precharge Delay Time */
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uint8_t tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */
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uint8_t tras_min_lsb; /* 22 Min Active to Precharge
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Delay Time */
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uint8_t trc_min_lsb; /* 23 Min Active to Active/Refresh
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Delay Time, LSB */
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uint8_t trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */
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uint8_t trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */
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uint8_t twtr_min; /* 26 Min Internal Write to
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Read Command Delay Time */
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uint8_t trtp_min; /* 27 Min Internal Read to Precharge
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Command Delay Time */
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uint8_t tfaw_msb; /* 28 Upper Nibble for tFAW */
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uint8_t tfaw_min; /* 29 Min Four Activate Window
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Delay Time*/
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uint8_t opt_features; /* 30 SDRAM Optional Features */
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uint8_t therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
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uint8_t therm_sensor; /* 32 Module Thermal Sensor */
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uint8_t device_type; /* 33 SDRAM device type */
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int8_t fine_tck_min; /* 34 Fine offset for tCKmin */
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int8_t fine_taa_min; /* 35 Fine offset for tAAmin */
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int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */
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int8_t fine_trp_min; /* 37 Fine offset for tRPmin */
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int8_t fine_trc_min; /* 38 Fine offset for tRCmin */
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uint8_t res_39_59[21]; /* 39-59 Reserved, General Section */
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/* Module-Specific Section: Bytes 60-116 */
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union {
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struct {
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/* 60 (Unbuffered) Module Nominal Height */
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uint8_t mod_height;
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/* 61 (Unbuffered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 62 (Unbuffered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 63 (Unbuffered) Address Mapping from
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Edge Connector to DRAM */
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uint8_t addr_mapping;
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/* 64-116 (Unbuffered) Reserved */
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uint8_t res_64_116[53];
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} unbuffered;
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struct {
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/* 60 (Registered) Module Nominal Height */
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uint8_t mod_height;
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/* 61 (Registered) Module Maximum Thickness */
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uint8_t mod_thickness;
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/* 62 (Registered) Reference Raw Card Used */
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uint8_t ref_raw_card;
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/* 63 DIMM Module Attributes */
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uint8_t modu_attr;
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/* 64 RDIMM Thermal Heat Spreader Solution */
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uint8_t thermal;
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/* 65 Register Manufacturer ID Code, LSB */
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uint8_t reg_id_lo;
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/* 66 Register Manufacturer ID Code, MSB */
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uint8_t reg_id_hi;
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/* 67 Register Revision Number */
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uint8_t reg_rev;
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/* 68 Register Type */
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uint8_t reg_type;
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/* 69-76 RC1,3,5..15 (MS Nib.)/RC0,2,4..14 (LS Nib.) */
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uint8_t rcw[8];
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} registered;
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uint8_t uc[57]; /* 60-116 Module-Specific Section */
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} mod_section;
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/* Unique Module ID: Bytes 117-125 */
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uint8_t mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
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uint8_t mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
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uint8_t mloc; /* 119 Mfg Location */
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uint8_t mdate[2]; /* 120-121 Mfg Date */
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uint8_t sernum[4]; /* 122-125 Module Serial Number */
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/* CRC: Bytes 126-127 */
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uint8_t crc[2]; /* 126-127 SPD CRC */
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/* Other Manufacturer Fields and User Space: Bytes 128-255 */
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uint8_t mpart[18]; /* 128-145 Mfg's Module Part Number */
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uint8_t mrev[2]; /* 146-147 Module Revision Code */
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uint8_t dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
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uint8_t dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
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uint8_t msd[26]; /* 150-175 Mfg's Specific Data */
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uint8_t cust[80]; /* 176-255 Open for Customer Use */
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};
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extern uint32_t ddr3_spd_checksum_pass(const struct ddr3_spd_eeprom_s *spd);
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extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);
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/* * Byte 2 Fundamental Memory Types. */
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#define SPD_MEMTYPE_DDR2 (0x08)
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#define SPD_MEMTYPE_DDR3 (0x0B)
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/* DIMM Type for DDR2 SPD (according to v1.3) */
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#define DDR2_SPD_DIMMTYPE_RDIMM (0x01)
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@ -132,4 +245,7 @@ extern uint32_t ddr2_spd_checksum_pass(const struct ddr2_spd_eeprom_s *spd);
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#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10)
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#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20)
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/* Byte 3 Key Byte / Module Type for DDR3 SPD */
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#define DDR3_SPD_MODULETYPE_MASK (0x0F)
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#define DDR3_SPD_MODULETYPE_UDIMM (0x02)
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#endif /* _DDR_SPD_H_ */
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