MIPS: add PCI support for GT64120-based Malta board
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
parent
a7c925bf03
commit
657f7eac3f
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@ -45,6 +45,7 @@ config MACH_MIPS_MALTA
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_BIG_ENDIAN
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select HAS_DEBUG_LL
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select HAS_DEBUG_LL
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select GPIOLIB
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select GPIOLIB
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select HW_HAS_PCI
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config MACH_MIPS_AR231X
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config MACH_MIPS_AR231X
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bool "Atheros ar231x-based boards"
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bool "Atheros ar231x-based boards"
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@ -18,6 +18,8 @@
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#ifndef _ASM_GT64120_H
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#ifndef _ASM_GT64120_H
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#define _ASM_GT64120_H
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#define _ASM_GT64120_H
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#define MSK(n) ((1 << (n)) - 1)
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#define GT_DEF_BASE 0x14000000
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#define GT_DEF_BASE 0x14000000
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/*
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/*
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@ -34,4 +36,55 @@
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#define GT_PCI0M1LD_OFS 0x080
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#define GT_PCI0M1LD_OFS 0x080
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#define GT_PCI0M1HD_OFS 0x088
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#define GT_PCI0M1HD_OFS 0x088
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#define GT_PCI0IOREMAP_OFS 0x0f0
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#define GT_PCI0M0REMAP_OFS 0x0f8
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#define GT_PCI0M1REMAP_OFS 0x100
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/* Interrupts. */
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#define GT_INTRCAUSE_OFS 0xc18
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/* PCI Internal. */
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#define GT_PCI0_CMD_OFS 0xc00
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#define GT_PCI0_CFGADDR_OFS 0xcf8
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#define GT_PCI0_CFGDATA_OFS 0xcfc
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#define GT_PCI_DCRM_SHF 21
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#define GT_PCI_LD_SHF 0
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#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
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#define GT_PCI_HD_SHF 0
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#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
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#define GT_PCI_REMAP_SHF 0
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#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
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#define GT_INTRCAUSE_MASABORT0_SHF 18
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#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
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#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
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#define GT_INTRCAUSE_TARABORT0_SHF 19
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#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
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#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
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#define GT_PCI0_CFGADDR_REGNUM_SHF 2
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#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
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#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
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#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
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#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
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#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
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#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
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#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
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#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
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/*
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* Because of an error/peculiarity in the Galileo chip, we need to swap the
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* bytes when running bigendian. We also provide non-swapping versions.
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*/
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#define __GT_READ(ofs) \
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(*(volatile u32 *)(GT64120_BASE+(ofs)))
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#define __GT_WRITE(ofs, data) \
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do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
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#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
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#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
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#endif /* _ASM_GT64120_H */
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#endif /* _ASM_GT64120_H */
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@ -1 +1,2 @@
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obj-y += reset.o
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obj-y += reset.o
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obj-$(CONFIG_PCI) += pci.o
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@ -10,4 +10,6 @@
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#define MIPS_GT_BASE 0x1be00000
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#define MIPS_GT_BASE 0x1be00000
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#define GT64120_BASE 0xbbe00000
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#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
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#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
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@ -0,0 +1,236 @@
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#include <common.h>
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#include <types.h>
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#include <driver.h>
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#include <init.h>
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#include <mach/hardware.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <linux/pci.h>
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#include <asm/gt64120.h>
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#include <mach/mach-gt64120.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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static struct resource gt64120_mem_resource = {
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.name = "GT-64120 PCI MEM",
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.flags = IORESOURCE_MEM,
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};
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static struct resource gt64120_io_resource = {
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.name = "GT-64120 PCI I/O",
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.flags = IORESOURCE_IO,
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};
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static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 *data)
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{
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unsigned char busnum = bus->number;
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u32 intr;
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if ((busnum == 0) && (devfn >= PCI_DEVFN(31, 0)))
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return -1; /* Because of a bug in the galileo (for slot 31). */
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/* Clear cause register bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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/* Setup address */
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(busnum << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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(devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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if (access_type == PCI_ACCESS_WRITE) {
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if (busnum == 0 && PCI_SLOT(devfn) == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
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} else
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__GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
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} else {
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if (busnum == 0 && PCI_SLOT(devfn) == 0) {
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/*
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* The Galileo system controller is acting
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* differently than other devices.
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*/
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*data = GT_READ(GT_PCI0_CFGDATA_OFS);
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} else
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*data = __GT_READ(GT_PCI0_CFGDATA_OFS);
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}
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/* Check for master or target abort */
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intr = GT_READ(GT_INTRCAUSE_OFS);
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if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) {
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/* Error occurred */
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/* Clear bits */
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GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
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GT_INTRCAUSE_TARABORT0_BIT));
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return -1;
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}
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 data = 0;
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if (size == 4)
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data = val;
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else {
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
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devfn, where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
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where, &data))
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return PCIBIOS_DEVICE_NOT_FOUND;
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return PCIBIOS_SUCCESSFUL;
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}
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/* function returns memory address for begin of pci resource */
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static int gt64xxx_res_start(struct pci_bus *bus, resource_size_t res_addr)
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{
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return KSEG0ADDR(res_addr);
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}
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struct pci_ops gt64xxx_pci0_ops = {
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.read = gt64xxx_pci0_pcibios_read,
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.write = gt64xxx_pci0_pcibios_write,
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.res_start = gt64xxx_res_start,
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};
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static struct pci_controller gt64120_controller = {
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.pci_ops = >64xxx_pci0_ops,
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.io_resource = >64120_io_resource,
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.mem_resource = >64120_mem_resource,
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};
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static int pcibios_init(void)
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{
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resource_size_t start, end, map, start1, end1, map1, mask, res_end;
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/*
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* Due to a bug in the Galileo system controller, we need
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* to setup the PCI BAR for the Galileo internal registers.
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* This should be done in the bios/bootprom and will be
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* fixed in a later revision of YAMON (the MIPS boards
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* boot prom).
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*/
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GT_WRITE(GT_PCI0_CFGADDR_OFS,
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(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
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(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 dev */
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(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0*/
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((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4*/
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GT_PCI0_CFGADDR_CONFIGEN_BIT);
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/* Perform the write */
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GT_WRITE(GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
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/* Here is linux code. It assumes, that firmware
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(pbl in case of barebox) made the work... */
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/* Set up resource ranges from the controller's registers. */
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start = GT_READ(GT_PCI0M0LD_OFS);
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end = GT_READ(GT_PCI0M0HD_OFS);
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map = GT_READ(GT_PCI0M0REMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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start1 = GT_READ(GT_PCI0M1LD_OFS);
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end1 = GT_READ(GT_PCI0M1HD_OFS);
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map1 = GT_READ(GT_PCI0M1REMAP_OFS);
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end1 = (end1 & GT_PCI_HD_MSK) | (start1 & ~GT_PCI_HD_MSK);
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_mem_resource.start = start;
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gt64120_mem_resource.end = end;
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gt64120_controller.mem_offset = (start & mask) - (map & mask);
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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gt64120_controller.mem_offset <<= GT_PCI_DCRM_SHF;
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start = GT_READ(GT_PCI0IOLD_OFS);
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end = GT_READ(GT_PCI0IOHD_OFS);
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map = GT_READ(GT_PCI0IOREMAP_OFS);
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end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
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mask = ~(start ^ end);
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/* We don't support remapping with a discontiguous mask. */
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BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
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mask != ~((mask & -mask) - 1));
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gt64120_io_resource.start = map & mask;
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res_end = (map & mask) | ~mask;
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gt64120_controller.io_offset = 0;
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/* Addresses are 36-bit, so do shifts in the destinations. */
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gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end <<= GT_PCI_DCRM_SHF;
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gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
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GT_PCI0_CMD_SBYTESWAP_BIT);
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#else
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GT_WRITE(GT_PCI0_CMD_OFS, 0);
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#endif
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/* Fix up PCI I/O mapping if necessary (for Atlas). */
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start = GT_READ(GT_PCI0IOLD_OFS);
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map = GT_READ(GT_PCI0IOREMAP_OFS);
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if ((start & map) != 0) {
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map &= ~start;
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GT_WRITE(GT_PCI0IOREMAP_OFS, map);
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}
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register_pci_controller(>64120_controller);
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return 0;
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}
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postcore_initcall(pcibios_init);
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