mtd: nand: update to v3.11-rc1
This updates the NAND stuff to Linux-3.11-rc1. It is synchronized as best as we can get: - locks removed - The splitting in different files we had to better support different features has been dropped. Instead this is now done mostly with the use of __maybe_unused Some barebox adjustments are forward ported, like: - Allow partial page writes - Optionally allow to erase bad blocks - check for all_ff before writing a page Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
69f3d6c93b
commit
66891566cc
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@ -43,8 +43,6 @@ static int nhk8815_nand_init(void)
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}
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static struct nomadik_nand_platform_data nhk8815_nand_data = {
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.options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
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| NAND_NO_READRDY | NAND_NO_AUTOINCR,
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.init = nhk8815_nand_init,
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};
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@ -13,11 +13,20 @@ config NAND_ECC_SOFT
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default y
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prompt "Support software ecc"
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config NAND_ECC_BCH
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select BCH
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bool
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prompt "Support software BCH ecc"
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config NAND_ECC_HW
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bool
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default y
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prompt "Support hardware ecc"
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config NAND_ECC_HW_OOB_FIRST
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bool
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prompt "Support hardware ecc (oob first)"
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config NAND_ECC_HW_SYNDROME
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bool
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default y
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@ -64,8 +73,9 @@ config NAND_IMX
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config NAND_IMX_BBM
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bool
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prompt "i.MX NAND flash bbt creation command"
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depends on NAND_BBT
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depends on NAND_IMX
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prompt "i.MX NAND flash bbt creation command"
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config NAND_MXS
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bool
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@ -100,15 +110,6 @@ config NAND_S3C24XX
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help
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Add support for processor's NAND device controller.
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config MTD_NAND_VERIFY_WRITE
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bool "Verify NAND page writes"
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help
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This adds an extra check when data is written to the flash. The
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NAND flash device internally checks only bits transitioning
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from 1 to 0. There is a rare possibility that even though the
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device thinks the write was successful, a bit could have been
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flipped accidentally due to device wear or something else.
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config MTD_NAND_ECC_SMC
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bool "NAND ECC Smart Media byte order"
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default n
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@ -116,14 +117,6 @@ config MTD_NAND_ECC_SMC
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Software ECC according to the Smart Media Specification.
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The original Linux implementation had byte 0 and 1 swapped.
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config MTD_NAND_MUSEUM_IDS
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bool "Enable chip ids for obsolete ancient NAND devices"
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default n
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help
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Enable this option only when your board has first generation
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NAND chips (page size 256 byte, erase size 4-8KiB). The IDs
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of these chips were reused by later, larger chips.
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config MTD_NAND_IDS
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tristate
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@ -1,10 +1,7 @@
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# Generic NAND options
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obj-$(CONFIG_NAND) += nand_ecc.o
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obj-$(CONFIG_MTD_WRITE) += nand_write.o
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obj-$(CONFIG_NAND_ECC_SOFT) += nand_ecc.o nand_swecc.o
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obj-$(CONFIG_NAND_ECC_HW) += nand_hwecc.o
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obj-$(CONFIG_NAND_ECC_HW_SYNDROME) += nand_hwecc_syndrome.o
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obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
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obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o
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obj-$(CONFIG_NAND) += nand_base.o nand-bb.o
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obj-$(CONFIG_NAND_BBT) += nand_bbt.o
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@ -624,7 +624,7 @@ normal_check:
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}
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static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, uint8_t *buf)
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struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
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{
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struct atmel_nand_host *host = chip->priv;
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int eccsize = chip->ecc.size;
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@ -659,8 +659,9 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
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return 0;
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}
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static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
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struct nand_chip *chip, const uint8_t *buf)
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static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
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struct nand_chip *chip, const uint8_t *buf,
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int oob_required)
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{
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struct atmel_nand_host *host = chip->priv;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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@ -681,7 +682,7 @@ static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
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!(pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY));
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if (ret) {
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dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
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return;
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return -ETIMEDOUT;
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}
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for (i = 0; i < host->pmecc_sector_number; i++) {
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@ -694,6 +695,8 @@ static void atmel_nand_pmecc_write_page(struct mtd_info *mtd,
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}
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}
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chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
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return 0;
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}
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static void atmel_pmecc_core_init(struct mtd_info *mtd)
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@ -881,7 +884,7 @@ static int atmel_nand_calculate(struct mtd_info *mtd,
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* buf: buffer to store read data
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*/
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static int atmel_nand_read_page(struct mtd_info *mtd,
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struct nand_chip *chip, uint8_t *buf)
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struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
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{
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int eccsize = chip->ecc.size;
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int eccbytes = chip->ecc.bytes;
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@ -1201,7 +1204,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
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/* first scan to find the device and get the page size */
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if (nand_scan_ident(mtd, 1)) {
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if (nand_scan_ident(mtd, 1, NULL)) {
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res = -ENXIO;
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goto err_scan_ident;
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}
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@ -17,7 +17,8 @@ void multi_erase_cmd(struct mtd_info *mtd, int page);
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void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf);
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int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int page, int cached, int raw);
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uint32_t offset, int data_len, const uint8_t *buf,
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int oob_required, int page, int cached, int raw);
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int nand_erase(struct mtd_info *mtd, struct erase_info *instr);
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int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
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size_t *retlen, const uint8_t *buf);
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,243 @@
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/*
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* This file provides ECC correction for more than 1 bit per block of data,
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* using binary BCH codes. It relies on the generic BCH library lib/bch.c.
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*
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* Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
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*
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* This file is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 or (at your option) any
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* later version.
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*
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* This file is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this file; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_bch.h>
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#include <linux/bch.h>
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/**
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* struct nand_bch_control - private NAND BCH control structure
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* @bch: BCH control structure
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* @ecclayout: private ecc layout for this BCH configuration
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* @errloc: error location array
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* @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
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*/
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struct nand_bch_control {
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struct bch_control *bch;
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struct nand_ecclayout ecclayout;
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unsigned int *errloc;
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unsigned char *eccmask;
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};
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/**
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* nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
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* @mtd: MTD block structure
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* @buf: input buffer with raw data
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* @code: output buffer with ECC
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*/
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int nand_bch_calculate_ecc(struct mtd_info *mtd, const unsigned char *buf,
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unsigned char *code)
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{
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const struct nand_chip *chip = mtd->priv;
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struct nand_bch_control *nbc = chip->ecc.priv;
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unsigned int i;
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memset(code, 0, chip->ecc.bytes);
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encode_bch(nbc->bch, buf, chip->ecc.size, code);
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/* apply mask so that an erased page is a valid codeword */
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for (i = 0; i < chip->ecc.bytes; i++)
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code[i] ^= nbc->eccmask[i];
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return 0;
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}
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EXPORT_SYMBOL(nand_bch_calculate_ecc);
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/**
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* nand_bch_correct_data - [NAND Interface] Detect and correct bit error(s)
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* @mtd: MTD block structure
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* @buf: raw data read from the chip
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* @read_ecc: ECC from the chip
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* @calc_ecc: the ECC calculated from raw data
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*
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* Detect and correct bit errors for a data byte block
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*/
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int nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
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unsigned char *read_ecc, unsigned char *calc_ecc)
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{
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const struct nand_chip *chip = mtd->priv;
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struct nand_bch_control *nbc = chip->ecc.priv;
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unsigned int *errloc = nbc->errloc;
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int i, count;
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count = decode_bch(nbc->bch, NULL, chip->ecc.size, read_ecc, calc_ecc,
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NULL, errloc);
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if (count > 0) {
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for (i = 0; i < count; i++) {
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if (errloc[i] < (chip->ecc.size*8))
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/* error is located in data, correct it */
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buf[errloc[i] >> 3] ^= (1 << (errloc[i] & 7));
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/* else error in ecc, no action needed */
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pr_debug("%s: corrected bitflip %u\n", __func__,
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errloc[i]);
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}
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} else if (count < 0) {
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printk(KERN_ERR "ecc unrecoverable error\n");
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count = -1;
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}
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return count;
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}
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EXPORT_SYMBOL(nand_bch_correct_data);
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/**
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* nand_bch_init - [NAND Interface] Initialize NAND BCH error correction
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* @mtd: MTD block structure
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* @eccsize: ecc block size in bytes
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* @eccbytes: ecc length in bytes
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* @ecclayout: output default layout
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*
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* Returns:
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* a pointer to a new NAND BCH control structure, or NULL upon failure
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*
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* Initialize NAND BCH error correction. Parameters @eccsize and @eccbytes
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* are used to compute BCH parameters m (Galois field order) and t (error
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* correction capability). @eccbytes should be equal to the number of bytes
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* required to store m*t bits, where m is such that 2^m-1 > @eccsize*8.
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*
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* Example: to configure 4 bit correction per 512 bytes, you should pass
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* @eccsize = 512 (thus, m=13 is the smallest integer such that 2^m-1 > 512*8)
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* @eccbytes = 7 (7 bytes are required to store m*t = 13*4 = 52 bits)
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*/
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struct nand_bch_control *
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nand_bch_init(struct mtd_info *mtd, unsigned int eccsize, unsigned int eccbytes,
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struct nand_ecclayout **ecclayout)
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{
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unsigned int m, t, eccsteps, i;
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struct nand_ecclayout *layout;
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struct nand_bch_control *nbc = NULL;
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unsigned char *erased_page;
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if (!eccsize || !eccbytes) {
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printk(KERN_WARNING "ecc parameters not supplied\n");
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goto fail;
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}
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m = fls(1+8*eccsize);
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t = (eccbytes*8)/m;
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nbc = kzalloc(sizeof(*nbc), GFP_KERNEL);
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if (!nbc)
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goto fail;
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nbc->bch = init_bch(m, t, 0);
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if (!nbc->bch)
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goto fail;
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/* verify that eccbytes has the expected value */
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if (nbc->bch->ecc_bytes != eccbytes) {
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printk(KERN_WARNING "invalid eccbytes %u, should be %u\n",
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eccbytes, nbc->bch->ecc_bytes);
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goto fail;
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}
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eccsteps = mtd->writesize/eccsize;
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/* if no ecc placement scheme was provided, build one */
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if (!*ecclayout) {
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/* handle large page devices only */
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if (mtd->oobsize < 64) {
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printk(KERN_WARNING "must provide an oob scheme for "
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"oobsize %d\n", mtd->oobsize);
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goto fail;
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}
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layout = &nbc->ecclayout;
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layout->eccbytes = eccsteps*eccbytes;
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/* reserve 2 bytes for bad block marker */
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if (layout->eccbytes+2 > mtd->oobsize) {
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printk(KERN_WARNING "no suitable oob scheme available "
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"for oobsize %d eccbytes %u\n", mtd->oobsize,
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eccbytes);
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goto fail;
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}
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/* put ecc bytes at oob tail */
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for (i = 0; i < layout->eccbytes; i++)
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layout->eccpos[i] = mtd->oobsize-layout->eccbytes+i;
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layout->oobfree[0].offset = 2;
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layout->oobfree[0].length = mtd->oobsize-2-layout->eccbytes;
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*ecclayout = layout;
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}
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/* sanity checks */
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if (8*(eccsize+eccbytes) >= (1 << m)) {
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printk(KERN_WARNING "eccsize %u is too large\n", eccsize);
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goto fail;
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}
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if ((*ecclayout)->eccbytes != (eccsteps*eccbytes)) {
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printk(KERN_WARNING "invalid ecc layout\n");
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goto fail;
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}
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nbc->eccmask = kmalloc(eccbytes, GFP_KERNEL);
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nbc->errloc = kmalloc(t*sizeof(*nbc->errloc), GFP_KERNEL);
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if (!nbc->eccmask || !nbc->errloc)
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goto fail;
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/*
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* compute and store the inverted ecc of an erased ecc block
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*/
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erased_page = kmalloc(eccsize, GFP_KERNEL);
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if (!erased_page)
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goto fail;
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memset(erased_page, 0xff, eccsize);
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memset(nbc->eccmask, 0, eccbytes);
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encode_bch(nbc->bch, erased_page, eccsize, nbc->eccmask);
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kfree(erased_page);
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for (i = 0; i < eccbytes; i++)
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nbc->eccmask[i] ^= 0xff;
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return nbc;
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fail:
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nand_bch_free(nbc);
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return NULL;
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}
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EXPORT_SYMBOL(nand_bch_init);
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/**
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* nand_bch_free - [NAND Interface] Release NAND BCH ECC resources
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* @nbc: NAND BCH control structure
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*/
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void nand_bch_free(struct nand_bch_control *nbc)
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{
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if (nbc) {
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free_bch(nbc->bch);
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kfree(nbc->errloc);
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kfree(nbc->eccmask);
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kfree(nbc);
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}
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}
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EXPORT_SYMBOL(nand_bch_free);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Ivan Djelic <ivan.djelic@parrot.com>");
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MODULE_DESCRIPTION("NAND software BCH ECC support");
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@ -1,103 +0,0 @@
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#include <common.h>
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#include <errno.h>
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#include <clock.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/err.h>
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#include <linux/mtd/nand_ecc.h>
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#include <asm/byteorder.h>
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#include <io.h>
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#include <malloc.h>
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#include "nand.h"
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/**
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* nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
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* @mtd: mtd info structure
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* @chip: nand chip info structure
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* @buf: buffer to store read data
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*
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* Not for syndrome calculating ecc controllers which need a special oob layout
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*/
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static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf)
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{
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int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *p = buf;
|
||||
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
||||
uint8_t *ecc_code = chip->buffers->ecccode;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
||||
chip->read_buf(mtd, p, eccsize);
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
}
|
||||
chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
|
||||
for (i = 0; i < chip->ecc.total; i++)
|
||||
ecc_code[i] = chip->oob_poi[eccpos[i]];
|
||||
|
||||
eccsteps = chip->ecc.steps;
|
||||
p = buf;
|
||||
|
||||
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
int stat;
|
||||
|
||||
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
|
||||
if (stat < 0)
|
||||
mtd->ecc_stats.failed++;
|
||||
else
|
||||
mtd->ecc_stats.corrected += stat;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: data buffer
|
||||
*/
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
||||
const uint8_t *p = buf;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
|
||||
chip->write_buf(mtd, p, eccsize);
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
}
|
||||
|
||||
for (i = 0; i < chip->ecc.total; i++)
|
||||
chip->oob_poi[eccpos[i]] = ecc_calc[i];
|
||||
|
||||
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
}
|
||||
#endif
|
||||
|
||||
void nand_init_ecc_hw(struct nand_chip *chip)
|
||||
{
|
||||
/* Use standard hwecc read page function ? */
|
||||
if (!chip->ecc.read_page)
|
||||
chip->ecc.read_page = nand_read_page_hwecc;
|
||||
#ifdef CONFIG_NAND_READ_OOB
|
||||
if (!chip->ecc.read_oob)
|
||||
chip->ecc.read_oob = nand_read_oob_std;
|
||||
#endif
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
if (!chip->ecc.write_oob)
|
||||
chip->ecc.write_oob = nand_write_oob_std;
|
||||
if (!chip->ecc.write_page)
|
||||
chip->ecc.write_page = nand_write_page_hwecc;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <clock.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <io.h>
|
||||
#include <malloc.h>
|
||||
#include <module.h>
|
||||
|
||||
/**
|
||||
* nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: buffer to store read data
|
||||
*
|
||||
* The hw generator calculates the error syndrome automatically. Therefor
|
||||
* we need a special oob layout and handling.
|
||||
*/
|
||||
static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *p = buf;
|
||||
uint8_t *oob = chip->oob_poi;
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
int stat;
|
||||
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_READ);
|
||||
chip->read_buf(mtd, p, eccsize);
|
||||
|
||||
if (chip->ecc.prepad) {
|
||||
chip->read_buf(mtd, oob, chip->ecc.prepad);
|
||||
oob += chip->ecc.prepad;
|
||||
}
|
||||
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
|
||||
chip->read_buf(mtd, oob, eccbytes);
|
||||
stat = chip->ecc.correct(mtd, p, oob, NULL);
|
||||
|
||||
if (stat < 0)
|
||||
mtd->ecc_stats.failed++;
|
||||
else
|
||||
mtd->ecc_stats.corrected += stat;
|
||||
|
||||
oob += eccbytes;
|
||||
|
||||
if (chip->ecc.postpad) {
|
||||
chip->read_buf(mtd, oob, chip->ecc.postpad);
|
||||
oob += chip->ecc.postpad;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate remaining oob bytes */
|
||||
i = mtd->oobsize - (oob - chip->oob_poi);
|
||||
if (i)
|
||||
chip->read_buf(mtd, oob, i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: data buffer
|
||||
*
|
||||
* The hw generator calculates the error syndrome automatically. Therefor
|
||||
* we need a special oob layout and handling.
|
||||
*/
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
static void nand_write_page_syndrome(struct mtd_info *mtd,
|
||||
struct nand_chip *chip, const uint8_t *buf)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
const uint8_t *p = buf;
|
||||
uint8_t *oob = chip->oob_poi;
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
|
||||
chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
|
||||
chip->write_buf(mtd, p, eccsize);
|
||||
|
||||
if (chip->ecc.prepad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.prepad);
|
||||
oob += chip->ecc.prepad;
|
||||
}
|
||||
|
||||
chip->ecc.calculate(mtd, p, oob);
|
||||
chip->write_buf(mtd, oob, eccbytes);
|
||||
oob += eccbytes;
|
||||
|
||||
if (chip->ecc.postpad) {
|
||||
chip->write_buf(mtd, oob, chip->ecc.postpad);
|
||||
oob += chip->ecc.postpad;
|
||||
}
|
||||
}
|
||||
|
||||
/* Calculate remaining oob bytes */
|
||||
i = mtd->oobsize - (oob - chip->oob_poi);
|
||||
if (i)
|
||||
chip->write_buf(mtd, oob, i);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
|
||||
* with syndromes
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @page: page number to read
|
||||
* @sndcmd: flag whether to issue read command or not
|
||||
*/
|
||||
static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page, int sndcmd)
|
||||
{
|
||||
uint8_t *buf = chip->oob_poi;
|
||||
int length = mtd->oobsize;
|
||||
int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
|
||||
int eccsize = chip->ecc.size;
|
||||
uint8_t *bufpoi = buf;
|
||||
int i, toread, sndrnd = 0, pos;
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
|
||||
for (i = 0; i < chip->ecc.steps; i++) {
|
||||
if (sndrnd) {
|
||||
pos = eccsize + i * (eccsize + chunk);
|
||||
if (mtd->writesize > 512)
|
||||
chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
|
||||
else
|
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
|
||||
} else
|
||||
sndrnd = 1;
|
||||
toread = min_t(int, length, chunk);
|
||||
chip->read_buf(mtd, bufpoi, toread);
|
||||
bufpoi += toread;
|
||||
length -= toread;
|
||||
}
|
||||
if (length > 0)
|
||||
chip->read_buf(mtd, bufpoi, length);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
|
||||
* with syndrome - only for large page flash !
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @page: page number to write
|
||||
*/
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
static int nand_write_oob_syndrome(struct mtd_info *mtd,
|
||||
struct nand_chip *chip, int page)
|
||||
{
|
||||
int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
|
||||
int eccsize = chip->ecc.size, length = mtd->oobsize;
|
||||
int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
|
||||
const uint8_t *bufpoi = chip->oob_poi;
|
||||
|
||||
/*
|
||||
* data-ecc-data-ecc ... ecc-oob
|
||||
* or
|
||||
* data-pad-ecc-pad-data-pad .... ecc-pad-oob
|
||||
*/
|
||||
if (!chip->ecc.prepad && !chip->ecc.postpad) {
|
||||
pos = steps * (eccsize + chunk);
|
||||
steps = 0;
|
||||
} else
|
||||
pos = eccsize;
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
|
||||
for (i = 0; i < steps; i++) {
|
||||
if (sndcmd) {
|
||||
if (mtd->writesize <= 512) {
|
||||
uint32_t fill = 0xFFFFFFFF;
|
||||
|
||||
len = eccsize;
|
||||
while (len > 0) {
|
||||
int num = min_t(int, len, 4);
|
||||
chip->write_buf(mtd, (uint8_t *)&fill,
|
||||
num);
|
||||
len -= num;
|
||||
}
|
||||
} else {
|
||||
pos = eccsize + i * (eccsize + chunk);
|
||||
chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
|
||||
}
|
||||
} else
|
||||
sndcmd = 1;
|
||||
len = min_t(int, length, chunk);
|
||||
chip->write_buf(mtd, bufpoi, len);
|
||||
bufpoi += len;
|
||||
length -= len;
|
||||
}
|
||||
if (length > 0)
|
||||
chip->write_buf(mtd, bufpoi, length);
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
|
||||
return status & NAND_STATUS_FAIL ? -EIO : 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void nand_init_ecc_hw_syndrome(struct nand_chip *chip)
|
||||
{
|
||||
/* Use standard syndrome read/write page function ? */
|
||||
if (!chip->ecc.read_page)
|
||||
chip->ecc.read_page = nand_read_page_syndrome;
|
||||
if (!chip->ecc.read_oob)
|
||||
chip->ecc.read_oob = nand_read_oob_syndrome;
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
if (!chip->ecc.write_page)
|
||||
chip->ecc.write_page = nand_write_page_syndrome;
|
||||
if (!chip->ecc.write_oob)
|
||||
chip->ecc.write_oob = nand_write_oob_syndrome;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -3,184 +3,178 @@
|
|||
*
|
||||
* Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
|
||||
*
|
||||
* $Id: nand_ids.c,v 1.16 2005/11/07 11:14:31 gleixner Exp $
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <sizes.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
|
||||
#ifdef CONFIG_NAND_INFO
|
||||
#define __NANDSTR(str) str
|
||||
#define __STR(str) str
|
||||
#else
|
||||
#define __NANDSTR(str) ""
|
||||
#define __STR(str) ""
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Chip ID list
|
||||
*
|
||||
* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
|
||||
* options
|
||||
*
|
||||
* Pagesize; 0, 256, 512
|
||||
* 0 get this information from the extended chip ID
|
||||
+ 256 256 Byte page size
|
||||
* 512 512 Byte page size
|
||||
*/
|
||||
struct nand_flash_dev nand_flash_ids[] = {
|
||||
|
||||
#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
|
||||
{__NANDSTR("NAND 1MiB 5V 8-bit"), 0x6e, 256, 1, 0x1000, 0},
|
||||
{__NANDSTR("NAND 2MiB 5V 8-bit"), 0x64, 256, 2, 0x1000, 0},
|
||||
{__NANDSTR("NAND 4MiB 5V 8-bit"), 0x6b, 512, 4, 0x2000, 0},
|
||||
{__NANDSTR("NAND 1MiB 3,3V 8-bit"), 0xe8, 256, 1, 0x1000, 0},
|
||||
{__NANDSTR("NAND 1MiB 3,3V 8-bit"), 0xec, 256, 1, 0x1000, 0},
|
||||
{__NANDSTR("NAND 2MiB 3,3V 8-bit"), 0xea, 256, 2, 0x1000, 0},
|
||||
{__NANDSTR("NAND 4MiB 3,3V 8-bit"), 0xd5, 512, 4, 0x2000, 0},
|
||||
{__NANDSTR("NAND 4MiB 3,3V 8-bit"), 0xe3, 512, 4, 0x2000, 0},
|
||||
{__NANDSTR("NAND 4MiB 3,3V 8-bit"), 0xe5, 512, 4, 0x2000, 0},
|
||||
{__NANDSTR("NAND 8MiB 3,3V 8-bit"), 0xd6, 512, 8, 0x2000, 0},
|
||||
|
||||
{__NANDSTR("NAND 8MiB 1,8V 8-bit"), 0x39, 512, 8, 0x2000, 0},
|
||||
{__NANDSTR("NAND 8MiB 3,3V 8-bit"), 0xe6, 512, 8, 0x2000, 0},
|
||||
{__NANDSTR("NAND 8MiB 1,8V 16-bit"), 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 8MiB 3,3V 16-bit"), 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
|
||||
#endif
|
||||
|
||||
{__NANDSTR("NAND 16MiB 1,8V 8-bit"), 0x33, 512, 16, 0x4000, 0},
|
||||
{__NANDSTR("NAND 16MiB 3,3V 8-bit"), 0x73, 512, 16, 0x4000, 0},
|
||||
{__NANDSTR("NAND 16MiB 1,8V 16-bit"), 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 16MiB 3,3V 16-bit"), 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
|
||||
|
||||
{__NANDSTR("NAND 32MiB 1,8V 8-bit"), 0x35, 512, 32, 0x4000, 0},
|
||||
{__NANDSTR("NAND 32MiB 3,3V 8-bit"), 0x75, 512, 32, 0x4000, 0},
|
||||
{__NANDSTR("NAND 32MiB 1,8V 16-bit"), 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 32MiB 3,3V 16-bit"), 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
|
||||
|
||||
{__NANDSTR("NAND 64MiB 1,8V 8-bit"), 0x36, 512, 64, 0x4000, 0},
|
||||
{__NANDSTR("NAND 64MiB 3,3V 8-bit"), 0x76, 512, 64, 0x4000, 0},
|
||||
{__NANDSTR("NAND 64MiB 1,8V 16-bit"), 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 64MiB 3,3V 16-bit"), 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
|
||||
|
||||
{__NANDSTR("NAND 128MiB 1,8V 8-bit"), 0x78, 512, 128, 0x4000, 0},
|
||||
{__NANDSTR("NAND 128MiB 1,8V 8-bit"), 0x39, 512, 128, 0x4000, 0},
|
||||
{__NANDSTR("NAND 128MiB 3,3V 8-bit"), 0x79, 512, 128, 0x4000, 0},
|
||||
{__NANDSTR("NAND 128MiB 1,8V 16-bit"), 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 128MiB 1,8V 16-bit"), 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 128MiB 3,3V 16-bit"), 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
|
||||
{__NANDSTR("NAND 128MiB 3,3V 16-bit"), 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
|
||||
|
||||
{__NANDSTR("NAND 256MiB 3,3V 8-bit"), 0x71, 512, 256, 0x4000, 0},
|
||||
|
||||
/*
|
||||
* These are the new chips with large page size. The pagesize and the
|
||||
* erasesize is determined from the extended id bytes
|
||||
*/
|
||||
#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
|
||||
#define LP_OPTIONS NAND_SAMSUNG_LP_OPTIONS
|
||||
#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
|
||||
|
||||
/*512 Megabit */
|
||||
{__NANDSTR("NAND 64MiB 1,8V 8-bit"), 0xA2, 0, 64, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 64MiB 3,3V 8-bit"), 0xF2, 0, 64, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 64MiB 1,8V 16-bit"), 0xB2, 0, 64, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 64MiB 3,3V 16-bit"), 0xC2, 0, 64, 0, LP_OPTIONS16},
|
||||
|
||||
/* 1 Gigabit */
|
||||
{__NANDSTR("NAND 128MiB 1,8V 8-bit"), 0xA1, 0, 128, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 128MiB 3,3V 8-bit"), 0xF1, 0, 128, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 128MiB 1,8V 16-bit"), 0xB1, 0, 128, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 128MiB 3,3V 16-bit"), 0xC1, 0, 128, 0, LP_OPTIONS16},
|
||||
|
||||
/* 2 Gigabit */
|
||||
{__NANDSTR("NAND 256MiB 1,8V 8-bit"), 0xAA, 0, 256, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 256MiB 3,3V 8-bit"), 0xDA, 0, 256, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 256MiB 1,8V 16-bit"), 0xBA, 0, 256, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 256MiB 3,3V 16-bit"), 0xCA, 0, 256, 0, LP_OPTIONS16},
|
||||
|
||||
/* 4 Gigabit */
|
||||
{__NANDSTR("NAND 512MiB 1,8V 8-bit"), 0xAC, 0, 512, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 512MiB 3,3V 8-bit"), 0xDC, 0, 512, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 512MiB 1,8V 16-bit"), 0xBC, 0, 512, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 512MiB 3,3V 16-bit"), 0xCC, 0, 512, 0, LP_OPTIONS16},
|
||||
|
||||
/* 8 Gigabit */
|
||||
{__NANDSTR("NAND 1GiB 1,8V 8-bit"), 0xA3, 0, 1024, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 1GiB 3,3V 8-bit"), 0xD3, 0, 1024, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 1GiB 1,8V 16-bit"), 0xB3, 0, 1024, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 1GiB 3,3V 16-bit"), 0xC3, 0, 1024, 0, LP_OPTIONS16},
|
||||
|
||||
/* 16 Gigabit */
|
||||
{__NANDSTR("NAND 2GiB 1,8V 8-bit"), 0xA5, 0, 2048, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 2GiB 3,3V 8-bit"), 0xD5, 0, 2048, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 2GiB 1,8V 16-bit"), 0xB5, 0, 2048, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 2GiB 3,3V 16-bit"), 0xC5, 0, 2048, 0, LP_OPTIONS16},
|
||||
|
||||
/* 32 Gigabit */
|
||||
{__NANDSTR("NAND 4GiB 1,8V 8-bit"), 0xA7, 0, 4096, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 4GiB 3,3V 8-bit"), 0xD7, 0, 4096, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 4GiB 1,8V 16-bit"), 0xB7, 0, 4096, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 4GiB 3,3V 16-bit"), 0xC7, 0, 4096, 0, LP_OPTIONS16},
|
||||
|
||||
/* 64 Gigabit */
|
||||
{__NANDSTR("NAND 8GiB 1,8V 8-bit"), 0xAE, 0, 8192, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 8GiB 3,3V 8-bit"), 0xDE, 0, 8192, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 8GiB 1,8V 16-bit"), 0xBE, 0, 8192, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 8GiB 3,3V 16-bit"), 0xCE, 0, 8192, 0, LP_OPTIONS16},
|
||||
|
||||
/* 128 Gigabit */
|
||||
{__NANDSTR("NAND 16GiB 1,8V 8-bit"), 0x1A, 0, 16384, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 16GiB 3,3V 8-bit"), 0x3A, 0, 16384, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 16GiB 1,8V 16-bit"), 0x2A, 0, 16384, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 16GiB 3,3V 16-bit"), 0x4A, 0, 16384, 0, LP_OPTIONS16},
|
||||
|
||||
/* 256 Gigabit */
|
||||
{__NANDSTR("NAND 32GiB 1,8V 8-bit"), 0x1C, 0, 32768, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 32GiB 3,3V 8-bit"), 0x3C, 0, 32768, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 32GiB 1,8V 16-bit"), 0x2C, 0, 32768, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 32GiB 3,3V 16-bit"), 0x4C, 0, 32768, 0, LP_OPTIONS16},
|
||||
|
||||
/* 512 Gigabit */
|
||||
{__NANDSTR("NAND 64GiB 1,8V 8-bit"), 0x1E, 0, 65536, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 64GiB 3,3V 8-bit"), 0x3E, 0, 65536, 0, LP_OPTIONS},
|
||||
{__NANDSTR("NAND 64GiB 1,8V 16-bit"), 0x2E, 0, 65536, 0, LP_OPTIONS16},
|
||||
{__NANDSTR("NAND 64GiB 3,3V 16-bit"), 0x4E, 0, 65536, 0, LP_OPTIONS16},
|
||||
|
||||
/*
|
||||
* Renesas AND 1 Gigabit. Those chips do not support extended id and
|
||||
* have a strange page/block layout ! The chosen minimum erasesize is
|
||||
* 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
|
||||
* planes 1 block = 2 pages, but due to plane arrangement the blocks
|
||||
* 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
|
||||
* increase the eraseblock size so we chose a combined one which can be
|
||||
* erased in one go There are more speed improvements for reads and
|
||||
* writes possible, but not implemented now
|
||||
*/
|
||||
{__NANDSTR("AND 128MiB 3,3V 8-bit"), 0x01, 2048, 128, 0x4000,
|
||||
NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
|
||||
BBT_AUTO_REFRESH
|
||||
},
|
||||
|
||||
{NULL,}
|
||||
};
|
||||
#define SP_OPTIONS NAND_NEED_READRDY
|
||||
#define SP_OPTIONS16 (SP_OPTIONS | NAND_BUSWIDTH_16)
|
||||
|
||||
/*
|
||||
* Manufacturer ID list
|
||||
*/
|
||||
* The chip ID list:
|
||||
* name, device ID, page size, chip size in MiB, eraseblock size, options
|
||||
*
|
||||
* If page size and eraseblock size are 0, the sizes are taken from the
|
||||
* extended chip ID.
|
||||
*/
|
||||
struct nand_flash_dev nand_flash_ids[] = {
|
||||
/*
|
||||
* Some incompatible NAND chips share device ID's and so must be
|
||||
* listed by full ID. We list them first so that we can easily identify
|
||||
* the most specific match.
|
||||
*/
|
||||
{__STR("TC58NVG2S0F 4G 3.3V 8-bit"),
|
||||
{ .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
|
||||
SZ_4K, SZ_512, SZ_256K, 0, 8, 224},
|
||||
{__STR("TC58NVG3S0F 8G 3.3V 8-bit"),
|
||||
{ .id = {0x98, 0xd3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08} },
|
||||
SZ_4K, SZ_1K, SZ_256K, 0, 8, 232},
|
||||
{__STR("TC58NVG5D2 32G 3.3V 8-bit"),
|
||||
{ .id = {0x98, 0xd7, 0x94, 0x32, 0x76, 0x56, 0x09, 0x00} },
|
||||
SZ_8K, SZ_4K, SZ_1M, 0, 8, 640},
|
||||
{__STR("TC58NVG6D2 64G 3.3V 8-bit"),
|
||||
{ .id = {0x98, 0xde, 0x94, 0x82, 0x76, 0x56, 0x04, 0x20} },
|
||||
SZ_8K, SZ_8K, SZ_2M, 0, 8, 640},
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 4MiB 5V 8-bit"), 0x6B, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 4MiB 3,3V 8-bit"), 0xE3, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 4MiB 3,3V 8-bit"), 0xE5, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 8MiB 3,3V 8-bit"), 0xD6, 8, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 8MiB 3,3V 8-bit"), 0xE6, 8, SZ_8K, SP_OPTIONS),
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 16MiB 1,8V 8-bit"), 0x33, 16, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 16MiB 3,3V 8-bit"), 0x73, 16, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 16MiB 1,8V 16-bit"), 0x43, 16, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 16MiB 3,3V 16-bit"), 0x53, 16, SZ_16K, SP_OPTIONS16),
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 32MiB 1,8V 8-bit"), 0x35, 32, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 32MiB 3,3V 8-bit"), 0x75, 32, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 32MiB 1,8V 16-bit"), 0x45, 32, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 32MiB 3,3V 16-bit"), 0x55, 32, SZ_16K, SP_OPTIONS16),
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"), 0x36, 64, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"), 0x76, 64, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0x46, 64, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0x56, 64, SZ_16K, SP_OPTIONS16),
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"), 0x78, 128, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"), 0x39, 128, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"), 0x79, 128, SZ_16K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0x72, 128, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0x49, 128, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0x74, 128, SZ_16K, SP_OPTIONS16),
|
||||
LEGACY_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0x59, 128, SZ_16K, SP_OPTIONS16),
|
||||
|
||||
LEGACY_ID_NAND(__STR("NAND 256MiB 3,3V 8-bit"), 0x71, 256, SZ_16K, SP_OPTIONS),
|
||||
|
||||
/*
|
||||
* These are the new chips with large page size. Their page size and
|
||||
* eraseblock size are determined from the extended ID bytes.
|
||||
*/
|
||||
|
||||
/* 512 Megabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"), 0xA2, 64, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 8-bit"), 0xA0, 64, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"), 0xF2, 64, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"), 0xD0, 64, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 8-bit"), 0xF0, 64, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0xB2, 64, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 1,8V 16-bit"), 0xB0, 64, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0xC2, 64, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64MiB 3,3V 16-bit"), 0xC0, 64, LP_OPTIONS16),
|
||||
|
||||
/* 1 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 8-bit"), 0xA1, 128, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"), 0xF1, 128, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 8-bit"), 0xD1, 128, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0xB1, 128, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 3,3V 16-bit"), 0xC1, 128, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 128MiB 1,8V 16-bit"), 0xAD, 128, LP_OPTIONS16),
|
||||
|
||||
/* 2 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 256MiB 1,8V 8-bit"), 0xAA, 256, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 256MiB 3,3V 8-bit"), 0xDA, 256, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 256MiB 1,8V 16-bit"), 0xBA, 256, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 256MiB 3,3V 16-bit"), 0xCA, 256, LP_OPTIONS16),
|
||||
|
||||
/* 4 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 512MiB 1,8V 8-bit"), 0xAC, 512, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 512MiB 3,3V 8-bit"), 0xDC, 512, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 512MiB 1,8V 16-bit"), 0xBC, 512, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 512MiB 3,3V 16-bit"), 0xCC, 512, LP_OPTIONS16),
|
||||
|
||||
/* 8 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 1GiB 1,8V 8-bit"), 0xA3, 1024, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 1GiB 3,3V 8-bit"), 0xD3, 1024, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 1GiB 1,8V 16-bit"), 0xB3, 1024, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 1GiB 3,3V 16-bit"), 0xC3, 1024, LP_OPTIONS16),
|
||||
|
||||
/* 16 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 2GiB 1,8V 8-bit"), 0xA5, 2048, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 2GiB 3,3V 8-bit"), 0xD5, 2048, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 2GiB 1,8V 16-bit"), 0xB5, 2048, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 2GiB 3,3V 16-bit"), 0xC5, 2048, LP_OPTIONS16),
|
||||
|
||||
/* 32 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 4GiB 1,8V 8-bit"), 0xA7, 4096, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 4GiB 3,3V 8-bit"), 0xD7, 4096, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 4GiB 1,8V 16-bit"), 0xB7, 4096, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 4GiB 3,3V 16-bit"), 0xC7, 4096, LP_OPTIONS16),
|
||||
|
||||
/* 64 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 8GiB 1,8V 8-bit"), 0xAE, 8192, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 8GiB 3,3V 8-bit"), 0xDE, 8192, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 8GiB 1,8V 16-bit"), 0xBE, 8192, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 8GiB 3,3V 16-bit"), 0xCE, 8192, LP_OPTIONS16),
|
||||
|
||||
/* 128 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 16GiB 1,8V 8-bit"), 0x1A, 16384, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 16GiB 3,3V 8-bit"), 0x3A, 16384, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 16GiB 1,8V 16-bit"), 0x2A, 16384, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 16GiB 3,3V 16-bit"), 0x4A, 16384, LP_OPTIONS16),
|
||||
|
||||
/* 256 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 32GiB 1,8V 8-bit"), 0x1C, 32768, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 32GiB 3,3V 8-bit"), 0x3C, 32768, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 32GiB 1,8V 16-bit"), 0x2C, 32768, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 32GiB 3,3V 16-bit"), 0x4C, 32768, LP_OPTIONS16),
|
||||
|
||||
/* 512 Gigabit */
|
||||
EXTENDED_ID_NAND(__STR("NAND 64GiB 1,8V 8-bit"), 0x1E, 65536, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64GiB 3,3V 8-bit"), 0x3E, 65536, LP_OPTIONS),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64GiB 1,8V 16-bit"), 0x2E, 65536, LP_OPTIONS16),
|
||||
EXTENDED_ID_NAND(__STR("NAND 64GiB 3,3V 16-bit"), 0x4E, 65536, LP_OPTIONS16),
|
||||
|
||||
{NULL}
|
||||
};
|
||||
|
||||
/* Manufacturer IDs */
|
||||
struct nand_manufacturers nand_manuf_ids[] = {
|
||||
{NAND_MFR_TOSHIBA, __NANDSTR("Toshiba")},
|
||||
{NAND_MFR_SAMSUNG, __NANDSTR("Samsung")},
|
||||
{NAND_MFR_FUJITSU, __NANDSTR("Fujitsu")},
|
||||
{NAND_MFR_NATIONAL, __NANDSTR("National")},
|
||||
{NAND_MFR_RENESAS, __NANDSTR("Renesas")},
|
||||
{NAND_MFR_STMICRO, __NANDSTR("ST Micro")},
|
||||
{NAND_MFR_HYNIX, __NANDSTR("Hynix")},
|
||||
{NAND_MFR_MICRON, __NANDSTR("Micron")},
|
||||
{NAND_MFR_AMD, __NANDSTR("AMD/Spansion")},
|
||||
{NAND_MFR_MACRONIX, __NANDSTR("Macronix")},
|
||||
{NAND_MFR_EON, __NANDSTR("Eon")},
|
||||
{NAND_MFR_TOSHIBA, "Toshiba"},
|
||||
{NAND_MFR_SAMSUNG, "Samsung"},
|
||||
{NAND_MFR_FUJITSU, "Fujitsu"},
|
||||
{NAND_MFR_NATIONAL, "National"},
|
||||
{NAND_MFR_RENESAS, "Renesas"},
|
||||
{NAND_MFR_STMICRO, "ST Micro"},
|
||||
{NAND_MFR_HYNIX, "Hynix"},
|
||||
{NAND_MFR_MICRON, "Micron"},
|
||||
{NAND_MFR_AMD, "AMD/Spansion"},
|
||||
{NAND_MFR_MACRONIX, "Macronix"},
|
||||
{NAND_MFR_EON, "Eon"},
|
||||
{0x0, "Unknown"}
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -686,23 +686,6 @@ static void copy_spare(struct mtd_info *mtd, int bfrom)
|
|||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is used by the upper layer to verify the data in NAND Flash
|
||||
* with the data in the \b buf.
|
||||
*
|
||||
* @param mtd MTD structure for the NAND Flash
|
||||
* @param buf data to be verified
|
||||
* @param len length of the data to be verified
|
||||
*
|
||||
* @return -EFAULT if error else 0
|
||||
*
|
||||
*/
|
||||
static int
|
||||
imx_nand_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is used by upper layer for select and deselect of the NAND
|
||||
* chip
|
||||
|
|
@ -1235,7 +1218,6 @@ static int __init imxnd_probe(struct device_d *dev)
|
|||
this->read_word = imx_nand_read_word;
|
||||
this->write_buf = imx_nand_write_buf;
|
||||
this->read_buf = imx_nand_read_buf;
|
||||
this->verify_buf = imx_nand_verify_buf;
|
||||
|
||||
if (host->hw_ecc) {
|
||||
this->ecc.calculate = imx_nand_calculate_ecc;
|
||||
|
|
@ -1268,7 +1250,7 @@ static int __init imxnd_probe(struct device_d *dev)
|
|||
}
|
||||
|
||||
/* first scan to find the device and get the page size */
|
||||
if (nand_scan_ident(mtd, 1)) {
|
||||
if (nand_scan_ident(mtd, 1, NULL)) {
|
||||
err = -ENXIO;
|
||||
goto escan;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -620,7 +620,7 @@ static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
|
|||
* Read a page from NAND.
|
||||
*/
|
||||
static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
|
||||
uint8_t *buf)
|
||||
uint8_t *buf, int oob_required, int page)
|
||||
{
|
||||
struct mxs_nand_info *nand_info = nand->priv;
|
||||
struct mxs_dma_desc *d;
|
||||
|
|
@ -762,13 +762,14 @@ rtn:
|
|||
/*
|
||||
* Write a page to NAND.
|
||||
*/
|
||||
static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
|
||||
struct nand_chip *nand, const uint8_t *buf)
|
||||
static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
|
||||
struct nand_chip *nand, const uint8_t *buf,
|
||||
int oob_required)
|
||||
{
|
||||
struct mxs_nand_info *nand_info = nand->priv;
|
||||
struct mxs_dma_desc *d;
|
||||
uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
|
||||
int ret;
|
||||
int ret = 0;
|
||||
|
||||
memcpy(nand_info->data_buf, buf, mtd->writesize);
|
||||
memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
|
||||
|
|
@ -816,6 +817,8 @@ static void mxs_nand_ecc_write_page(struct mtd_info *mtd,
|
|||
|
||||
rtn:
|
||||
mxs_nand_return_dma_descs(nand_info);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -934,7 +937,7 @@ static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
|||
* what to do.
|
||||
*/
|
||||
static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
|
||||
int page, int cmd)
|
||||
int page)
|
||||
{
|
||||
struct mxs_nand_info *nand_info = nand->priv;
|
||||
int column;
|
||||
|
|
@ -1249,7 +1252,7 @@ static int mxs_nand_probe(struct device_d *dev)
|
|||
nand->ecc.strength = 8;
|
||||
|
||||
/* first scan to find the device and get the page size */
|
||||
err = nand_scan_ident(mtd, 1);
|
||||
err = nand_scan_ident(mtd, 1, NULL);
|
||||
if (err)
|
||||
goto err2;
|
||||
|
||||
|
|
|
|||
|
|
@ -697,7 +697,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
|
|||
* generate dummy eccs for the unprotected oob area.
|
||||
*/
|
||||
static int omap_gpmc_read_page_bch_rom_mode(struct mtd_info *mtd,
|
||||
struct nand_chip *chip, uint8_t *buf)
|
||||
struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
|
||||
{
|
||||
struct gpmc_nand_info *oinfo = chip->priv;
|
||||
int dev_width = chip->options & NAND_BUSWIDTH_16 ? GPMC_ECC_CONFIG_ECC16B : 0;
|
||||
|
|
@ -886,7 +886,7 @@ static int omap_gpmc_eccmode_set(struct device_d *dev, struct param_d *param, co
|
|||
return omap_gpmc_eccmode(oinfo, i);
|
||||
}
|
||||
|
||||
static int gpmc_set_buswidth(struct mtd_info *mtd, struct nand_chip *chip, int buswidth)
|
||||
static int gpmc_set_buswidth(struct nand_chip *chip, int buswidth)
|
||||
{
|
||||
struct gpmc_nand_info *oinfo = chip->priv;
|
||||
|
||||
|
|
@ -1007,8 +1007,6 @@ static int gpmc_nand_probe(struct device_d *pdev)
|
|||
nand->options |= NAND_OWN_BUFFERS;
|
||||
nand->buffers = xzalloc(sizeof(*nand->buffers));
|
||||
|
||||
nand->set_buswidth = gpmc_set_buswidth;
|
||||
|
||||
/* State my controller */
|
||||
nand->controller = &oinfo->controller;
|
||||
|
||||
|
|
@ -1031,11 +1029,13 @@ static int gpmc_nand_probe(struct device_d *pdev)
|
|||
mdelay(1);
|
||||
|
||||
/* first scan to find the device and get the page size */
|
||||
if (nand_scan_ident(minfo, 1)) {
|
||||
if (nand_scan_ident(minfo, 1, NULL)) {
|
||||
err = -ENXIO;
|
||||
goto out_release_mem;
|
||||
}
|
||||
|
||||
gpmc_set_buswidth(nand, nand->options & NAND_BUSWIDTH_16);
|
||||
|
||||
if (nand->options & NAND_BUSWIDTH_16) {
|
||||
lsp = &ecc_sp_x16;
|
||||
llp = &ecc_lp_x16;
|
||||
|
|
|
|||
|
|
@ -1,95 +0,0 @@
|
|||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <clock.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <io.h>
|
||||
#include <malloc.h>
|
||||
|
||||
#include "nand.h"
|
||||
|
||||
/**
|
||||
* nand_read_page_swecc - [REPLACABLE] software ecc based page read function
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: buffer to store read data
|
||||
*/
|
||||
static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *p = buf;
|
||||
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
||||
uint8_t *ecc_code = chip->buffers->ecccode;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
|
||||
chip->ecc.read_page_raw(mtd, chip, buf);
|
||||
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
|
||||
for (i = 0; i < chip->ecc.total; i++)
|
||||
ecc_code[i] = chip->oob_poi[eccpos[i]];
|
||||
|
||||
eccsteps = chip->ecc.steps;
|
||||
p = buf;
|
||||
|
||||
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
int stat;
|
||||
|
||||
stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
|
||||
if (stat < 0)
|
||||
mtd->ecc_stats.failed++;
|
||||
else
|
||||
mtd->ecc_stats.corrected += stat;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_page_swecc - [REPLACABLE] software ecc based page write function
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: data buffer
|
||||
*/
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf)
|
||||
{
|
||||
int i, eccsize = chip->ecc.size;
|
||||
int eccbytes = chip->ecc.bytes;
|
||||
int eccsteps = chip->ecc.steps;
|
||||
uint8_t *ecc_calc = chip->buffers->ecccalc;
|
||||
const uint8_t *p = buf;
|
||||
uint32_t *eccpos = chip->ecc.layout->eccpos;
|
||||
|
||||
/* Software ecc calculation */
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
|
||||
chip->ecc.calculate(mtd, p, &ecc_calc[i]);
|
||||
|
||||
for (i = 0; i < chip->ecc.total; i++)
|
||||
chip->oob_poi[eccpos[i]] = ecc_calc[i];
|
||||
|
||||
chip->ecc.write_page_raw(mtd, chip, buf);
|
||||
}
|
||||
#endif
|
||||
|
||||
void nand_init_ecc_soft(struct nand_chip *chip)
|
||||
{
|
||||
chip->ecc.calculate = nand_calculate_ecc;
|
||||
chip->ecc.correct = nand_correct_data;
|
||||
chip->ecc.read_page = nand_read_page_swecc;
|
||||
chip->ecc.read_oob = nand_read_oob_std;
|
||||
#ifdef CONFIG_MTD_WRITE
|
||||
chip->ecc.write_page = nand_write_page_swecc;
|
||||
chip->ecc.write_oob = nand_write_oob_std;
|
||||
#endif
|
||||
chip->ecc.size = 256;
|
||||
chip->ecc.bytes = 3;
|
||||
chip->ecc.strength = 1;
|
||||
}
|
||||
|
|
@ -1,788 +0,0 @@
|
|||
#define pr_fmt(fmt) "nand: " fmt
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <clock.h>
|
||||
#include <linux/mtd/mtd.h>
|
||||
#include <linux/mtd/nand.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <io.h>
|
||||
#include <malloc.h>
|
||||
#include <module.h>
|
||||
|
||||
#include "nand.h"
|
||||
|
||||
static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
|
||||
struct mtd_oob_ops *ops);
|
||||
|
||||
/**
|
||||
* nand_write_buf - [DEFAULT] write buffer to chip
|
||||
* @mtd: MTD device structure
|
||||
* @buf: data buffer
|
||||
* @len: number of bytes to write
|
||||
*
|
||||
* Default write function for 8bit buswith
|
||||
*/
|
||||
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
|
||||
{
|
||||
int i;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
writeb(buf[i], chip->IO_ADDR_W);
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_buf16 - [DEFAULT] write buffer to chip
|
||||
* @mtd: MTD device structure
|
||||
* @buf: data buffer
|
||||
* @len: number of bytes to write
|
||||
*
|
||||
* Default write function for 16bit buswith
|
||||
*/
|
||||
void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
|
||||
{
|
||||
int i;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
u16 *p = (u16 *) buf;
|
||||
len >>= 1;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
writew(p[i], chip->IO_ADDR_W);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_default_block_markbad - [DEFAULT] mark a block bad
|
||||
* @mtd: MTD device structure
|
||||
* @ofs: offset from device start
|
||||
*
|
||||
* This is the default implementation, which can be overridden by a hardware
|
||||
* specific driver. We try operations in the following order, according to our
|
||||
* bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
|
||||
* (1) erase the affected block, to allow OOB marker to be written cleanly
|
||||
* (2) update in-memory BBT
|
||||
* (3) write bad block marker to OOB area of affected block
|
||||
* (4) update flash-based BBT
|
||||
* Note that we retain the first error encountered in (3) or (4), finish the
|
||||
* procedures, and dump the error in the end.
|
||||
*/
|
||||
int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
uint8_t buf[2] = { 0, 0 };
|
||||
int block, res, ret = 0, i = 0;
|
||||
int write_oob = 1; /* Currently we do not have NAND_BBT_NO_OOB_BBM */
|
||||
|
||||
if (write_oob) {
|
||||
struct erase_info einfo;
|
||||
|
||||
/* Attempt erase before marking OOB */
|
||||
memset(&einfo, 0, sizeof(einfo));
|
||||
einfo.mtd = mtd;
|
||||
einfo.addr = ofs;
|
||||
einfo.len = 1 << chip->phys_erase_shift;
|
||||
nand_erase_nand(mtd, &einfo, 0);
|
||||
}
|
||||
|
||||
/* Get block number */
|
||||
block = (int)(ofs >> chip->bbt_erase_shift);
|
||||
/* Mark block bad in memory-based BBT */
|
||||
if (chip->bbt)
|
||||
chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
|
||||
|
||||
/* Write bad block marker to OOB */
|
||||
if (write_oob) {
|
||||
struct mtd_oob_ops ops;
|
||||
loff_t wr_ofs = ofs;
|
||||
|
||||
ops.datbuf = NULL;
|
||||
ops.oobbuf = buf;
|
||||
ops.ooboffs = chip->badblockpos;
|
||||
if (chip->options & NAND_BUSWIDTH_16) {
|
||||
ops.ooboffs &= ~0x01;
|
||||
ops.len = ops.ooblen = 2;
|
||||
} else {
|
||||
ops.len = ops.ooblen = 1;
|
||||
}
|
||||
ops.mode = MTD_OPS_PLACE_OOB;
|
||||
|
||||
/* Write to first/last page(s) if necessary */
|
||||
if (chip->options & NAND_BBT_LASTBLOCK)
|
||||
wr_ofs += mtd->erasesize - mtd->writesize;
|
||||
do {
|
||||
res = nand_do_write_oob(mtd, wr_ofs, &ops);
|
||||
if (!ret)
|
||||
ret = res;
|
||||
|
||||
i++;
|
||||
wr_ofs += mtd->writesize;
|
||||
} while ((chip->options & NAND_BBT_SCAN2NDPAGE) && i < 2);
|
||||
}
|
||||
|
||||
/* Update flash-based bad block table */
|
||||
if (chip->options & NAND_BBT_USE_FLASH) {
|
||||
res = nand_update_bbt(mtd, ofs);
|
||||
if (!ret)
|
||||
ret = res;
|
||||
}
|
||||
|
||||
if (!ret)
|
||||
mtd->ecc_stats.badblocks++;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_check_wp - [GENERIC] check if the chip is write protected
|
||||
* @mtd: MTD device structure
|
||||
* Check, if the device is write protected
|
||||
*
|
||||
* The function expects, that the device is already selected
|
||||
*/
|
||||
static int nand_check_wp(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
/* Check the WP bit */
|
||||
chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
|
||||
return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_oob_std - [REPLACABLE] the most common OOB data write function
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @page: page number to write
|
||||
*/
|
||||
int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page)
|
||||
{
|
||||
int status = 0;
|
||||
const uint8_t *buf = chip->oob_poi;
|
||||
int length = mtd->oobsize;
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
|
||||
chip->write_buf(mtd, buf, length);
|
||||
/* Send command to program the OOB data */
|
||||
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
|
||||
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
|
||||
return status & NAND_STATUS_FAIL ? -EIO : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_page_raw - [Intern] raw page write function
|
||||
* @mtd: mtd info structure
|
||||
* @chip: nand chip info structure
|
||||
* @buf: data buffer
|
||||
*/
|
||||
void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf)
|
||||
{
|
||||
chip->write_buf(mtd, buf, mtd->writesize);
|
||||
chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_page - [REPLACEABLE] write one page
|
||||
* @mtd: MTD device structure
|
||||
* @chip: NAND chip descriptor
|
||||
* @buf: the data to write
|
||||
* @page: page number to write
|
||||
* @cached: cached programming
|
||||
* @raw: use _raw version of write_page
|
||||
*/
|
||||
int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw)
|
||||
{
|
||||
int status;
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
|
||||
|
||||
if (unlikely(raw))
|
||||
chip->ecc.write_page_raw(mtd, chip, buf);
|
||||
else
|
||||
chip->ecc.write_page(mtd, chip, buf);
|
||||
|
||||
/*
|
||||
* Cached progamming disabled for now, Not sure if its worth the
|
||||
* trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
|
||||
*/
|
||||
cached = 0;
|
||||
|
||||
if (!cached || !(chip->options & NAND_CACHEPRG)) {
|
||||
|
||||
chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
/*
|
||||
* See if operation failed and additional status checks are
|
||||
* available
|
||||
*/
|
||||
if ((status & NAND_STATUS_FAIL) && (chip->errstat))
|
||||
status = chip->errstat(mtd, chip, FL_WRITING, status,
|
||||
page);
|
||||
|
||||
if (status & NAND_STATUS_FAIL) {
|
||||
return -EIO;
|
||||
}
|
||||
} else {
|
||||
chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
/* Send command to read back the data */
|
||||
chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
|
||||
|
||||
if (chip->verify_buf(mtd, buf, mtd->writesize))
|
||||
return -EIO;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_fill_oob - [Internal] Transfer client buffer to oob
|
||||
* @chip: nand chip structure
|
||||
* @oob: oob data buffer
|
||||
* @ops: oob ops structure
|
||||
*/
|
||||
static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
|
||||
struct mtd_oob_ops *ops)
|
||||
{
|
||||
size_t len = ops->ooblen;
|
||||
|
||||
switch(ops->mode) {
|
||||
|
||||
case MTD_OPS_PLACE_OOB:
|
||||
case MTD_OPS_RAW:
|
||||
memcpy(chip->oob_poi + ops->ooboffs, oob, len);
|
||||
return oob + len;
|
||||
|
||||
case MTD_OPS_AUTO_OOB: {
|
||||
struct nand_oobfree *free = chip->ecc.layout->oobfree;
|
||||
uint32_t boffs = 0, woffs = ops->ooboffs;
|
||||
size_t bytes = 0;
|
||||
|
||||
for(; free->length && len; free++, len -= bytes) {
|
||||
/* Write request not from offset 0 ? */
|
||||
if (unlikely(woffs)) {
|
||||
if (woffs >= free->length) {
|
||||
woffs -= free->length;
|
||||
continue;
|
||||
}
|
||||
boffs = free->offset + woffs;
|
||||
bytes = min_t(size_t, len,
|
||||
(free->length - woffs));
|
||||
woffs = 0;
|
||||
} else {
|
||||
bytes = min_t(size_t, len, free->length);
|
||||
boffs = free->offset;
|
||||
}
|
||||
memcpy(chip->oob_poi + boffs, oob, bytes);
|
||||
oob += bytes;
|
||||
}
|
||||
return oob;
|
||||
}
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
|
||||
|
||||
/**
|
||||
* nand_do_write_ops - [Internal] NAND write with ECC
|
||||
* @mtd: MTD device structure
|
||||
* @to: offset to write to
|
||||
* @ops: oob operations description structure
|
||||
*
|
||||
* NAND write with ECC
|
||||
*/
|
||||
int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
|
||||
struct mtd_oob_ops *ops)
|
||||
{
|
||||
int chipnr, realpage, page, blockmask, column;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
uint32_t writelen = ops->len;
|
||||
uint8_t *oob = ops->oobbuf;
|
||||
uint8_t *buf = ops->datbuf;
|
||||
int ret = 0, subpage;
|
||||
|
||||
ops->retlen = 0;
|
||||
if (!writelen)
|
||||
return 0;
|
||||
|
||||
column = to & (mtd->writesize - 1);
|
||||
subpage = column || (writelen & (mtd->writesize - 1));
|
||||
|
||||
if (subpage && oob)
|
||||
return -EINVAL;
|
||||
|
||||
chipnr = (int)(to >> chip->chip_shift);
|
||||
chip->select_chip(mtd, chipnr);
|
||||
|
||||
/* Check, if it is write protected */
|
||||
if (nand_check_wp(mtd)) {
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
realpage = (int)(to >> chip->page_shift);
|
||||
page = realpage & chip->pagemask;
|
||||
blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
|
||||
|
||||
/* Invalidate the page cache, when we write to the cached page */
|
||||
if (to <= (chip->pagebuf << chip->page_shift) &&
|
||||
(chip->pagebuf << chip->page_shift) < (to + ops->len))
|
||||
chip->pagebuf = -1;
|
||||
|
||||
while(1) {
|
||||
int bytes = mtd->writesize;
|
||||
int cached = writelen > bytes && page != blockmask;
|
||||
uint8_t *wbuf = buf;
|
||||
|
||||
/* Partial page write ? */
|
||||
if (unlikely(column || writelen < (mtd->writesize - 1))) {
|
||||
cached = 0;
|
||||
bytes = min_t(int, bytes - column, (int) writelen);
|
||||
chip->pagebuf = -1;
|
||||
memset(chip->buffers->databuf, 0xff, mtd->writesize);
|
||||
memcpy(&chip->buffers->databuf[column], buf, bytes);
|
||||
wbuf = chip->buffers->databuf;
|
||||
}
|
||||
|
||||
if (unlikely(oob)) {
|
||||
oob = nand_fill_oob(chip, oob, ops);
|
||||
} else {
|
||||
/* We still need to erase leftover OOB data */
|
||||
memset(chip->oob_poi, 0xff, mtd->oobsize);
|
||||
}
|
||||
|
||||
if (oob || !mtd_all_ff(wbuf, mtd->writesize)) {
|
||||
ret = chip->write_page(mtd, chip, wbuf, page, cached,
|
||||
(ops->mode == MTD_OPS_RAW));
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
writelen -= bytes;
|
||||
if (!writelen)
|
||||
break;
|
||||
|
||||
column = 0;
|
||||
buf += bytes;
|
||||
realpage++;
|
||||
|
||||
page = realpage & chip->pagemask;
|
||||
/* Check, if we cross a chip boundary */
|
||||
if (!page) {
|
||||
chipnr++;
|
||||
chip->select_chip(mtd, -1);
|
||||
chip->select_chip(mtd, chipnr);
|
||||
}
|
||||
}
|
||||
|
||||
ops->retlen = ops->len - writelen;
|
||||
if (unlikely(oob))
|
||||
ops->oobretlen = ops->ooblen;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write - [MTD Interface] NAND write with ECC
|
||||
* @mtd: MTD device structure
|
||||
* @to: offset to write to
|
||||
* @len: number of bytes to write
|
||||
* @retlen: pointer to variable to store the number of written bytes
|
||||
* @buf: the data to write
|
||||
*
|
||||
* NAND write with ECC
|
||||
*/
|
||||
int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
|
||||
size_t *retlen, const uint8_t *buf)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
int ret;
|
||||
|
||||
/* Do not allow reads past end of device */
|
||||
if ((to + len) > mtd->size)
|
||||
return -EINVAL;
|
||||
if (!len)
|
||||
return 0;
|
||||
|
||||
chip->ops.len = len;
|
||||
chip->ops.datbuf = (uint8_t *)buf;
|
||||
chip->ops.oobbuf = NULL;
|
||||
|
||||
ret = nand_do_write_ops(mtd, to, &chip->ops);
|
||||
|
||||
*retlen = chip->ops.retlen;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_do_write_oob - [MTD Interface] NAND write out-of-band
|
||||
* @mtd: MTD device structure
|
||||
* @to: offset to write to
|
||||
* @ops: oob operation description structure
|
||||
*
|
||||
* NAND write out-of-band
|
||||
*/
|
||||
static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
|
||||
struct mtd_oob_ops *ops)
|
||||
{
|
||||
int chipnr, page, status, len;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
|
||||
(unsigned int)to, (int)ops->ooblen);
|
||||
|
||||
if (ops->mode == MTD_OPS_AUTO_OOB)
|
||||
len = chip->ecc.layout->oobavail;
|
||||
else
|
||||
len = mtd->oobsize;
|
||||
|
||||
/* Do not allow write past end of page */
|
||||
if ((ops->ooboffs + ops->ooblen) > len) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_write_oob: "
|
||||
"Attempt to write past end of page\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (unlikely(ops->ooboffs >= len)) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
|
||||
"Attempt to start write outside oob\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Do not allow reads past end of device */
|
||||
if (unlikely(to >= mtd->size ||
|
||||
ops->ooboffs + ops->ooblen >
|
||||
((mtd->size >> chip->page_shift) -
|
||||
(to >> chip->page_shift)) * len)) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
|
||||
"Attempt write beyond end of device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
chipnr = (int)(to >> chip->chip_shift);
|
||||
chip->select_chip(mtd, chipnr);
|
||||
|
||||
/* Shift to get page */
|
||||
page = (int)(to >> chip->page_shift);
|
||||
|
||||
/*
|
||||
* Reset the chip. Some chips (like the Toshiba TC5832DC found in one
|
||||
* of my DiskOnChip 2000 test units) will clear the whole data page too
|
||||
* if we don't do this. I have no clue why, but I seem to have 'fixed'
|
||||
* it in the doc2000 driver in August 1999. dwmw2.
|
||||
*/
|
||||
chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
|
||||
|
||||
/* Check, if it is write protected */
|
||||
if (nand_check_wp(mtd))
|
||||
return -EROFS;
|
||||
|
||||
/* Invalidate the page cache, if we write to the cached page */
|
||||
if (page == chip->pagebuf)
|
||||
chip->pagebuf = -1;
|
||||
|
||||
memset(chip->oob_poi, 0xff, mtd->oobsize);
|
||||
nand_fill_oob(chip, ops->oobbuf, ops);
|
||||
status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
|
||||
memset(chip->oob_poi, 0xff, mtd->oobsize);
|
||||
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
ops->oobretlen = ops->ooblen;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
|
||||
* @mtd: MTD device structure
|
||||
* @to: offset to write to
|
||||
* @ops: oob operation description structure
|
||||
*/
|
||||
int nand_write_oob(struct mtd_info *mtd, loff_t to,
|
||||
struct mtd_oob_ops *ops)
|
||||
{
|
||||
int ret = -ENOSYS;
|
||||
|
||||
ops->retlen = 0;
|
||||
|
||||
/* Do not allow writes past end of device */
|
||||
if (ops->datbuf && (to + ops->len) > mtd->size) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_read_oob: "
|
||||
"Attempt read beyond end of device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch(ops->mode) {
|
||||
case MTD_OPS_PLACE_OOB:
|
||||
case MTD_OPS_AUTO_OOB:
|
||||
case MTD_OPS_RAW:
|
||||
break;
|
||||
|
||||
default:
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (!ops->datbuf)
|
||||
ret = nand_do_write_oob(mtd, to, ops);
|
||||
else
|
||||
ret = nand_do_write_ops(mtd, to, ops);
|
||||
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* single_erease_cmd - [GENERIC] NAND standard block erase command function
|
||||
* @mtd: MTD device structure
|
||||
* @page: the page address of the block which will be erased
|
||||
*
|
||||
* Standard erase command for NAND chips
|
||||
*/
|
||||
void single_erase_cmd(struct mtd_info *mtd, int page)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
/* Send commands to erase a block */
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
|
||||
}
|
||||
|
||||
/**
|
||||
* multi_erease_cmd - [GENERIC] AND specific block erase command function
|
||||
* @mtd: MTD device structure
|
||||
* @page: the page address of the block which will be erased
|
||||
*
|
||||
* AND multi block erase command function
|
||||
* Erase 4 consecutive blocks
|
||||
*/
|
||||
void multi_erase_cmd(struct mtd_info *mtd, int page)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
/* Send commands to erase a block */
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
|
||||
chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_erase - [MTD Interface] erase block(s)
|
||||
* @mtd: MTD device structure
|
||||
* @instr: erase instruction
|
||||
*
|
||||
* Erase one ore more blocks
|
||||
*/
|
||||
int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
|
||||
{
|
||||
return nand_erase_nand(mtd, instr, 0);
|
||||
}
|
||||
|
||||
#define BBT_PAGE_MASK 0xffffff3f
|
||||
/**
|
||||
* nand_erase_nand - [Internal] erase block(s)
|
||||
* @mtd: MTD device structure
|
||||
* @instr: erase instruction
|
||||
* @allowbbt: allow erasing the bbt area
|
||||
*
|
||||
* Erase one ore more blocks
|
||||
*/
|
||||
int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
||||
int allowbbt)
|
||||
{
|
||||
int page, len, status, pages_per_block, ret, chipnr;
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
int rewrite_bbt[NAND_MAX_CHIPS]={0};
|
||||
unsigned int bbt_masked_page = 0xffffffff;
|
||||
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
|
||||
(unsigned int)instr->addr, (unsigned int)instr->len);
|
||||
|
||||
/* Start address must align on block boundary */
|
||||
if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Length must align on block boundary */
|
||||
if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
|
||||
"Length not block aligned\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Do not allow erase past end of device */
|
||||
if ((instr->len + instr->addr) > mtd->size) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
|
||||
"Erase past end of device\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
instr->fail_addr = 0xffffffff;
|
||||
|
||||
/* Shift to get first page */
|
||||
page = (int)(instr->addr >> chip->page_shift);
|
||||
chipnr = (int)(instr->addr >> chip->chip_shift);
|
||||
|
||||
/* Calculate pages in each block */
|
||||
pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
|
||||
|
||||
/* Select the NAND device */
|
||||
chip->select_chip(mtd, chipnr);
|
||||
|
||||
/* Check, if it is write protected */
|
||||
if (nand_check_wp(mtd)) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
|
||||
"Device is write protected!!!\n");
|
||||
instr->state = MTD_ERASE_FAILED;
|
||||
goto erase_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* If BBT requires refresh, set the BBT page mask to see if the BBT
|
||||
* should be rewritten. Otherwise the mask is set to 0xffffffff which
|
||||
* can not be matched. This is also done when the bbt is actually
|
||||
* erased to avoid recusrsive updates
|
||||
*/
|
||||
if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
|
||||
bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
|
||||
|
||||
/* Loop through the pages */
|
||||
len = instr->len;
|
||||
|
||||
instr->state = MTD_ERASING;
|
||||
|
||||
while (len) {
|
||||
/*
|
||||
* heck if we have a bad block, we do not erase bad blocks !
|
||||
*/
|
||||
if (!mtd->allow_erasebad &&
|
||||
nand_block_checkbad(mtd, ((loff_t) page) <<
|
||||
chip->page_shift, 0, allowbbt)) {
|
||||
pr_warn("nand_erase: attempt to erase a "
|
||||
"bad block at page 0x%08x\n", page);
|
||||
instr->state = MTD_ERASE_FAILED;
|
||||
goto erase_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* Invalidate the page cache, if we erase the block which
|
||||
* contains the current cached page
|
||||
*/
|
||||
if (page <= chip->pagebuf && chip->pagebuf <
|
||||
(page + pages_per_block))
|
||||
chip->pagebuf = -1;
|
||||
|
||||
chip->erase_cmd(mtd, page & chip->pagemask);
|
||||
|
||||
status = chip->waitfunc(mtd, chip);
|
||||
|
||||
/*
|
||||
* See if operation failed and additional status checks are
|
||||
* available
|
||||
*/
|
||||
if ((status & NAND_STATUS_FAIL) && (chip->errstat))
|
||||
status = chip->errstat(mtd, chip, FL_ERASING,
|
||||
status, page);
|
||||
|
||||
/* See if block erase succeeded */
|
||||
if (status & NAND_STATUS_FAIL) {
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase: "
|
||||
"Failed erase, page 0x%08x\n", page);
|
||||
instr->state = MTD_ERASE_FAILED;
|
||||
instr->fail_addr = (page << chip->page_shift);
|
||||
goto erase_exit;
|
||||
}
|
||||
|
||||
/*
|
||||
* If BBT requires refresh, set the BBT rewrite flag to the
|
||||
* page being erased
|
||||
*/
|
||||
if (bbt_masked_page != 0xffffffff &&
|
||||
(page & BBT_PAGE_MASK) == bbt_masked_page)
|
||||
rewrite_bbt[chipnr] = (page << chip->page_shift);
|
||||
|
||||
/* Increment page address and decrement length */
|
||||
len -= (1 << chip->phys_erase_shift);
|
||||
page += pages_per_block;
|
||||
|
||||
/* Check, if we cross a chip boundary */
|
||||
if (len && !(page & chip->pagemask)) {
|
||||
chipnr++;
|
||||
chip->select_chip(mtd, -1);
|
||||
chip->select_chip(mtd, chipnr);
|
||||
|
||||
/*
|
||||
* If BBT requires refresh and BBT-PERCHIP, set the BBT
|
||||
* page mask to see if this BBT should be rewritten
|
||||
*/
|
||||
if (bbt_masked_page != 0xffffffff &&
|
||||
(chip->bbt_td->options & NAND_BBT_PERCHIP))
|
||||
bbt_masked_page = chip->bbt_td->pages[chipnr] &
|
||||
BBT_PAGE_MASK;
|
||||
}
|
||||
}
|
||||
instr->state = MTD_ERASE_DONE;
|
||||
|
||||
erase_exit:
|
||||
|
||||
ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
|
||||
|
||||
/* Do call back function */
|
||||
if (!ret)
|
||||
mtd_erase_callback(instr);
|
||||
|
||||
/*
|
||||
* If BBT requires refresh and erase was successful, rewrite any
|
||||
* selected bad block tables
|
||||
*/
|
||||
if (bbt_masked_page == 0xffffffff || ret)
|
||||
return ret;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_NAND_BBT))
|
||||
return ret;
|
||||
|
||||
for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
|
||||
if (!rewrite_bbt[chipnr])
|
||||
continue;
|
||||
/* update the BBT for chip */
|
||||
MTD_DEBUG(MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
|
||||
"(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
|
||||
chip->bbt_td->pages[chipnr]);
|
||||
nand_update_bbt(mtd, rewrite_bbt[chipnr]);
|
||||
}
|
||||
|
||||
/* Return more or less happy */
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
|
||||
* @mtd: MTD device structure
|
||||
* @ofs: offset relative to mtd start
|
||||
*/
|
||||
int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
|
||||
{
|
||||
struct nand_chip *chip = mtd->priv;
|
||||
int ret;
|
||||
|
||||
if ((ret = nand_block_isbad(mtd, ofs))) {
|
||||
/* If it was bad already, return success and do nothing. */
|
||||
if (ret > 0)
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return chip->block_markbad(mtd, ofs);
|
||||
}
|
||||
|
|
@ -133,6 +133,8 @@
|
|||
#define ERESTARTNOHAND 514 /* restart if no handler.. */
|
||||
#define ENOIOCTLCMD 515 /* No ioctl command */
|
||||
|
||||
#define _LAST_ERRNO 515
|
||||
#define ENOTSUPP 524 /* Operation is not supported */
|
||||
|
||||
#define _LAST_ERRNO 524
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -103,7 +103,6 @@ struct nand_bbt_descr {
|
|||
#define NAND_BBT_SCAN2NDPAGE 0x00008000
|
||||
/* Search good / bad pattern on the last page of the eraseblock */
|
||||
#define NAND_BBT_SCANLASTPAGE 0x00010000
|
||||
|
||||
/*
|
||||
* Use a flash based bad block table. By default, OOB identifier is saved in
|
||||
* OOB area. This option is passed to the default bad block table function.
|
||||
|
|
@ -130,4 +129,48 @@ struct nand_bbt_descr {
|
|||
/* The maximum number of blocks to scan for a bbt */
|
||||
#define NAND_BBT_SCAN_MAXBLOCKS 4
|
||||
|
||||
/*
|
||||
* Constants for oob configuration
|
||||
*/
|
||||
#define NAND_SMALL_BADBLOCK_POS 5
|
||||
#define NAND_LARGE_BADBLOCK_POS 0
|
||||
#define ONENAND_BADBLOCK_POS 0
|
||||
|
||||
/*
|
||||
* Bad block scanning errors
|
||||
*/
|
||||
#define ONENAND_BBT_READ_ERROR 1
|
||||
#define ONENAND_BBT_READ_ECC_ERROR 2
|
||||
#define ONENAND_BBT_READ_FATAL_ERROR 4
|
||||
|
||||
/**
|
||||
* struct bbm_info - [GENERIC] Bad Block Table data structure
|
||||
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob area
|
||||
* @options: options for this descriptor
|
||||
* @bbt: [INTERN] bad block table pointer
|
||||
* @isbad_bbt: function to determine if a block is bad
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for
|
||||
* initial bad block scan
|
||||
* @priv: [OPTIONAL] pointer to private bbm date
|
||||
*/
|
||||
struct bbm_info {
|
||||
int bbt_erase_shift;
|
||||
int badblockpos;
|
||||
int options;
|
||||
|
||||
uint8_t *bbt;
|
||||
|
||||
int (*isbad_bbt)(struct mtd_info *mtd, loff_t ofs, int allowbbt);
|
||||
|
||||
/* TODO Add more NAND specific fileds */
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/* OneNAND BBT interface */
|
||||
extern int onenand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
|
||||
extern int onenand_default_bbt(struct mtd_info *mtd);
|
||||
|
||||
#endif /* __LINUX_MTD_BBM_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright © 2000 Red Hat UK Limited
|
||||
* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MTD_FLASHCHIP_H__
|
||||
#define __MTD_FLASHCHIP_H__
|
||||
|
||||
typedef enum {
|
||||
FL_READY,
|
||||
FL_STATUS,
|
||||
FL_CFI_QUERY,
|
||||
FL_JEDEC_QUERY,
|
||||
FL_ERASING,
|
||||
FL_ERASE_SUSPENDING,
|
||||
FL_ERASE_SUSPENDED,
|
||||
FL_WRITING,
|
||||
FL_WRITING_TO_BUFFER,
|
||||
FL_OTP_WRITE,
|
||||
FL_WRITE_SUSPENDING,
|
||||
FL_WRITE_SUSPENDED,
|
||||
FL_PM_SUSPENDED,
|
||||
FL_SYNCING,
|
||||
FL_UNLOADING,
|
||||
FL_LOCKING,
|
||||
FL_UNLOCKING,
|
||||
FL_POINT,
|
||||
FL_XIP_WHILE_ERASING,
|
||||
FL_XIP_WHILE_WRITING,
|
||||
FL_SHUTDOWN,
|
||||
/* These 2 come from nand_state_t, which has been unified here */
|
||||
FL_READING,
|
||||
FL_CACHEDPRG,
|
||||
/* These 4 come from onenand_state_t, which has been unified here */
|
||||
FL_RESETING,
|
||||
FL_OTPING,
|
||||
FL_PREPARING_ERASE,
|
||||
FL_VERIFYING_ERASE,
|
||||
|
||||
FL_UNKNOWN
|
||||
} flstate_t;
|
||||
|
||||
|
||||
|
||||
/* NOTE: confusingly, this can be used to refer to more than one chip at a time,
|
||||
if they're interleaved. This can even refer to individual partitions on
|
||||
the same physical chip when present. */
|
||||
|
||||
struct flchip {
|
||||
unsigned long start; /* Offset within the map */
|
||||
// unsigned long len;
|
||||
/* We omit len for now, because when we group them together
|
||||
we insist that they're all of the same size, and the chip size
|
||||
is held in the next level up. If we get more versatile later,
|
||||
it'll make it a damn sight harder to find which chip we want from
|
||||
a given offset, and we'll want to add the per-chip length field
|
||||
back in.
|
||||
*/
|
||||
int ref_point_counter;
|
||||
flstate_t state;
|
||||
flstate_t oldstate;
|
||||
|
||||
unsigned int write_suspended:1;
|
||||
unsigned int erase_suspended:1;
|
||||
unsigned long in_progress_block_addr;
|
||||
|
||||
int word_write_time;
|
||||
int buffer_write_time;
|
||||
int erase_time;
|
||||
|
||||
int word_write_time_max;
|
||||
int buffer_write_time_max;
|
||||
int erase_time_max;
|
||||
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/* This is used to handle contention on write/erase operations
|
||||
between partitions of the same physical chip. */
|
||||
struct flchip_shared {
|
||||
struct flchip *writing;
|
||||
struct flchip *erasing;
|
||||
};
|
||||
|
||||
|
||||
#endif /* __MTD_FLASHCHIP_H__ */
|
||||
|
|
@ -101,6 +101,17 @@ struct mtd_info {
|
|||
*/
|
||||
u_int32_t writesize;
|
||||
|
||||
/*
|
||||
* Size of the write buffer used by the MTD. MTD devices having a write
|
||||
* buffer can write multiple writesize chunks at a time. E.g. while
|
||||
* writing 4 * writesize bytes to a device with 2 * writesize bytes
|
||||
* buffer the MTD driver can (but doesn't have to) do 2 writesize
|
||||
* operations, but not 4. Currently, all NANDs have writebufsize
|
||||
* equivalent to writesize (NAND page size). Some NOR flashes do have
|
||||
* writebufsize greater than writesize.
|
||||
*/
|
||||
uint32_t writebufsize;
|
||||
|
||||
u_int32_t oobsize; // Amount of OOB data per block (e.g. 16)
|
||||
u_int32_t oobavail; // Available OOB bytes per block
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,9 @@
|
|||
/*
|
||||
* linux/include/linux/mtd/nand.h
|
||||
*
|
||||
* Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org>
|
||||
* Steven J. Hill <sjhill@realitydiluted.com>
|
||||
* Thomas Gleixner <tglx@linutronix.de>
|
||||
*
|
||||
* $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
|
||||
* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
|
||||
* Steven J. Hill <sjhill@realitydiluted.com>
|
||||
* Thomas Gleixner <tglx@linutronix.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -20,34 +18,43 @@
|
|||
#ifndef __LINUX_MTD_NAND_H
|
||||
#define __LINUX_MTD_NAND_H
|
||||
|
||||
#ifndef DOXYGEN_SHOULD_SKIP_THIS
|
||||
|
||||
#include <linux/mtd/mtd.h>
|
||||
|
||||
/* The maximum number of NAND chips in an array */
|
||||
#define NAND_MAX_CHIPS 8
|
||||
|
||||
#include <linux/mtd/flashchip.h>
|
||||
#include <linux/mtd/bbm.h>
|
||||
|
||||
struct mtd_info;
|
||||
struct nand_flash_dev;
|
||||
/* Scan and identify a NAND device */
|
||||
extern int nand_scan (struct mtd_info *mtd, int max_chips);
|
||||
/* Separate phases of nand_scan(), allowing board driver to intervene
|
||||
* and override command or ECC setup according to flash type */
|
||||
extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
|
||||
extern int nand_scan(struct mtd_info *mtd, int max_chips);
|
||||
/*
|
||||
* Separate phases of nand_scan(), allowing board driver to intervene
|
||||
* and override command or ECC setup according to flash type.
|
||||
*/
|
||||
extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
|
||||
struct nand_flash_dev *table);
|
||||
extern int nand_scan_tail(struct mtd_info *mtd);
|
||||
|
||||
/* Free resources held by the NAND device */
|
||||
extern void nand_release (struct mtd_info *mtd);
|
||||
extern void nand_release(struct mtd_info *mtd);
|
||||
|
||||
/* Internal helper for board drivers which need to override command function */
|
||||
extern void nand_wait_ready(struct mtd_info *mtd);
|
||||
|
||||
/* This constant declares the max. oobsize / page, which
|
||||
/* locks all blocks present in the device */
|
||||
extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
|
||||
|
||||
/* unlocks specified locked blocks */
|
||||
extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
|
||||
|
||||
/* The maximum number of NAND chips in an array */
|
||||
#define NAND_MAX_CHIPS 8
|
||||
|
||||
/*
|
||||
* This constant declares the max. oobsize / page, which
|
||||
* is supported now. If you add a chip with bigger oobsize/page
|
||||
* adjust this accordingly.
|
||||
*/
|
||||
#define NAND_MAX_OOBSIZE 576
|
||||
#define NAND_MAX_OOBSIZE 640
|
||||
#define NAND_MAX_PAGESIZE 8192
|
||||
|
||||
/*
|
||||
|
|
@ -77,38 +84,24 @@ extern void nand_wait_ready(struct mtd_info *mtd);
|
|||
#define NAND_CMD_READOOB 0x50
|
||||
#define NAND_CMD_ERASE1 0x60
|
||||
#define NAND_CMD_STATUS 0x70
|
||||
#define NAND_CMD_STATUS_MULTI 0x71
|
||||
#define NAND_CMD_SEQIN 0x80
|
||||
#define NAND_CMD_RNDIN 0x85
|
||||
#define NAND_CMD_READID 0x90
|
||||
#define NAND_CMD_ERASE2 0xd0
|
||||
#define NAND_CMD_PARAM 0xec
|
||||
#define NAND_CMD_GET_FEATURES 0xee
|
||||
#define NAND_CMD_SET_FEATURES 0xef
|
||||
#define NAND_CMD_RESET 0xff
|
||||
|
||||
#define NAND_CMD_LOCK 0x2a
|
||||
#define NAND_CMD_UNLOCK1 0x23
|
||||
#define NAND_CMD_UNLOCK2 0x24
|
||||
|
||||
/* Extended commands for large page devices */
|
||||
#define NAND_CMD_READSTART 0x30
|
||||
#define NAND_CMD_RNDOUTSTART 0xE0
|
||||
#define NAND_CMD_CACHEDPROG 0x15
|
||||
|
||||
/* Extended commands for AG-AND device */
|
||||
/*
|
||||
* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
|
||||
* there is no way to distinguish that from NAND_CMD_READ0
|
||||
* until the remaining sequence of commands has been completed
|
||||
* so add a high order bit and mask it off in the command.
|
||||
*/
|
||||
#define NAND_CMD_DEPLETE1 0x100
|
||||
#define NAND_CMD_DEPLETE2 0x38
|
||||
#define NAND_CMD_STATUS_MULTI 0x71
|
||||
#define NAND_CMD_STATUS_ERROR 0x72
|
||||
/* multi-bank error status (banks 0-3) */
|
||||
#define NAND_CMD_STATUS_ERROR0 0x73
|
||||
#define NAND_CMD_STATUS_ERROR1 0x74
|
||||
#define NAND_CMD_STATUS_ERROR2 0x75
|
||||
#define NAND_CMD_STATUS_ERROR3 0x76
|
||||
#define NAND_CMD_STATUS_RESET 0x7f
|
||||
#define NAND_CMD_STATUS_CLEAR 0xff
|
||||
|
||||
#define NAND_CMD_NONE -1
|
||||
|
||||
/* Status bits */
|
||||
|
|
@ -126,6 +119,8 @@ typedef enum {
|
|||
NAND_ECC_SOFT,
|
||||
NAND_ECC_HW,
|
||||
NAND_ECC_HW_SYNDROME,
|
||||
NAND_ECC_HW_OOB_FIRST,
|
||||
NAND_ECC_SOFT_BCH,
|
||||
} nand_ecc_modes_t;
|
||||
|
||||
/*
|
||||
|
|
@ -135,65 +130,65 @@ typedef enum {
|
|||
#define NAND_ECC_READ 0
|
||||
/* Reset Hardware ECC for write */
|
||||
#define NAND_ECC_WRITE 1
|
||||
/* Enable Hardware ECC before syndrom is read back from flash */
|
||||
/* Enable Hardware ECC before syndrome is read back from flash */
|
||||
#define NAND_ECC_READSYN 2
|
||||
|
||||
/* Bit mask for flags passed to do_nand_read_ecc */
|
||||
#define NAND_GET_DEVICE 0x80
|
||||
|
||||
|
||||
/* Option constants for bizarre disfunctionality and real
|
||||
* features
|
||||
*/
|
||||
/* Chip can not auto increment pages */
|
||||
#define NAND_NO_AUTOINCR 0x00000001
|
||||
/* Buswitdh is 16 bit */
|
||||
/*
|
||||
* Option constants for bizarre disfunctionality and real
|
||||
* features.
|
||||
*/
|
||||
/* Buswidth is 16 bit */
|
||||
#define NAND_BUSWIDTH_16 0x00000002
|
||||
/* Device supports partial programming without padding */
|
||||
#define NAND_NO_PADDING 0x00000004
|
||||
/* Chip has cache program function */
|
||||
#define NAND_CACHEPRG 0x00000008
|
||||
/* Chip has copy back function */
|
||||
#define NAND_COPYBACK 0x00000010
|
||||
/* AND Chip which has 4 banks and a confusing page / block
|
||||
* assignment. See Renesas datasheet for further information */
|
||||
#define NAND_IS_AND 0x00000020
|
||||
/* Chip has a array of 4 pages which can be read without
|
||||
* additional ready /busy waits */
|
||||
#define NAND_4PAGE_ARRAY 0x00000040
|
||||
/* Chip requires that BBT is periodically rewritten to prevent
|
||||
* bits from adjacent blocks from 'leaking' in altering data.
|
||||
* This happens with the Renesas AG-AND chips, possibly others. */
|
||||
#define BBT_AUTO_REFRESH 0x00000080
|
||||
/* Chip does not require ready check on read. True
|
||||
* for all large page devices, as they do not support
|
||||
* autoincrement.*/
|
||||
#define NAND_NO_READRDY 0x00000100
|
||||
/*
|
||||
* Chip requires ready check on read (for auto-incremented sequential read).
|
||||
* True only for small page devices; large page devices do not support
|
||||
* autoincrement.
|
||||
*/
|
||||
#define NAND_NEED_READRDY 0x00000100
|
||||
|
||||
/* Chip does not allow subpage writes */
|
||||
#define NAND_NO_SUBPAGE_WRITE 0x00000200
|
||||
/* Buswitdh shal be autodetected */
|
||||
#define NAND_BUSWIDTH_AUTO 0x00080000
|
||||
|
||||
/* Device is one of 'new' xD cards that expose fake nand command set */
|
||||
#define NAND_BROKEN_XD 0x00000400
|
||||
|
||||
/* Device behaves just like nand, but is readonly */
|
||||
#define NAND_ROM 0x00000800
|
||||
|
||||
/* Device supports subpage reads */
|
||||
#define NAND_SUBPAGE_READ 0x00001000
|
||||
|
||||
/* Options valid for Samsung large page devices */
|
||||
#define NAND_SAMSUNG_LP_OPTIONS \
|
||||
(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
|
||||
#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
|
||||
|
||||
/* Macros to identify the above */
|
||||
#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
|
||||
#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
|
||||
#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
|
||||
#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
|
||||
|
||||
/* Mask to zero out the chip options, which come from the id table */
|
||||
#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
|
||||
#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
|
||||
|
||||
/* Non chip related options */
|
||||
/* This option skips the bbt scan during initialization. */
|
||||
#define NAND_SKIP_BBTSCAN 0x00020000
|
||||
/* This option is defined if the board driver allocates its own buffers
|
||||
(e.g. because it needs them DMA-coherent */
|
||||
#define NAND_OWN_BUFFERS 0x00040000
|
||||
#define NAND_SKIP_BBTSCAN 0x00010000
|
||||
/*
|
||||
* This option is defined if the board driver allocates its own buffers
|
||||
* (e.g. because it needs them DMA-coherent).
|
||||
*/
|
||||
#define NAND_OWN_BUFFERS 0x00020000
|
||||
/* Chip may not exist, so silence any errors in scan */
|
||||
#define NAND_SCAN_SILENT_NODEV 0x00040000
|
||||
/*
|
||||
* Autodetect nand buswidth with readid/onfi.
|
||||
* This suppose the driver will configure the hardware in 8 bits mode
|
||||
* when calling nand_scan_ident, and update its configuration
|
||||
* before calling nand_scan_tail.
|
||||
*/
|
||||
#define NAND_BUSWIDTH_AUTO 0x00080000
|
||||
|
||||
/* Options set by nand scan */
|
||||
/* Nand scan has allocated controller struct */
|
||||
#define NAND_CONTROLLER_ALLOC 0x80000000
|
||||
|
|
@ -202,23 +197,24 @@ typedef enum {
|
|||
#define NAND_CI_CHIPNR_MSK 0x03
|
||||
#define NAND_CI_CELLTYPE_MSK 0x0C
|
||||
|
||||
/*
|
||||
* nand_state_t - chip states
|
||||
* Enumeration for NAND flash chip state
|
||||
*/
|
||||
typedef enum {
|
||||
FL_READY,
|
||||
FL_READING,
|
||||
FL_WRITING,
|
||||
FL_ERASING,
|
||||
FL_SYNCING,
|
||||
FL_CACHEDPRG,
|
||||
FL_PM_SUSPENDED,
|
||||
} nand_state_t;
|
||||
|
||||
/* Keep gcc happy */
|
||||
struct nand_chip;
|
||||
|
||||
/* ONFI timing mode, used in both asynchronous and synchronous mode */
|
||||
#define ONFI_TIMING_MODE_0 (1 << 0)
|
||||
#define ONFI_TIMING_MODE_1 (1 << 1)
|
||||
#define ONFI_TIMING_MODE_2 (1 << 2)
|
||||
#define ONFI_TIMING_MODE_3 (1 << 3)
|
||||
#define ONFI_TIMING_MODE_4 (1 << 4)
|
||||
#define ONFI_TIMING_MODE_5 (1 << 5)
|
||||
#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
|
||||
|
||||
/* ONFI feature address */
|
||||
#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
|
||||
|
||||
/* ONFI subfeature parameters length */
|
||||
#define ONFI_SUBFEATURE_PARAM_LEN 4
|
||||
|
||||
struct nand_onfi_params {
|
||||
/* rev info and features block */
|
||||
/* 'O' 'N' 'F' 'I' */
|
||||
|
|
@ -287,77 +283,87 @@ struct nand_onfi_params {
|
|||
* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
|
||||
* @lock: protection lock
|
||||
* @active: the mtd device which holds the controller currently
|
||||
* @wq: wait queue to sleep on if a NAND operation is in progress
|
||||
* used instead of the per chip wait queue when a hw controller is available
|
||||
* @wq: wait queue to sleep on if a NAND operation is in
|
||||
* progress used instead of the per chip wait queue
|
||||
* when a hw controller is available.
|
||||
*/
|
||||
struct nand_hw_control {
|
||||
struct nand_chip *active;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nand_ecc_ctrl - Control structure for ecc
|
||||
* @mode: ecc mode
|
||||
* @steps: number of ecc steps per page
|
||||
* @size: data bytes per ecc step
|
||||
* @bytes: ecc bytes per step
|
||||
* struct nand_ecc_ctrl - Control structure for ECC
|
||||
* @mode: ECC mode
|
||||
* @steps: number of ECC steps per page
|
||||
* @size: data bytes per ECC step
|
||||
* @bytes: ECC bytes per step
|
||||
* @strength: max number of correctible bits per ECC step
|
||||
* @total: total number of ecc bytes per page
|
||||
* @prepad: padding information for syndrome based ecc generators
|
||||
* @postpad: padding information for syndrome based ecc generators
|
||||
* @total: total number of ECC bytes per page
|
||||
* @prepad: padding information for syndrome based ECC generators
|
||||
* @postpad: padding information for syndrome based ECC generators
|
||||
* @layout: ECC layout control struct pointer
|
||||
* @hwctl: function to control hardware ecc generator. Must only
|
||||
* @priv: pointer to private ECC control data
|
||||
* @hwctl: function to control hardware ECC generator. Must only
|
||||
* be provided if an hardware ECC is available
|
||||
* @calculate: function for ecc calculation or readback from ecc hardware
|
||||
* @correct: function for ecc correction, matching to ecc generator (sw/hw)
|
||||
* @calculate: function for ECC calculation or readback from ECC hardware
|
||||
* @correct: function for ECC correction, matching to ECC generator (sw/hw)
|
||||
* @read_page_raw: function to read a raw page without ECC
|
||||
* @write_page_raw: function to write a raw page without ECC
|
||||
* @read_page: function to read a page according to the ecc generator requirements
|
||||
* @write_page: function to write a page according to the ecc generator requirements
|
||||
* @read_page: function to read a page according to the ECC generator
|
||||
* requirements; returns maximum number of bitflips corrected in
|
||||
* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
|
||||
* @read_subpage: function to read parts of the page covered by ECC;
|
||||
* returns same as read_page()
|
||||
* @write_subpage: function to write parts of the page covered by ECC.
|
||||
* @write_page: function to write a page according to the ECC generator
|
||||
* requirements.
|
||||
* @write_oob_raw: function to write chip OOB data without ECC
|
||||
* @read_oob_raw: function to read chip OOB data without ECC
|
||||
* @read_oob: function to read chip OOB data
|
||||
* @write_oob: function to write chip OOB data
|
||||
*/
|
||||
struct nand_ecc_ctrl {
|
||||
nand_ecc_modes_t mode;
|
||||
int steps;
|
||||
int size;
|
||||
int bytes;
|
||||
int total;
|
||||
int strength;
|
||||
int prepad;
|
||||
int postpad;
|
||||
nand_ecc_modes_t mode;
|
||||
int steps;
|
||||
int size;
|
||||
int bytes;
|
||||
int total;
|
||||
int strength;
|
||||
int prepad;
|
||||
int postpad;
|
||||
struct nand_ecclayout *layout;
|
||||
void (*hwctl)(struct mtd_info *mtd, int mode);
|
||||
int (*calculate)(struct mtd_info *mtd,
|
||||
const uint8_t *dat,
|
||||
uint8_t *ecc_code);
|
||||
int (*correct)(struct mtd_info *mtd, uint8_t *dat,
|
||||
uint8_t *read_ecc,
|
||||
uint8_t *calc_ecc);
|
||||
int (*read_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf);
|
||||
void (*write_page_raw)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_page)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
uint8_t *buf);
|
||||
void (*write_page)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
const uint8_t *buf);
|
||||
int (*read_oob)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
int page,
|
||||
int sndcmd);
|
||||
int (*write_oob)(struct mtd_info *mtd,
|
||||
struct nand_chip *chip,
|
||||
int page);
|
||||
void *priv;
|
||||
void (*hwctl)(struct mtd_info *mtd, int mode);
|
||||
int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
|
||||
uint8_t *ecc_code);
|
||||
int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
|
||||
uint8_t *calc_ecc);
|
||||
int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf, int oob_required, int page);
|
||||
int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int oob_required);
|
||||
int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint8_t *buf, int oob_required, int page);
|
||||
int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint32_t offs, uint32_t len, uint8_t *buf);
|
||||
int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint32_t offset, uint32_t data_len,
|
||||
const uint8_t *data_buf, int oob_required);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int oob_required);
|
||||
int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page);
|
||||
int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page);
|
||||
int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
|
||||
int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int page);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct nand_buffers - buffer structure for read/write
|
||||
* @ecccalc: buffer for calculated ecc
|
||||
* @ecccode: buffer for ecc read from flash
|
||||
* @ecccalc: buffer for calculated ECC
|
||||
* @ecccode: buffer for ECC read from flash
|
||||
* @databuf: buffer for data - dynamically sized
|
||||
*
|
||||
* Do not change the order of buffers. databuf and oobrbuf must be in
|
||||
|
|
@ -371,168 +377,234 @@ struct nand_buffers {
|
|||
|
||||
/**
|
||||
* struct nand_chip - NAND Private Flash Chip Data
|
||||
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
|
||||
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
|
||||
* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
|
||||
* flash device
|
||||
* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
|
||||
* flash device.
|
||||
* @read_byte: [REPLACEABLE] read one byte from the chip
|
||||
* @read_word: [REPLACEABLE] read one word from the chip
|
||||
* @write_buf: [REPLACEABLE] write data from the buffer to the chip
|
||||
* @read_buf: [REPLACEABLE] read data from the chip into the buffer
|
||||
* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
|
||||
* @select_chip: [REPLACEABLE] select chip nr
|
||||
* @block_bad: [REPLACEABLE] check, if the block is bad
|
||||
* @block_markbad: [REPLACEABLE] mark the block bad
|
||||
* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
|
||||
* ALE/CLE/nCE. Also used to write command and address
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
|
||||
* If set to NULL no access to ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register
|
||||
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
|
||||
* @ecc: [BOARDSPECIFIC] ecc control ctructure
|
||||
* @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
|
||||
* mtd->oobsize, mtd->writesize and so on.
|
||||
* @id_data contains the 8 bytes values of NAND_CMD_READID.
|
||||
* Return with the bus width.
|
||||
* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
|
||||
* device ready/busy line. If set to NULL no access to
|
||||
* ready/busy is available and the ready/busy information
|
||||
* is read from the chip status register.
|
||||
* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
|
||||
* commands to the chip.
|
||||
* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
|
||||
* ready.
|
||||
* @ecc: [BOARDSPECIFIC] ECC control structure
|
||||
* @buffers: buffer structure for read/write
|
||||
* @hwcontrol: platform-specific hardware control structure
|
||||
* @ops: oob operation operands
|
||||
* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
|
||||
* @erase_cmd: [INTERN] erase command write function, selectable due
|
||||
* to AND support.
|
||||
* @scan_bbt: [REPLACEABLE] function to scan bad block table
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
|
||||
* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
|
||||
* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
|
||||
* data from array to read regs (tR).
|
||||
* @state: [INTERN] the current state of the NAND device
|
||||
* @oob_poi: poison value buffer
|
||||
* @page_shift: [INTERN] number of address bits in a page (column address bits)
|
||||
* @oob_poi: "poison value buffer," used for laying out OOB data
|
||||
* before writing
|
||||
* @page_shift: [INTERN] number of address bits in a page (column
|
||||
* address bits).
|
||||
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
||||
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
||||
* @chip_shift: [INTERN] number of address bits in one chip
|
||||
* @datbuf: [INTERN] internal buffer for one page + oob
|
||||
* @oobbuf: [INTERN] oob buffer for one eraseblock
|
||||
* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
|
||||
* @data_poi: [INTERN] pointer to a data buffer
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
|
||||
* special functionality. See the defines for further explanation
|
||||
* @options: [BOARDSPECIFIC] various chip options. They can partly
|
||||
* be set to inform nand_scan about special functionality.
|
||||
* See the defines for further explanation.
|
||||
* @bbt_options: [INTERN] bad block specific options. All options used
|
||||
* here must come from bbm.h. By default, these options
|
||||
* will be copied to the appropriate nand_bbt_descr's.
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob area
|
||||
* @badblockpos: [INTERN] position of the bad block marker in the oob
|
||||
* area.
|
||||
* @badblockbits: [INTERN] minimum number of set bits in a good block's
|
||||
* bad block marker position; i.e., BBM == 11110111b is
|
||||
* not bad when badblockbits == 7
|
||||
* @cellinfo: [INTERN] MLC/multichip data from chip ident
|
||||
* @numchips: [INTERN] number of physical chips
|
||||
* @chipsize: [INTERN] the size of one chip for multichip arrays
|
||||
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
||||
* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
|
||||
* @pagebuf: [INTERN] holds the pagenumber which is currently in
|
||||
* data_buf.
|
||||
* @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
|
||||
* currently in data_buf.
|
||||
* @subpagesize: [INTERN] holds the subpagesize
|
||||
* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
|
||||
* non 0 if ONFI supported.
|
||||
* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
|
||||
* supported, 0 otherwise.
|
||||
* @ecclayout: [REPLACEABLE] the default ecc placement scheme
|
||||
* @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
|
||||
* @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
|
||||
* @ecclayout: [REPLACEABLE] the default ECC placement scheme
|
||||
* @bbt: [INTERN] bad block table pointer
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
|
||||
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
|
||||
* lookup.
|
||||
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller structure
|
||||
* which is shared among multiple independend devices
|
||||
* @priv: [OPTIONAL] pointer to private chip date
|
||||
* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
|
||||
* (determine if errors are correctable)
|
||||
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
|
||||
* bad block scan.
|
||||
* @controller: [REPLACEABLE] a pointer to a hardware controller
|
||||
* structure which is shared among multiple independent
|
||||
* devices.
|
||||
* @priv: [OPTIONAL] pointer to private chip data
|
||||
* @errstat: [OPTIONAL] hardware specific function to perform
|
||||
* additional error status checks (determine if errors are
|
||||
* correctable).
|
||||
* @write_page: [REPLACEABLE] High-level page write function
|
||||
*/
|
||||
|
||||
struct nand_chip {
|
||||
void __iomem *IO_ADDR_R;
|
||||
void __iomem *IO_ADDR_W;
|
||||
|
||||
void __iomem *IO_ADDR_R;
|
||||
void __iomem *IO_ADDR_W;
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
|
||||
u8 *id_data);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
|
||||
int page_addr);
|
||||
int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
|
||||
int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
uint32_t offset, int data_len, const uint8_t *buf,
|
||||
int oob_required, int page, int cached, int raw);
|
||||
int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int feature_addr, uint8_t *subfeature_para);
|
||||
int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
int feature_addr, uint8_t *subfeature_para);
|
||||
|
||||
uint8_t (*read_byte)(struct mtd_info *mtd);
|
||||
u16 (*read_word)(struct mtd_info *mtd);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
||||
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
|
||||
int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
||||
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
||||
int (*scan_bbt)(struct mtd_info *mtd);
|
||||
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
|
||||
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
const uint8_t *buf, int page, int cached, int raw);
|
||||
int (*set_buswidth)(struct mtd_info *mtd, struct nand_chip *this, int buswidth);
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
unsigned int bbt_options;
|
||||
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
unsigned int bbt_options;
|
||||
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int page_shift;
|
||||
int phys_erase_shift;
|
||||
int bbt_erase_shift;
|
||||
int chip_shift;
|
||||
int numchips;
|
||||
uint64_t chipsize;
|
||||
int pagemask;
|
||||
int pagebuf;
|
||||
unsigned int pagebuf_bitflips;
|
||||
int subpagesize;
|
||||
uint8_t cellinfo;
|
||||
int badblockpos;
|
||||
int badblockbits;
|
||||
|
||||
int onfi_version;
|
||||
struct nand_onfi_params onfi_params;
|
||||
struct nand_onfi_params onfi_params;
|
||||
|
||||
nand_state_t state;
|
||||
flstate_t state;
|
||||
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
uint8_t *oob_poi;
|
||||
struct nand_hw_control *controller;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
|
||||
struct nand_ecc_ctrl ecc;
|
||||
struct nand_buffers *buffers;
|
||||
struct nand_hw_control hwcontrol;
|
||||
|
||||
struct mtd_oob_ops ops;
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
|
||||
uint8_t *bbt;
|
||||
struct nand_bbt_descr *bbt_td;
|
||||
struct nand_bbt_descr *bbt_md;
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
|
||||
struct nand_bbt_descr *badblock_pattern;
|
||||
|
||||
void *priv;
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/*
|
||||
* NAND Flash Manufacturer ID Codes
|
||||
*/
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
#define NAND_MFR_FUJITSU 0x04
|
||||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
#define NAND_MFR_AMD 0x01
|
||||
#define NAND_MFR_MACRONIX 0xc2
|
||||
#define NAND_MFR_EON 0x92
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
#define NAND_MFR_FUJITSU 0x04
|
||||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
#define NAND_MFR_AMD 0x01
|
||||
#define NAND_MFR_MACRONIX 0xc2
|
||||
#define NAND_MFR_EON 0x92
|
||||
|
||||
/* The maximum expected count of bytes in the NAND ID sequence */
|
||||
#define NAND_MAX_ID_LEN 8
|
||||
|
||||
/*
|
||||
* A helper for defining older NAND chips where the second ID byte fully
|
||||
* defined the chip, including the geometry (chip size, eraseblock size, page
|
||||
* size). All these chips have 512 bytes NAND page size.
|
||||
*/
|
||||
#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
|
||||
{ .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
|
||||
.chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
|
||||
|
||||
/*
|
||||
* A helper for defining newer chips which report their page size and
|
||||
* eraseblock size via the extended ID bytes.
|
||||
*
|
||||
* The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
|
||||
* EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
|
||||
* device ID now only represented a particular total chip size (and voltage,
|
||||
* buswidth), and the page size, eraseblock size, and OOB size could vary while
|
||||
* using the same device ID.
|
||||
*/
|
||||
#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
|
||||
{ .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
|
||||
.options = (opts) }
|
||||
|
||||
/**
|
||||
* struct nand_flash_dev - NAND Flash Device ID Structure
|
||||
* @name: Identify the device type
|
||||
* @id: device ID code
|
||||
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
|
||||
* If the pagesize is 0, then the real pagesize
|
||||
* and the eraseize are determined from the
|
||||
* extended id bytes in the chip
|
||||
* @erasesize: Size of an erase block in the flash device.
|
||||
* @chipsize: Total chipsize in Mega Bytes
|
||||
* @options: Bitfield to store chip relevant options
|
||||
* @name: a human-readable name of the NAND chip
|
||||
* @dev_id: the device ID (the second byte of the full chip ID array)
|
||||
* @mfr_id: manufecturer ID part of the full chip ID array (refers the same
|
||||
* memory address as @id[0])
|
||||
* @dev_id: device ID part of the full chip ID array (refers the same memory
|
||||
* address as @id[1])
|
||||
* @id: full device ID array
|
||||
* @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
|
||||
* well as the eraseblock size) is determined from the extended NAND
|
||||
* chip ID array)
|
||||
* @chipsize: total chip size in MiB
|
||||
* @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
|
||||
* @options: stores various chip bit options
|
||||
* @id_len: The valid length of the @id.
|
||||
* @oobsize: OOB size
|
||||
*/
|
||||
struct nand_flash_dev {
|
||||
char *name;
|
||||
int id;
|
||||
unsigned long pagesize;
|
||||
unsigned long chipsize;
|
||||
unsigned long erasesize;
|
||||
unsigned long options;
|
||||
union {
|
||||
struct {
|
||||
uint8_t mfr_id;
|
||||
uint8_t dev_id;
|
||||
};
|
||||
uint8_t id[NAND_MAX_ID_LEN];
|
||||
};
|
||||
unsigned int pagesize;
|
||||
unsigned int chipsize;
|
||||
unsigned int erasesize;
|
||||
unsigned int options;
|
||||
uint16_t id_len;
|
||||
uint16_t oobsize;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -542,7 +614,7 @@ struct nand_flash_dev {
|
|||
*/
|
||||
struct nand_manufacturers {
|
||||
int id;
|
||||
char * name;
|
||||
char *name;
|
||||
};
|
||||
|
||||
extern struct nand_flash_dev nand_flash_ids[];
|
||||
|
|
@ -555,13 +627,8 @@ extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
|
|||
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
||||
int allowbbt);
|
||||
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
||||
size_t * retlen, uint8_t * buf);
|
||||
size_t *retlen, uint8_t *buf);
|
||||
extern int add_mtd_nand_device(struct mtd_info *mtd, char *devname);
|
||||
/*
|
||||
* Constants for oob configuration
|
||||
*/
|
||||
#define NAND_SMALL_BADBLOCK_POS 5
|
||||
#define NAND_LARGE_BADBLOCK_POS 0
|
||||
|
||||
/**
|
||||
* struct platform_nand_chip - chip level device structure
|
||||
|
|
@ -571,40 +638,52 @@ extern int add_mtd_nand_device(struct mtd_info *mtd, char *devname);
|
|||
* @partitions: mtd partition list
|
||||
* @chip_delay: R/B delay value in us
|
||||
* @options: Option flags, e.g. 16bit buswidth
|
||||
* @ecclayout: ecc layout info structure
|
||||
* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
|
||||
* @ecclayout: ECC layout info structure
|
||||
* @part_probe_types: NULL-terminated array of probe types
|
||||
* @priv: hardware controller specific settings
|
||||
*/
|
||||
struct platform_nand_chip {
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
const char **part_probe_types;
|
||||
void *priv;
|
||||
int nr_chips;
|
||||
int chip_offset;
|
||||
int nr_partitions;
|
||||
struct mtd_partition *partitions;
|
||||
struct nand_ecclayout *ecclayout;
|
||||
int chip_delay;
|
||||
unsigned int options;
|
||||
unsigned int bbt_options;
|
||||
const char **part_probe_types;
|
||||
};
|
||||
|
||||
/* Keep gcc happy */
|
||||
struct platform_device;
|
||||
|
||||
/**
|
||||
* struct platform_nand_ctrl - controller level device structure
|
||||
* @probe: platform specific function to probe/setup hardware
|
||||
* @remove: platform specific function to remove/teardown hardware
|
||||
* @hwcontrol: platform specific hardware control structure
|
||||
* @dev_ready: platform specific function to read ready/busy pin
|
||||
* @select_chip: platform specific chip select function
|
||||
* @cmd_ctrl: platform specific function for controlling
|
||||
* ALE/CLE/nCE. Also used to write command and address
|
||||
* @write_buf: platform specific function for write buffer
|
||||
* @read_buf: platform specific function for read buffer
|
||||
* @read_byte: platform specific function to read one byte from chip
|
||||
* @priv: private data to transport driver specific settings
|
||||
*
|
||||
* All fields are optional and depend on the hardware driver requirements
|
||||
*/
|
||||
struct platform_nand_ctrl {
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
|
||||
unsigned int ctrl);
|
||||
void *priv;
|
||||
int (*probe)(struct platform_device *pdev);
|
||||
void (*remove)(struct platform_device *pdev);
|
||||
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
||||
int (*dev_ready)(struct mtd_info *mtd);
|
||||
void (*select_chip)(struct mtd_info *mtd, int chip);
|
||||
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
||||
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
||||
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
||||
unsigned char (*read_byte)(struct mtd_info *mtd);
|
||||
void *priv;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -613,8 +692,8 @@ struct platform_nand_ctrl {
|
|||
* @ctrl: controller level device structure
|
||||
*/
|
||||
struct platform_nand_data {
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
struct platform_nand_chip chip;
|
||||
struct platform_nand_ctrl ctrl;
|
||||
};
|
||||
|
||||
/* Some helpers to access the data structures */
|
||||
|
|
@ -626,6 +705,20 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
|
|||
return chip->priv;
|
||||
}
|
||||
|
||||
#endif /* DOXYGEN_SHOULD_SKIP_THIS */
|
||||
/* return the supported asynchronous timing mode. */
|
||||
static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
|
||||
{
|
||||
if (!chip->onfi_version)
|
||||
return ONFI_TIMING_MODE_UNKNOWN;
|
||||
return le16_to_cpu(chip->onfi_params.async_timing_mode);
|
||||
}
|
||||
|
||||
/* return the supported synchronous timing mode. */
|
||||
static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
|
||||
{
|
||||
if (!chip->onfi_version)
|
||||
return ONFI_TIMING_MODE_UNKNOWN;
|
||||
return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
|
||||
}
|
||||
|
||||
#endif /* __LINUX_MTD_NAND_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright © 2011 Ivan Djelic <ivan.djelic@parrot.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This file is the header for the NAND BCH ECC implementation.
|
||||
*/
|
||||
|
||||
#ifndef __MTD_NAND_BCH_H__
|
||||
#define __MTD_NAND_BCH_H__
|
||||
|
||||
struct mtd_info;
|
||||
struct nand_bch_control;
|
||||
|
||||
#if defined(CONFIG_NAND_ECC_BCH)
|
||||
|
||||
static inline int mtd_nand_has_bch(void) { return 1; }
|
||||
|
||||
/*
|
||||
* Calculate BCH ecc code
|
||||
*/
|
||||
int nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code);
|
||||
|
||||
/*
|
||||
* Detect and correct bit errors
|
||||
*/
|
||||
int nand_bch_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc,
|
||||
u_char *calc_ecc);
|
||||
/*
|
||||
* Initialize BCH encoder/decoder
|
||||
*/
|
||||
struct nand_bch_control *
|
||||
nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
|
||||
unsigned int eccbytes, struct nand_ecclayout **ecclayout);
|
||||
/*
|
||||
* Release BCH encoder/decoder resources
|
||||
*/
|
||||
void nand_bch_free(struct nand_bch_control *nbc);
|
||||
|
||||
#else /* !CONFIG_MTD_NAND_ECC_BCH */
|
||||
|
||||
static inline int mtd_nand_has_bch(void) { return 0; }
|
||||
|
||||
static inline int
|
||||
nand_bch_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int
|
||||
nand_bch_correct_data(struct mtd_info *mtd, unsigned char *buf,
|
||||
unsigned char *read_ecc, unsigned char *calc_ecc)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline struct nand_bch_control *
|
||||
nand_bch_init(struct mtd_info *mtd, unsigned int eccsize,
|
||||
unsigned int eccbytes, struct nand_ecclayout **ecclayout)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline void nand_bch_free(struct nand_bch_control *nbc) {}
|
||||
|
||||
#endif /* CONFIG_MTD_NAND_ECC_BCH */
|
||||
|
||||
#endif /* __MTD_NAND_BCH_H__ */
|
||||
Loading…
Reference in New Issue