* Patch by Yuli Barcohen, 13 Jul 2004:
Allow clock setting on MPC866/MPC885 series chips according to environment variable `cpuclk' * Patch by Yuli Barcohen, 20 Apr 2004: Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
This commit is contained in:
parent
4ec3a7f0fd
commit
66ca92a5ba
|
@ -2,6 +2,13 @@
|
||||||
Changes since U-Boot 1.1.1:
|
Changes since U-Boot 1.1.1:
|
||||||
======================================================================
|
======================================================================
|
||||||
|
|
||||||
|
* Patch by Yuli Barcohen, 13 Jul 2004:
|
||||||
|
Allow clock setting on MPC866/MPC885 series chips according to
|
||||||
|
environment variable `cpuclk'
|
||||||
|
|
||||||
|
* Patch by Yuli Barcohen, 20 Apr 2004:
|
||||||
|
Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
|
||||||
|
|
||||||
* Patch by Vincent Dubey, 24 Sep 2004:
|
* Patch by Vincent Dubey, 24 Sep 2004:
|
||||||
Add support for xaeniax board
|
Add support for xaeniax board
|
||||||
|
|
||||||
|
|
17
README
17
README
|
@ -339,16 +339,17 @@ The following options need to be configured:
|
||||||
CONFIG_MPC8240, CONFIG_MPC8245
|
CONFIG_MPC8240, CONFIG_MPC8245
|
||||||
|
|
||||||
- 8xx CPU Options: (if using an MPC8xx cpu)
|
- 8xx CPU Options: (if using an MPC8xx cpu)
|
||||||
Define one or more of
|
CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
|
||||||
CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() cannot work
|
get_gclk_freq() cannot work
|
||||||
e.g. if there is no 32KHz
|
e.g. if there is no 32KHz
|
||||||
reference PIT/RTC clock
|
reference PIT/RTC clock
|
||||||
|
CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK
|
||||||
|
or XTAL/EXTAL)
|
||||||
|
|
||||||
- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
|
- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
|
||||||
CFG_866_OSCCLK
|
CFG_8xx_CPUCLK_MIN
|
||||||
CFG_866_CPUCLK_MIN
|
CFG_8xx_CPUCLK_MAX
|
||||||
CFG_866_CPUCLK_MAX
|
CONFIG_8xx_CPUCLK_DEFAULT
|
||||||
CFG_866_CPUCLK_DEFAULT
|
|
||||||
See doc/README.MPC866
|
See doc/README.MPC866
|
||||||
|
|
||||||
CFG_MEASURE_CPUCLK
|
CFG_MEASURE_CPUCLK
|
||||||
|
@ -358,7 +359,7 @@ The following options need to be configured:
|
||||||
values. Mostly useful for board bringup to make sure
|
values. Mostly useful for board bringup to make sure
|
||||||
the PLL is locked at the intended frequency. Note
|
the PLL is locked at the intended frequency. Note
|
||||||
that this requires a (stable) reference clock (32 kHz
|
that this requires a (stable) reference clock (32 kHz
|
||||||
RTC clock),
|
RTC clock or CFG_8XX_XIN)
|
||||||
|
|
||||||
- Linux Kernel Interface:
|
- Linux Kernel Interface:
|
||||||
CONFIG_CLOCKS_IN_MHZ
|
CONFIG_CLOCKS_IN_MHZ
|
||||||
|
|
|
@ -20,13 +20,6 @@
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/cpm_8260.h>
|
#include <asm/cpm_8260.h>
|
||||||
|
|
||||||
/*
|
|
||||||
* because we have stack and init data in dual port ram
|
|
||||||
* we must reduce the size
|
|
||||||
*/
|
|
||||||
#undef CPM_DATAONLY_SIZE
|
|
||||||
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
|
|
||||||
|
|
||||||
void
|
void
|
||||||
m8260_cpm_reset(void)
|
m8260_cpm_reset(void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -124,13 +124,13 @@ static int check_CPU (long clock, uint pvr, uint immr)
|
||||||
printf ("unknown M%s (0x%08x)", id_str, k);
|
printf ("unknown M%s (0x%08x)", id_str, k);
|
||||||
|
|
||||||
|
|
||||||
#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
|
#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
|
||||||
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
|
printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
|
||||||
strmhz (buf, clock),
|
strmhz (buf, clock),
|
||||||
CFG_866_CPUCLK_MIN / 1000000,
|
CFG_8xx_CPUCLK_MIN / 1000000,
|
||||||
((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
|
((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
|
||||||
CFG_866_CPUCLK_MAX / 1000000,
|
CFG_8xx_CPUCLK_MAX / 1000000,
|
||||||
((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
|
((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
|
||||||
);
|
);
|
||||||
#else
|
#else
|
||||||
printf (" at %s MHz: ", strmhz (buf, clock));
|
printf (" at %s MHz: ", strmhz (buf, clock));
|
||||||
|
@ -140,7 +140,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
|
||||||
checkdcache () >> 10
|
checkdcache () >> 10
|
||||||
);
|
);
|
||||||
|
|
||||||
/* do we have a FEC (860T/P or 852/859/866)? */
|
/* do we have a FEC (860T/P or 852/859/866/885)? */
|
||||||
|
|
||||||
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
|
immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
|
||||||
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
|
if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
|
||||||
|
|
|
@ -25,7 +25,7 @@
|
||||||
#include <mpc8xx.h>
|
#include <mpc8xx.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
|
|
||||||
#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK)
|
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK)
|
||||||
|
|
||||||
#define PITC_SHIFT 16
|
#define PITC_SHIFT 16
|
||||||
#define PITR_SHIFT 16
|
#define PITR_SHIFT 16
|
||||||
|
@ -172,7 +172,7 @@ unsigned long measure_gclk(void)
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
|
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
|
* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
|
||||||
|
@ -226,15 +226,15 @@ int get_clocks (void)
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
||||||
#else /* CONFIG_MPC866_FAMILY */
|
#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
|
||||||
|
|
||||||
static long init_pll_866 (long clk);
|
static long init_pll_866 (long clk);
|
||||||
|
|
||||||
/* This function sets up PLL (init_pll_866() is called) and
|
/* This function sets up PLL (init_pll_866() is called) and
|
||||||
* fills gd->cpu_clk and gd->bus_clk according to the environment
|
* fills gd->cpu_clk and gd->bus_clk according to the environment
|
||||||
* variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
|
* variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
|
||||||
* contains invalid value).
|
* contains invalid value).
|
||||||
* This functions requires an MPC866 series CPU.
|
* This functions requires an MPC866 or newer series CPU.
|
||||||
*/
|
*/
|
||||||
int get_clocks_866 (void)
|
int get_clocks_866 (void)
|
||||||
{
|
{
|
||||||
|
@ -248,8 +248,8 @@ int get_clocks_866 (void)
|
||||||
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
|
if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
|
||||||
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
|
cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
|
||||||
|
|
||||||
if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
|
if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
|
||||||
cpuclk = CFG_866_CPUCLK_DEFAULT;
|
cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
|
||||||
|
|
||||||
gd->cpu_clk = init_pll_866 (cpuclk);
|
gd->cpu_clk = init_pll_866 (cpuclk);
|
||||||
#if defined(CFG_MEASURE_CPUCLK)
|
#if defined(CFG_MEASURE_CPUCLK)
|
||||||
|
@ -284,13 +284,13 @@ int sdram_adjust_866 (void)
|
||||||
|
|
||||||
mamr = immr->im_memctl.memc_mamr;
|
mamr = immr->im_memctl.memc_mamr;
|
||||||
mamr &= ~MAMR_PTA_MSK;
|
mamr &= ~MAMR_PTA_MSK;
|
||||||
mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
|
mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
|
||||||
immr->im_memctl.memc_mamr = mamr;
|
immr->im_memctl.memc_mamr = mamr;
|
||||||
|
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Configure PLL for MPC866/859 CPU series
|
/* Configure PLL for MPC866/859/885 CPU series
|
||||||
* PLL multiplication factor is set to the value nearest to the desired clk,
|
* PLL multiplication factor is set to the value nearest to the desired clk,
|
||||||
* assuming a oscclk of 10 MHz.
|
* assuming a oscclk of 10 MHz.
|
||||||
*/
|
*/
|
||||||
|
@ -312,19 +312,19 @@ static long init_pll_866 (long clk)
|
||||||
|
|
||||||
if (clk < 40000000) {
|
if (clk < 40000000) {
|
||||||
s = 2;
|
s = 2;
|
||||||
step_mfi = CFG_866_OSCCLK / 4;
|
step_mfi = CONFIG_8xx_OSCLK / 4;
|
||||||
mfd = 7;
|
mfd = 7;
|
||||||
step_mfn = CFG_866_OSCCLK / 30;
|
step_mfn = CONFIG_8xx_OSCLK / 30;
|
||||||
} else if (clk < 80000000) {
|
} else if (clk < 80000000) {
|
||||||
s = 1;
|
s = 1;
|
||||||
step_mfi = CFG_866_OSCCLK / 2;
|
step_mfi = CONFIG_8xx_OSCLK / 2;
|
||||||
mfd = 14;
|
mfd = 14;
|
||||||
step_mfn = CFG_866_OSCCLK / 30;
|
step_mfn = CONFIG_8xx_OSCLK / 30;
|
||||||
} else {
|
} else {
|
||||||
s = 0;
|
s = 0;
|
||||||
step_mfi = CFG_866_OSCCLK;
|
step_mfi = CONFIG_8xx_OSCLK;
|
||||||
mfd = 29;
|
mfd = 29;
|
||||||
step_mfn = CFG_866_OSCCLK / 30;
|
step_mfn = CONFIG_8xx_OSCLK / 30;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Calculate integer part of multiplication factor
|
/* Calculate integer part of multiplication factor
|
||||||
|
@ -362,7 +362,7 @@ static long init_pll_866 (long clk)
|
||||||
return (n);
|
return (n);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_MPC866_FAMILY */
|
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
|
||||||
|
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -1,12 +1,12 @@
|
||||||
The current implementation allows the user to specify the desired CPU
|
The current implementation allows the user to specify the desired CPU
|
||||||
clock value, in MHz, via an environment variable "cpuclk".
|
clock value, in MHz, via an environment variable "cpuclk".
|
||||||
|
|
||||||
Three compile-time constants are used:
|
Four compile-time constants are used:
|
||||||
|
|
||||||
CFG_866_OSCCLK - input quartz clock
|
CONFIG_8xx_OSCLK - input quartz clock
|
||||||
CFG_866_CPUCLK_MIN - minimum allowed CPU clock
|
CFG_8xx_CPUCLK_MIN - minimum allowed CPU clock
|
||||||
CFG_866_CPUCLK_MAX - maximum allowed CPU clock
|
CFG_8xx_CPUCLK_MAX - maximum allowed CPU clock
|
||||||
CFG_866_CPUCLK_DEFAULT - default CPU clock value
|
CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value
|
||||||
|
|
||||||
If the "cpuclk" environment variable value is within the CPUCLK_MIN /
|
If the "cpuclk" environment variable value is within the CPUCLK_MIN /
|
||||||
CPUCLK_MAX limits, the specified value is used. Otherwise, the
|
CPUCLK_MAX limits, the specified value is used. Otherwise, the
|
||||||
|
@ -16,8 +16,9 @@ Please make sure you understand what you are doing, and understand
|
||||||
the restrictions of your hardware (board, processor). For example,
|
the restrictions of your hardware (board, processor). For example,
|
||||||
ethernet will stop working for CPU clock frequencies below 25 MHz.
|
ethernet will stop working for CPU clock frequencies below 25 MHz.
|
||||||
|
|
||||||
Please note that for now the new clock-handling code has been enabled
|
Please note that the new clock-handling code is enabled if
|
||||||
for the TQM866M board only, even though it should be pretty much
|
CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports
|
||||||
common for other MPC859 / MPC866 based boards also. Our intention
|
only MPC866 and newer CPUs, this constant MUST NOT be defined for
|
||||||
here was to move in small steps and not to break the existing code
|
MPC823/850/860/862 series. The clock generation algorithm for older
|
||||||
for other boards.
|
chips is different and has not been implemented yet. If you need it,
|
||||||
|
your patch is welcome.
|
||||||
|
|
|
@ -41,7 +41,14 @@
|
||||||
#define FEC_ENET
|
#define FEC_ENET
|
||||||
#endif /* CONFIG_FEC_ENET */
|
#endif /* CONFIG_FEC_ENET */
|
||||||
|
|
||||||
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||||
|
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
|
||||||
|
#define CFG_8xx_CPUCLK_MIN 40000000
|
||||||
|
#ifdef CONFIG_MPC852T
|
||||||
|
#define CFG_8xx_CPUCLK_MAX 50000000
|
||||||
|
#else
|
||||||
|
#define CFG_8xx_CPUCLK_MAX 120000000
|
||||||
|
#endif /* CONFIG_MPC852T */
|
||||||
|
|
||||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||||
| CFG_CMD_DHCP \
|
| CFG_CMD_DHCP \
|
||||||
|
@ -89,6 +96,15 @@
|
||||||
|
|
||||||
#define CFG_MAMR 0x00802114
|
#define CFG_MAMR 0x00802114
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 2048 SDRAM rows
|
||||||
|
* 1000 factor s -> ms
|
||||||
|
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||||
|
* 4 Number of refresh cycles per period
|
||||||
|
* 64 Refresh cycle in ms per number of rows
|
||||||
|
*/
|
||||||
|
#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
|
||||||
|
|
||||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||||
#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
|
#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
|
||||||
|
|
||||||
|
|
|
@ -44,25 +44,25 @@
|
||||||
/*
|
/*
|
||||||
* 10 MHz - PLL input clock
|
* 10 MHz - PLL input clock
|
||||||
*/
|
*/
|
||||||
#define CFG_866_OSCCLK 10000000
|
#define CFG_8xx_OSCCLK 10000000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 50 MHz - default CPU clock
|
* 50 MHz - default CPU clock
|
||||||
*/
|
*/
|
||||||
#define CFG_866_CPUCLK_DEFAULT 50000000
|
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 15 MHz - CPU minimum clock
|
* 15 MHz - CPU minimum clock
|
||||||
*/
|
*/
|
||||||
#define CFG_866_CPUCLK_MIN 15000000
|
#define CFG_8xx_CPUCLK_MIN 15000000
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 133 MHz - CPU maximum clock
|
* 133 MHz - CPU maximum clock
|
||||||
*/
|
*/
|
||||||
#define CFG_866_CPUCLK_MAX 133000000
|
#define CFG_8xx_CPUCLK_MAX 133000000
|
||||||
|
|
||||||
#define CFG_MEASURE_CPUCLK
|
#define CFG_MEASURE_CPUCLK
|
||||||
#define CFG_8XX_XIN CFG_866_OSCCLK
|
#define CFG_8XX_XIN CFG_8xx_OSCCLK
|
||||||
|
|
||||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
|
|
||||||
|
@ -307,7 +307,7 @@
|
||||||
* 4 Number of refresh cycles per period
|
* 4 Number of refresh cycles per period
|
||||||
* 64 Refresh cycle in ms per number of rows
|
* 64 Refresh cycle in ms per number of rows
|
||||||
*/
|
*/
|
||||||
#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory Periodic Timer Prescaler
|
* Memory Periodic Timer Prescaler
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
/*
|
/*
|
||||||
* (C) Copyright 2000-2003
|
* (C) Copyright 2000-2004
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
*
|
*
|
||||||
* See file CREDITS for list of people who contributed to this
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
@ -36,10 +36,10 @@
|
||||||
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
|
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
|
||||||
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
|
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
|
||||||
|
|
||||||
#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
|
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
|
||||||
#define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
|
#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
|
||||||
#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
|
#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
|
||||||
#define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
|
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
|
||||||
/* (it will be used if there is no */
|
/* (it will be used if there is no */
|
||||||
/* 'cpuclk' variable with valid value) */
|
/* 'cpuclk' variable with valid value) */
|
||||||
|
|
||||||
|
@ -404,12 +404,12 @@
|
||||||
* 4 Number of refresh cycles per period
|
* 4 Number of refresh cycles per period
|
||||||
* 64 Refresh cycle in ms per number of rows
|
* 64 Refresh cycle in ms per number of rows
|
||||||
*/
|
*/
|
||||||
#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Memory Periodic Timer Prescaler
|
* Memory Periodic Timer Prescaler
|
||||||
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
|
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
|
||||||
* (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
|
* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
|
||||||
*/
|
*/
|
||||||
#define CFG_MAMR_PTA 39
|
#define CFG_MAMR_PTA 39
|
||||||
|
|
||||||
|
|
|
@ -264,7 +264,7 @@ init_fnc_t *init_sequence[] = {
|
||||||
board_early_init_f,
|
board_early_init_f,
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
|
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
||||||
adjust_sdram_tbs_8xx,
|
adjust_sdram_tbs_8xx,
|
||||||
|
@ -280,7 +280,7 @@ init_fnc_t *init_sequence[] = {
|
||||||
board_postclk_init,
|
board_postclk_init,
|
||||||
#endif
|
#endif
|
||||||
env_init,
|
env_init,
|
||||||
#if defined(CONFIG_TQM866M) || defined(CONFIG_NC650)
|
#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||||
get_clocks_866, /* get CPU and bus clocks according to the environment variable */
|
get_clocks_866, /* get CPU and bus clocks according to the environment variable */
|
||||||
sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
|
sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
|
||||||
init_timebase,
|
init_timebase,
|
||||||
|
|
Loading…
Reference in New Issue