diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8674a2d17..8465d4a7f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -92,8 +92,10 @@ config ARCH_MVEBU select CLKDEV_LOOKUP select GPIOLIB select HAS_DEBUG_LL + select HAVE_PBL_MULTI_IMAGES select MVEBU_MBUS select OFTREE + select OF_ADDRESS_PCI config ARCH_MXS bool "Freescale i.MX23/28 (mxs) based" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 64db73c62..983f7f57c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -86,17 +86,11 @@ machine-$(CONFIG_ARCH_ZYNQ) := zynq board-$(CONFIG_MACH_A9M2410) += a9m2410 board-$(CONFIG_MACH_A9M2440) += a9m2440 board-$(CONFIG_MACH_AT91RM9200EK) += at91rm9200ek -board-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug -board-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox -board-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp board-$(CONFIG_MACH_MINI2440) += friendlyarm-mini2440 board-$(CONFIG_MACH_MINI6410) += friendlyarm-mini6410 board-$(CONFIG_MACH_PCM027) += phytec-phycore-pxa270 -board-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ -board-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox board-$(CONFIG_MACH_TINY210) += friendlyarm-tiny210 board-$(CONFIG_MACH_TINY6410) += friendlyarm-tiny6410 -board-$(CONFIG_MACH_USI_TOPKICK) += usi-topkick machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index b8bfb8433..d20051275 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -41,6 +41,8 @@ obj-$(CONFIG_MACH_FREESCALE_MX53_SMD) += freescale-mx53-smd/ obj-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += freescale-mx53-vmx53/ obj-$(CONFIG_MACH_GE863) += telit-evk-pro3/ obj-$(CONFIG_MACH_GK802) += gk802/ +obj-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += globalscale-guruplug/ +obj-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += globalscale-mirabox/ obj-$(CONFIG_MACH_GUF_CUPID) += guf-cupid/ obj-$(CONFIG_MACH_GUF_SANTARO) += guf-santaro/ obj-$(CONFIG_MACH_GUF_VINCELL) += guf-vincell/ @@ -48,6 +50,7 @@ obj-$(CONFIG_MACH_HIGHBANK) += highbank/ obj-$(CONFIG_MACH_IMX21ADS) += freescale-mx21-ads/ obj-$(CONFIG_MACH_IMX233_OLINUXINO) += imx233-olinuxino/ obj-$(CONFIG_MACH_IMX27ADS) += freescale-mx27-ads/ +obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/ obj-$(CONFIG_MACH_MB7707) += module-mb7707/ obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MMCCPU) += mmccpu/ @@ -73,6 +76,7 @@ obj-$(CONFIG_MACH_PCM043) += phytec-phycore-imx35/ obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PCM051) += phytec-phycore-am335x/ obj-$(CONFIG_MACH_PHYTEC_PFLA02) += phytec-phyflex-imx6/ +obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/ obj-$(CONFIG_MACH_PM9261) += pm9261/ obj-$(CONFIG_MACH_PM9263) += pm9263/ obj-$(CONFIG_MACH_PM9G45) += pm9g45/ @@ -88,6 +92,7 @@ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/ obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/ +obj-$(CONFIG_MACH_SOLIDRUN_CUBOX) += solidrun-cubox/ obj-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += solidrun-microsom/ obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/ obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/ @@ -104,6 +109,7 @@ obj-$(CONFIG_MACH_UDOO) += udoo/ obj-$(CONFIG_MACH_USB_A9260) += usb-a926x/ obj-$(CONFIG_MACH_USB_A9263) += usb-a926x/ obj-$(CONFIG_MACH_USB_A9G20) += usb-a926x/ +obj-$(CONFIG_MACH_USI_TOPKICK) += usi-topkick/ obj-$(CONFIG_MACH_VERSATILEPB) += versatile/ obj-$(CONFIG_MACH_VEXPRESS) += vexpress/ obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/ diff --git a/arch/arm/boards/globalscale-guruplug/Makefile b/arch/arm/boards/globalscale-guruplug/Makefile index dcfc2937d..01c7a259e 100644 --- a/arch/arm/boards/globalscale-guruplug/Makefile +++ b/arch/arm/boards/globalscale-guruplug/Makefile @@ -1 +1,2 @@ obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/globalscale-guruplug/lowlevel.c b/arch/arm/boards/globalscale-guruplug/lowlevel.c new file mode 100644 index 000000000..508746a06 --- /dev/null +++ b/arch/arm/boards/globalscale-guruplug/lowlevel.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +extern char __dtb_kirkwood_guruplug_server_plus_bb_start[]; + +ENTRY_FUNCTION(start_globalscale_guruplug, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_kirkwood_guruplug_server_plus_bb_start - + get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/boards/globalscale-mirabox/Makefile b/arch/arm/boards/globalscale-mirabox/Makefile index dcfc2937d..01c7a259e 100644 --- a/arch/arm/boards/globalscale-mirabox/Makefile +++ b/arch/arm/boards/globalscale-mirabox/Makefile @@ -1 +1,2 @@ obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/globalscale-mirabox/kwbimage.cfg b/arch/arm/boards/globalscale-mirabox/kwbimage.cfg index 72283d9b6..16fb77c31 100644 --- a/arch/arm/boards/globalscale-mirabox/kwbimage.cfg +++ b/arch/arm/boards/globalscale-mirabox/kwbimage.cfg @@ -2,4 +2,4 @@ VERSION 1 BOOT_FROM nand NAND_BLKSZ 00020000 NAND_BADBLK_LOCATION 01 -BINARY globalscale-mirabox-binary.0 0000005b 00000068 +BINARY arch/arm/boards/globalscale-mirabox/binary.0 0000005b 00000068 diff --git a/arch/arm/boards/globalscale-mirabox/lowlevel.c b/arch/arm/boards/globalscale-mirabox/lowlevel.c new file mode 100644 index 000000000..92203b768 --- /dev/null +++ b/arch/arm/boards/globalscale-mirabox/lowlevel.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +extern char __dtb_armada_370_mirabox_bb_start[]; + +ENTRY_FUNCTION(start_globalscale_mirabox, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_armada_370_mirabox_bb_start - + get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/boards/marvell-armada-xp-gp/Makefile b/arch/arm/boards/marvell-armada-xp-gp/Makefile index dcfc2937d..01c7a259e 100644 --- a/arch/arm/boards/marvell-armada-xp-gp/Makefile +++ b/arch/arm/boards/marvell-armada-xp-gp/Makefile @@ -1 +1,2 @@ obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/marvell-armada-xp-gp/kwbimage.cfg b/arch/arm/boards/marvell-armada-xp-gp/kwbimage.cfg index db75969fe..3f66aa080 100644 --- a/arch/arm/boards/marvell-armada-xp-gp/kwbimage.cfg +++ b/arch/arm/boards/marvell-armada-xp-gp/kwbimage.cfg @@ -1,3 +1,3 @@ VERSION 1 BOOT_FROM spi -BINARY marvell-armada-xp-gp-binary.0 0000005b 00000068 +BINARY arch/arm/boards/marvell-armada-xp-gp/binary.0 0000005b 00000068 diff --git a/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c new file mode 100644 index 000000000..046057f56 --- /dev/null +++ b/arch/arm/boards/marvell-armada-xp-gp/lowlevel.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +extern char __dtb_armada_xp_gp_bb_start[]; + +ENTRY_FUNCTION(start_marvell_armada_xp_gp, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_armada_xp_gp_bb_start - get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/boards/plathome-openblocks-ax3/Makefile b/arch/arm/boards/plathome-openblocks-ax3/Makefile index dcfc2937d..01c7a259e 100644 --- a/arch/arm/boards/plathome-openblocks-ax3/Makefile +++ b/arch/arm/boards/plathome-openblocks-ax3/Makefile @@ -1 +1,2 @@ obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/boards/plathome-openblocks-ax3/kwbimage.cfg b/arch/arm/boards/plathome-openblocks-ax3/kwbimage.cfg index 69fd1fd1c..1d0571503 100644 --- a/arch/arm/boards/plathome-openblocks-ax3/kwbimage.cfg +++ b/arch/arm/boards/plathome-openblocks-ax3/kwbimage.cfg @@ -1,3 +1,3 @@ VERSION 1 BOOT_FROM spi -BINARY plathome-openblocks-ax3-binary.0 0000005b 00000068 +BINARY arch/arm/boards/plathome-openblocks-ax3/binary.0 0000005b 00000068 diff --git a/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c new file mode 100644 index 000000000..721d2de97 --- /dev/null +++ b/arch/arm/boards/plathome-openblocks-ax3/lowlevel.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +extern char __dtb_armada_xp_openblocks_ax3_4_bb_start[]; + +ENTRY_FUNCTION(start_plathome_openblocks_ax3, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_armada_xp_openblocks_ax3_4_bb_start - + get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/boards/usi-topkick/Makefile b/arch/arm/boards/usi-topkick/Makefile index dcfc2937d..01c7a259e 100644 --- a/arch/arm/boards/usi-topkick/Makefile +++ b/arch/arm/boards/usi-topkick/Makefile @@ -1 +1,2 @@ obj-y += board.o +lwl-y += lowlevel.o diff --git a/arch/arm/mach-mvebu/include/mach/mvebu.h b/arch/arm/boards/usi-topkick/lowlevel.c similarity index 54% rename from arch/arm/mach-mvebu/include/mach/mvebu.h rename to arch/arm/boards/usi-topkick/lowlevel.c index e13a446fc..df661564d 100644 --- a/arch/arm/mach-mvebu/include/mach/mvebu.h +++ b/arch/arm/boards/usi-topkick/lowlevel.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2013 Thomas Petazzoni + * Copyright (C) 2014 + * Sebastian Hesselbarth * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -13,10 +14,21 @@ * */ -#ifndef __MACH_MVEBU_H -#define __MACH_MVEBU_H +#include +#include +#include +#include +#include -int mvebu_add_uart0(void); -void __naked __noreturn mvebu_barebox_entry(void); +extern char __dtb_kirkwood_topkick_bb_start[]; -#endif /* __MACH_MVEBU_H */ +ENTRY_FUNCTION(start_usi_topkick, r0, r1, r2) +{ + void *fdt; + + arm_cpu_lowlevel_init(); + + fdt = __dtb_kirkwood_topkick_bb_start - get_runtime_offset(); + + mvebu_barebox_entry(fdt); +} diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a9bb20e06..72ad5e6a6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -32,7 +32,6 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \ imx6q-var-custom.dtb \ imx6s-riotboard.dtb \ imx6q-phytec-pbaa03.dtb -dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox-bb.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3188-radxarock.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb @@ -46,37 +45,42 @@ BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME)) obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o pbl-$(CONFIG_MACH_BEAGLEBONE) += am335x-bone.dtb.o am335x-boneblack.dtb.o am335x-bone-common.dtb.o +pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o pbl-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += imx51-genesi-efika-sb.dtb.o pbl-$(CONFIG_MACH_EMBEST_RIOTBOARD) += imx6s-riotboard.dtb.o pbl-$(CONFIG_MACH_FREESCALE_MX51_PDK) += imx51-babbage.dtb.o pbl-$(CONFIG_MACH_FREESCALE_MX53_LOCO) += imx53-qsb.dtb.o imx53-qsrb.dtb.o pbl-$(CONFIG_MACH_FREESCALE_MX53_VMX53) += imx53-voipac-bsb.dtb.o -pbl-$(CONFIG_MACH_DFI_FS700_M60) += imx6q-dfi-fs700-m60-6q.dtb.o imx6dl-dfi-fs700-m60-6s.dtb.o +pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o +pbl-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += kirkwood-guruplug-server-plus-bb.dtb.o +pbl-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += armada-370-mirabox-bb.dtb.o +pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o +pbl-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += armada-xp-gp-bb.dtb.o +pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o pbl-$(CONFIG_MACH_NVIDIA_BEAVER) += tegra30-beaver.dtb.o pbl-$(CONFIG_MACH_NVIDIA_JETSON) += tegra124-jetson-tk1.dtb.o +pbl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o +pbl-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o +pbl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o pbl-$(CONFIG_MACH_PCM051) += am335x-phytec-phycore.dtb.o pbl-$(CONFIG_MACH_PHYTEC_PFLA02) += imx6s-phytec-pbab01.dtb.o imx6dl-phytec-pbab01.dtb.o imx6q-phytec-pbab01.dtb.o +pbl-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o +pbl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-edmqmx6.dtb.o +pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o +pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o +pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o +pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox-bb.dtb.o -pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o -pbl-$(CONFIG_MACH_PCA100) += imx27-phytec-phycard-s-rdk-bb.dtb.o -pbl-$(CONFIG_MACH_PCM038) += imx27-phytec-phycore-rdk.dtb.o +pbl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o pbl-$(CONFIG_MACH_TORADEX_COLIBRI_T20) += tegra20-colibri-iris.dtb.o pbl-$(CONFIG_MACH_TOSHIBA_AC100) += tegra20-paz00.dtb.o pbl-$(CONFIG_MACH_TQMA53) += imx53-mba53.dtb.o pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o pbl-$(CONFIG_MACH_TX25) += imx25-karo-tx25.dtb.o -pbl-$(CONFIG_MACH_RADXA_ROCK) += rk3188-radxarock.dtb.o -pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o -pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o -pbl-$(CONFIG_MACH_SOLIDRUN_MICROSOM) += imx6dl-hummingboard.dtb.o -pbl-$(CONFIG_MACH_SABRELITE) += imx6q-sabrelite.dtb.o imx6dl-sabrelite.dtb.o -pbl-$(CONFIG_MACH_SABRESD) += imx6q-sabresd.dtb.o -pbl-$(CONFIG_MACH_GUF_SANTARO) += imx6q-guf-santaro.dtb.o -pbl-$(CONFIG_MACH_NITROGEN6X) += imx6q-nitrogen6x.dtb.o imx6dl-nitrogen6x.dtb.o pbl-$(CONFIG_MACH_UDOO) += imx6q-udoo.dtb.o +pbl-$(CONFIG_MACH_USI_TOPKICK) += kirkwood-topkick-bb.dtb.o pbl-$(CONFIG_MACH_VARISCITE_MX6) += imx6q-var-custom.dtb.o -pbl-$(CONFIG_MACH_PCAAXL3) += imx6q-phytec-pbaa03.dtb.o .SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S .SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y)) diff --git a/arch/arm/dts/armada-370-mirabox-bb.dts b/arch/arm/dts/armada-370-mirabox-bb.dts new file mode 100644 index 000000000..de37a75bb --- /dev/null +++ b/arch/arm/dts/armada-370-mirabox-bb.dts @@ -0,0 +1,25 @@ +/* + * Barebox specific DT overlay for Globalscale Mirabox + * Sebastian Hesselbarth + */ + +#include "arm/armada-370-mirabox.dts" + +/ { + chosen { + stdout-path = "/soc/internal-regs/serial@12000"; + }; + + soc { + ranges = ; + + internal-regs { + gpio_leds { + green_pwr_led { + barebox,default-trigger = "heartbeat"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/armada-xp-gp-bb.dts b/arch/arm/dts/armada-xp-gp-bb.dts new file mode 100644 index 000000000..383601642 --- /dev/null +++ b/arch/arm/dts/armada-xp-gp-bb.dts @@ -0,0 +1,12 @@ +/* + * Barebox specific DT overlay for Marvell Armada XP DB-MV784MP-GP + * Sebastian Hesselbarth + */ + +#include "arm/armada-xp-gp.dts" + +/ { + chosen { + stdout-path = "/soc/internal-regs/serial@12000"; + }; +}; diff --git a/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts new file mode 100644 index 000000000..611d72707 --- /dev/null +++ b/arch/arm/dts/armada-xp-openblocks-ax3-4-bb.dts @@ -0,0 +1,26 @@ +/* + * Barebox specific DT overlay for OpenBlocks AX3-4 board + * Sebastian Hesselbarth + */ + +#include "arm/armada-xp-openblocks-ax3-4.dts" + +/ { + chosen { + stdout-path = "/soc/internal-regs/serial@12000"; + }; + + soc { + ranges = ; + + internal-regs { + gpio_leds { + red_led { + barebox,default-trigger = "heartbeat"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts new file mode 100644 index 000000000..aba7c0616 --- /dev/null +++ b/arch/arm/dts/kirkwood-guruplug-server-plus-bb.dts @@ -0,0 +1,14 @@ +/* + * Barebox specific DT overlay for Globalscale Guruplug + * Sebastian Hesselbarth + */ + +#include "arm/kirkwood-guruplug-server-plus.dts" + +/ { + gpio-leds { + health-r { + barebox,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/dts/kirkwood-topkick-bb.dts b/arch/arm/dts/kirkwood-topkick-bb.dts new file mode 100644 index 000000000..20b74b111 --- /dev/null +++ b/arch/arm/dts/kirkwood-topkick-bb.dts @@ -0,0 +1,14 @@ +/* + * Barebox specific DT overlay for USI Topkick + * Sebastian Hesselbarth + */ + +#include "arm/kirkwood-topkick.dts" + +/ { + gpio-leds { + system { + barebox,default-trigger = "heartbeat"; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 70c49ecc6..18f61f74f 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -2,12 +2,10 @@ if ARCH_MVEBU config ARCH_TEXT_BASE hex - default 0x2000000 if MACH_PLATHOME_OPENBLOCKS_AX3 - default 0x2000000 if MACH_GLOBALSCALE_MIRABOX - default 0x2000000 if MACH_GLOBALSCALE_GURUPLUG - default 0x2000000 if MACH_USI_TOPKICK - default 0x2000000 if MACH_MARVELL_ARMADA_XP_GP - default 0x2000000 if MACH_SOLIDRUN_CUBOX + default 0x2000000 if ARCH_ARMADA_370 + default 0x2000000 if ARCH_ARMADA_XP + default 0x2000000 if ARCH_DOVE + default 0x2000000 if ARCH_KIRKWOOD choice prompt "Marvell EBU Processor" @@ -26,11 +24,13 @@ config ARCH_DOVE bool "Dove 88AP510" select CPU_V7 select CLOCKSOURCE_ORION + select PINCTRL_DOVE config ARCH_KIRKWOOD bool "Kirkwood" select CPU_FEROCEON select CLOCKSOURCE_ORION + select PINCTRL_KIRKWOOD endchoice @@ -40,14 +40,9 @@ endchoice if ARCH_ARMADA_370 -choice - prompt "Armada 370 Board Type" - config MACH_GLOBALSCALE_MIRABOX bool "Globalscale Mirabox" -endchoice - endif # ARCH_ARMADA_370 # @@ -56,17 +51,12 @@ endif # ARCH_ARMADA_370 if ARCH_ARMADA_XP -choice - prompt "Armada XP Board Type" - config MACH_PLATHOME_OPENBLOCKS_AX3 bool "PlatHome OpenBlocks AX3" config MACH_MARVELL_ARMADA_XP_GP bool "Marvell Armada XP GP" -endchoice - endif # ARCH_ARMADA_XP # @@ -75,14 +65,8 @@ endif # ARCH_ARMADA_XP if ARCH_DOVE -choice - prompt "Dove 88AP510 Board Type" - config MACH_SOLIDRUN_CUBOX bool "SolidRun CuBox" - select HAVE_PBL_MULTI_IMAGES - -endchoice endif # ARCH_DOVE @@ -92,17 +76,12 @@ endif # ARCH_DOVE if ARCH_KIRKWOOD -choice - prompt "Kirkwood Board Type" - config MACH_GLOBALSCALE_GURUPLUG bool "Guruplug" config MACH_USI_TOPKICK bool "Topkick" -endchoice - endif # ARCH_KIRKWOOD # diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 6e303663c..80b3947cc 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1,5 +1,5 @@ lwl-y += lowlevel.o -lwl-y += common.o +obj-y += common.o obj-$(CONFIG_ARCH_ARMADA_370) += armada-370-xp.o obj-$(CONFIG_ARCH_ARMADA_XP) += armada-370-xp.o obj-$(CONFIG_ARCH_DOVE) += dove.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c index 209be0b60..e416a3876 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.c +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -17,17 +17,9 @@ #include #include #include -#include -#include -#include #include #include -#define CONSOLE_UART_BASE \ - ARMADA_370_XP_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART) - -static struct clk *tclk; - static inline void armada_370_xp_memory_find(unsigned long *phys_base, unsigned long *phys_size) { @@ -51,52 +43,6 @@ static inline void armada_370_xp_memory_find(unsigned long *phys_base, } } -static struct NS16550_plat uart_plat = { - .shift = 2, -}; - -static int armada_370_xp_add_uart(void) -{ - uart_plat.clock = clk_get_rate(tclk); - if (!add_ns16550_device(DEVICE_ID_DYNAMIC, - (unsigned int)CONSOLE_UART_BASE, 32, - IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - &uart_plat)) - return -ENODEV; - return 0; -} - -#if defined(CONFIG_ARCH_ARMADA_370) -static int armada_370_init_clocks(void) -{ - u32 val = readl(ARMADA_370_XP_SAR_BASE + SAR_LOW); - unsigned int rate; - - /* - * On Armada 370, the TCLK frequency can be either - * 166 Mhz or 200 Mhz - */ - if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ) - rate = 200000000; - else - rate = 166000000; - - tclk = clk_fixed("tclk", rate); - return clk_register_clkdev(tclk, NULL, "mvebu-timer"); -} -#define armada_370_xp_init_clocks() armada_370_init_clocks() -#endif - -#if defined(CONFIG_ARCH_ARMADA_XP) -static int armada_xp_init_clocks(void) -{ - /* On Armada XP, the TCLK frequency is always 250 Mhz */ - tclk = clk_fixed("tclk", 250000000); - return 0; -} -#define armada_370_xp_init_clocks() armada_xp_init_clocks() -#endif - static int armada_370_xp_init_soc(void) { unsigned long phys_base, phys_size; @@ -104,14 +50,9 @@ static int armada_370_xp_init_soc(void) barebox_set_model("Marvell Armada 370/XP"); barebox_set_hostname("armada"); - armada_370_xp_init_clocks(); - clkdev_add_physbase(tclk, (unsigned int)ARMADA_370_XP_TIMER_BASE, NULL); - add_generic_device("mvebu-timer", DEVICE_ID_SINGLE, NULL, - (unsigned int)ARMADA_370_XP_TIMER_BASE, 0x30, - IORESOURCE_MEM, NULL); armada_370_xp_memory_find(&phys_base, &phys_size); arm_add_mem_device("ram0", phys_base, phys_size); - armada_370_xp_add_uart(); + return 0; } core_initcall(armada_370_xp_init_soc); diff --git a/arch/arm/mach-mvebu/common.c b/arch/arm/mach-mvebu/common.c index d52b88d71..b054bf5af 100644 --- a/arch/arm/mach-mvebu/common.c +++ b/arch/arm/mach-mvebu/common.c @@ -16,42 +16,66 @@ */ #include +#include #include -#include -#include -#include +#include +#include +#include /* - * All MVEBU SoCs start with internal registers at 0xd0000000. - * To get more contiguous address space and as Linux expects them - * there, we remap them early to 0xf1000000. - * - * There is no way to determine internal registers base address - * safely later on, as the remap register itself is within the - * internal registers. + * Marvell MVEBU SoC id and revision can be read from any PCIe + * controller port. */ -#define MVEBU_BOOTUP_INT_REG_BASE 0xd0000000 -#define MVEBU_BRIDGE_REG_BASE 0x20000 -#define DEVICE_INTERNAL_BASE_ADDR (MVEBU_BRIDGE_REG_BASE + 0x80) +u16 soc_devid; +EXPORT_SYMBOL(soc_devid); +u16 soc_revid; +EXPORT_SYMBOL(soc_revid); -static void mvebu_remap_registers(void) +static const struct of_device_id mvebu_pcie_of_ids[] = { + { .compatible = "marvell,armada-xp-pcie", }, + { .compatible = "marvell,armada-370-pcie", }, + { .compatible = "marvell,dove-pcie" }, + { .compatible = "marvell,kirkwood-pcie" }, + { }, +}; + +#define PCIE_VEN_DEV_ID 0x000 +#define PCIE_REV_ID 0x008 +#define REV_ID_MASK 0xff + +static int mvebu_soc_id_init(void) { - writel(MVEBU_REMAP_INT_REG_BASE, - IOMEM(MVEBU_BOOTUP_INT_REG_BASE) + DEVICE_INTERNAL_BASE_ADDR); -} + struct device_node *np, *cnp; + struct clk *clk; + void __iomem *base; -/* - * Determining the actual memory size is highly SoC dependent, - * but for all SoCs RAM starts at 0x00000000. Therefore, we start - * with a minimal memory setup of 64M and probe correct memory size - * later. - */ -#define MVEBU_BOOTUP_MEMORY_BASE 0x00000000 -#define MVEBU_BOOTUP_MEMORY_SIZE SZ_64M + np = of_find_matching_node(NULL, mvebu_pcie_of_ids); + if (!np) + return -ENODEV; -void __naked __noreturn mvebu_barebox_entry(void *boarddata) -{ - mvebu_remap_registers(); - barebox_arm_entry(MVEBU_BOOTUP_MEMORY_BASE, - MVEBU_BOOTUP_MEMORY_SIZE, boarddata); + for_each_child_of_node(np, cnp) { + base = of_iomap(cnp, 0); + if (!base) + continue; + + clk = of_clk_get(cnp, 0); + if (IS_ERR(clk)) + continue; + + clk_enable(clk); + soc_devid = readl(base + PCIE_VEN_DEV_ID) >> 16; + soc_revid = readl(base + PCIE_REV_ID) & REV_ID_MASK; + clk_disable(clk); + break; + } + + if (!soc_devid) { + pr_err("Unable to read SoC id from PCIe ports\n"); + return -EINVAL; + } + + pr_info("SoC: Marvell %04x rev %d\n", soc_devid, soc_revid); + + return 0; } +postcore_initcall(mvebu_soc_id_init); diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c index f081e50e7..bcbf4b8ad 100644 --- a/arch/arm/mach-mvebu/dove.c +++ b/arch/arm/mach-mvebu/dove.c @@ -71,6 +71,9 @@ static int dove_init_soc(void) { unsigned long phys_base, phys_size; + barebox_set_model("Marvell Dove"); + barebox_set_hostname("dove"); + dove_remap_mc_regs(); dove_memory_find(&phys_base, &phys_size); arm_add_mem_device("ram0", phys_base, phys_size); diff --git a/arch/arm/mach-mvebu/include/mach/socid.h b/arch/arm/mach-mvebu/include/mach/socid.h new file mode 100644 index 000000000..36d681a9d --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/socid.h @@ -0,0 +1,76 @@ +/* + * Marvell MVEBU SoC Ids + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_MVEBU_SOCID_H +#define __MACH_MVEBU_SOCID_H + +extern u16 soc_devid; +extern u16 soc_revid; + +static inline u16 mvebu_get_soc_devid(void) +{ + return soc_devid; +} + +static inline u16 mvebu_get_soc_revid(void) +{ + return soc_revid; +} + +/* Orion */ +#define DEVID_F5180 0x5180 +#define REVID_F5180N_B1 0x3 +#define DEVID_F5181 0x5181 +#define REVID_F5181_B1 0x3 +#define REVID_F5181L 0x8 +#define DEVID_F5182 0x5182 +#define REVID_F5182_A1 0x1 +#define DEVID_F6183 0x6183 +/* Kirkwood */ +#define DEVID_F6180 0x6180 +#define DEVID_F6190 0x6190 +#define DEVID_F6192 0x6192 +#define DEVID_F6280 0x6280 +#define DEVID_F6281 0x6281 +#define DEVID_F6282 0x1155 +/* Kirkwood Duo */ +#define DEVID_F6321 0x6321 +#define DEVID_F6322 0x6322 +#define DEVID_F6323 0x6323 +/* Avanta */ +#define DEVID_F6510 0x6510 +#define DEVID_F6530 0x6530 +#define DEVID_F6550 0x6550 +#define DEVID_F6560 0x6560 +/* Dove */ +#define DEVID_AP510 0x0510 +#define DEVID_F6781 0x6781 +/* Discovery Duo */ +#define DEVID_MV76100 0x7610 +#define DEVID_MV78100 0x7810 +#define DEVID_MV78200 0x7820 +/* Armada 370 */ +#define DEVID_F6707 0x6707 +#define DEVID_F6710 0x6710 +#define DEVID_F6711 0x6711 +/* Armada XP */ +#define DEVID_MV78130 0x7813 +#define DEVID_MV78160 0x7816 +#define DEVID_MV78230 0x7823 +#define DEVID_MV78260 0x7826 +#define DEVID_MV78460 0x7846 +#define DEVID_MV78880 0x7888 + +#endif /* __MACH_MVEBU_SOCID_H */ diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c index c79d13002..fe9ca9cbe 100644 --- a/arch/arm/mach-mvebu/kirkwood.c +++ b/arch/arm/mach-mvebu/kirkwood.c @@ -16,16 +16,9 @@ #include #include #include -#include -#include -#include #include #include -#define CONSOLE_UART_BASE KIRKWOOD_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART) - -static struct clk *tclk; - static inline void kirkwood_memory_find(unsigned long *phys_base, unsigned long *phys_size) { @@ -49,39 +42,6 @@ static inline void kirkwood_memory_find(unsigned long *phys_base, } } -static struct NS16550_plat uart_plat = { - .shift = 2, -}; - -static int kirkwood_add_uart(void) -{ - uart_plat.clock = clk_get_rate(tclk); - if (!add_ns16550_device(DEVICE_ID_DYNAMIC, - (unsigned int)CONSOLE_UART_BASE, 32, - IORESOURCE_MEM | IORESOURCE_MEM_32BIT, - &uart_plat)) - return -ENODEV; - return 0; -} - -static int kirkwood_init_clocks(void) -{ - u32 val = readl(KIRKWOOD_SAR_BASE); - unsigned int rate; - - /* - * On Kirkwood, the TCLK frequency can be either - * 166 Mhz or 200 Mhz - */ - if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ) - rate = 166666667; - else - rate = 200000000; - - tclk = clk_fixed("tclk", rate); - return 0; -} - static int kirkwood_init_soc(void) { unsigned long phys_base, phys_size; @@ -89,14 +49,8 @@ static int kirkwood_init_soc(void) barebox_set_model("Marvell Kirkwood"); barebox_set_hostname("kirkwood"); - kirkwood_init_clocks(); - clkdev_add_physbase(tclk, (unsigned int)KIRKWOOD_TIMER_BASE, NULL); - add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL, - (unsigned int)KIRKWOOD_TIMER_BASE, 0x30, - IORESOURCE_MEM, NULL); kirkwood_memory_find(&phys_base, &phys_size); arm_add_mem_device("ram0", phys_base, phys_size); - kirkwood_add_uart(); return 0; } diff --git a/arch/arm/mach-mvebu/lowlevel.c b/arch/arm/mach-mvebu/lowlevel.c index 147a717ad..7c4facfa1 100644 --- a/arch/arm/mach-mvebu/lowlevel.c +++ b/arch/arm/mach-mvebu/lowlevel.c @@ -16,9 +16,11 @@ */ #include +#include #include #include #include +#include #include void __naked barebox_arm_reset_vector(void) @@ -26,3 +28,38 @@ void __naked barebox_arm_reset_vector(void) arm_cpu_lowlevel_init(); mvebu_barebox_entry(NULL); } + +/* + * All MVEBU SoCs start with internal registers at 0xd0000000. + * To get more contiguous address space and as Linux expects them + * there, we remap them early to 0xf1000000. + * + * There is no way to determine internal registers base address + * safely later on, as the remap register itself is within the + * internal registers. + */ +#define MVEBU_BOOTUP_INT_REG_BASE 0xd0000000 +#define MVEBU_BRIDGE_REG_BASE 0x20000 +#define DEVICE_INTERNAL_BASE_ADDR (MVEBU_BRIDGE_REG_BASE + 0x80) + +static void mvebu_remap_registers(void) +{ + writel(MVEBU_REMAP_INT_REG_BASE, + IOMEM(MVEBU_BOOTUP_INT_REG_BASE) + DEVICE_INTERNAL_BASE_ADDR); +} + +/* + * Determining the actual memory size is highly SoC dependent, + * but for all SoCs RAM starts at 0x00000000. Therefore, we start + * with a minimal memory setup of 64M and probe correct memory size + * later. + */ +#define MVEBU_BOOTUP_MEMORY_BASE 0x00000000 +#define MVEBU_BOOTUP_MEMORY_SIZE SZ_64M + +void __naked __noreturn mvebu_barebox_entry(void *boarddata) +{ + mvebu_remap_registers(); + barebox_arm_entry(MVEBU_BOOTUP_MEMORY_BASE, + MVEBU_BOOTUP_MEMORY_SIZE, boarddata); +} diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c index d189c6ca5..8d02ed93d 100644 --- a/drivers/clk/mvebu/armada-370.c +++ b/drivers/clk/mvebu/armada-370.c @@ -37,8 +37,8 @@ static const struct coreclk_ratio a370_coreclk_ratios[] = { }; static const u32 a370_tclk_freqs[] = { - 16600000, - 20000000, + 166000000, + 200000000, }; static u32 a370_get_tclk_freq(void __iomem *sar) diff --git a/drivers/clocksource/mvebu.c b/drivers/clocksource/mvebu.c index e0c85edaa..e5cb921d9 100644 --- a/drivers/clocksource/mvebu.c +++ b/drivers/clocksource/mvebu.c @@ -19,24 +19,27 @@ #include #include -#define TIMER_CTRL_OFF 0x0000 -#define TIMER0_EN 0x0001 -#define TIMER0_RELOAD_EN 0x0002 -#define TIMER0_25MHZ 0x0800 -#define TIMER0_DIV(div) ((div) << 19) -#define TIMER1_EN 0x0004 -#define TIMER1_RELOAD_EN 0x0008 -#define TIMER1_25MHZ 0x1000 -#define TIMER1_DIV(div) ((div) << 22) -#define TIMER_EVENTS_STATUS 0x0004 -#define TIMER0_CLR_MASK (~0x1) -#define TIMER1_CLR_MASK (~0x100) -#define TIMER0_RELOAD_OFF 0x0010 -#define TIMER0_VAL_OFF 0x0014 -#define TIMER1_RELOAD_OFF 0x0018 -#define TIMER1_VAL_OFF 0x001c +#define TIMER_CTRL_OFF 0x0000 +#define TIMER0_EN BIT(0) +#define TIMER0_RELOAD_EN BIT(1) +#define TIMER0_25MHZ BIT(11) +#define TIMER0_DIV(div) ((div) << 19) +#define TIMER0_DIV_MASK TIMER0_DIV(0x7) +#define TIMER1_EN BIT(2) +#define TIMER1_RELOAD_EN BIT(3) +#define TIMER1_25MHZ BIT(12) +#define TIMER1_DIV(div) ((div) << 22) +#define TIMER1_DIV_MASK TIMER1_DIV(0x7) +#define TIMER_EVENTS_STATUS 0x0004 +#define TIMER0_CLR_MASK (~BIT(0)) +#define TIMER1_CLR_MASK (~BIT(9)) +#define TIMER0_RELOAD_OFF 0x0010 +#define TIMER0_VAL_OFF 0x0014 +#define TIMER1_RELOAD_OFF 0x0018 +#define TIMER1_VAL_OFF 0x001c -#define TIMER_DIVIDER_SHIFT 5 +#define TIMER_DIVIDER_SHIFT 5 +#define TIMER_DIVIDER BIT(TIMER_DIVIDER_SHIFT) static __iomem void *timer_base; @@ -53,24 +56,35 @@ static struct clocksource cs = { static int mvebu_timer_probe(struct device_d *dev) { - struct clk *tclk; - u32 val; + struct clk *clk; + u32 rate, div, val; timer_base = dev_request_mem_region(dev, 0); - tclk = clk_get(dev, NULL); val = __raw_readl(timer_base + TIMER_CTRL_OFF); - val &= ~TIMER0_25MHZ; + val &= ~(TIMER0_25MHZ | TIMER0_DIV_MASK); + if (of_device_is_compatible(dev->device_node, + "marvell,armada-370-timer")) { + clk = clk_get(dev, NULL); + div = TIMER_DIVIDER; + val |= TIMER0_DIV(TIMER_DIVIDER_SHIFT); + rate = clk_get_rate(clk) / TIMER_DIVIDER; + } else { + clk = clk_get(dev, "fixed"); + div = 1; + val |= TIMER0_25MHZ; + rate = clk_get_rate(clk); + } __raw_writel(val, timer_base + TIMER_CTRL_OFF); __raw_writel(0xffffffff, timer_base + TIMER0_VAL_OFF); __raw_writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); val = __raw_readl(timer_base + TIMER_CTRL_OFF); - val |= TIMER0_EN | TIMER0_RELOAD_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); + val |= TIMER0_EN | TIMER0_RELOAD_EN; __raw_writel(val, timer_base + TIMER_CTRL_OFF); - cs.mult = clocksource_hz2mult(clk_get_rate(tclk), cs.shift); + cs.mult = clocksource_hz2mult(rate, cs.shift); init_clock(&cs); @@ -78,7 +92,8 @@ static int mvebu_timer_probe(struct device_d *dev) } static struct of_device_id mvebu_timer_dt_ids[] = { - { .compatible = "marvell,armada-370-xp-timer", }, + { .compatible = "marvell,armada-370-timer", }, + { .compatible = "marvell,armada-xp-timer", }, { } }; diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index c4525cbff..45f77a759 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -15,6 +15,9 @@ config OFDEVICE select DTC bool "Enable probing of devices from the devicetree" +config OF_ADDRESS_PCI + bool + config OF_NET depends on NET def_bool y diff --git a/drivers/of/address.c b/drivers/of/address.c index 4cacdb1cf..b3cbb1545 100644 --- a/drivers/of/address.c +++ b/drivers/of/address.c @@ -108,11 +108,94 @@ static unsigned int of_bus_default_get_flags(const __be32 *addr) return IORESOURCE_MEM; } +#ifdef CONFIG_OF_ADDRESS_PCI +/* + * PCI bus specific translator + */ + +static int of_bus_pci_match(struct device_node *np) +{ + return !of_property_match_string(np, "device_type", "pci"); +} + +static void of_bus_pci_count_cells(struct device_node *np, + int *addrc, int *sizec) +{ + if (addrc) + *addrc = 3; + if (sizec) + *sizec = 2; +} + +static unsigned int of_bus_pci_get_flags(const __be32 *addr) +{ + unsigned int flags = 0; + u32 w = be32_to_cpup(addr); + + switch ((w >> 24) & 0x03) { + case 0x01: + flags |= IORESOURCE_IO; + break; + case 0x02: /* 32 bits */ + case 0x03: /* 64 bits */ + flags |= IORESOURCE_MEM; + break; + } + if (w & 0x40000000) + flags |= IORESOURCE_PREFETCH; + return flags; +} + +static u64 of_bus_pci_map(__be32 *addr, const __be32 *range, int na, int ns, + int pna) +{ + u64 cp, s, da; + unsigned int af, rf; + + af = of_bus_pci_get_flags(addr); + rf = of_bus_pci_get_flags(range); + + /* Check address type match */ + if ((af ^ rf) & (IORESOURCE_MEM | IORESOURCE_IO)) + return OF_BAD_ADDR; + + /* Read address values, skipping high cell */ + cp = of_read_number(range + 1, na - 1); + s = of_read_number(range + na + pna, ns); + da = of_read_number(addr + 1, na - 1); + + pr_debug("OF: PCI map, cp=%llx, s=%llx, da=%llx\n", + (unsigned long long)cp, (unsigned long long)s, + (unsigned long long)da); + + if (da < cp || da >= (cp + s)) + return OF_BAD_ADDR; + return da - cp; +} + +static int of_bus_pci_translate(__be32 *addr, u64 offset, int na) +{ + return of_bus_default_translate(addr + 1, offset, na - 1); +} +#endif /* CONFIG_OF_ADDRESS_PCI */ + /* * Array of bus specific translators */ static struct of_bus of_busses[] = { +#ifdef CONFIG_OF_ADDRESS_PCI + /* PCI */ + { + .name = "pci", + .addresses = "assigned-addresses", + .match = of_bus_pci_match, + .count_cells = of_bus_pci_count_cells, + .map = of_bus_pci_map, + .translate = of_bus_pci_translate, + .get_flags = of_bus_pci_get_flags, + }, +#endif /* Default */ { .name = "default", diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 421525b30..dffaa4eeb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -46,3 +46,5 @@ config PINCTRL_TEGRA30 bool help The pinmux controller found on the Tegra 30+ line of SoCs. + +source drivers/pinctrl/mvebu/Kconfig diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 3978c5692..566ba111d 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -6,3 +6,5 @@ obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o + +obj-$(CONFIG_ARCH_MVEBU) += mvebu/ diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig new file mode 100644 index 000000000..f5cf60804 --- /dev/null +++ b/drivers/pinctrl/mvebu/Kconfig @@ -0,0 +1,7 @@ +config PINCTRL_DOVE + bool + select PINCTRL + +config PINCTRL_KIRKWOOD + bool + select PINCTRL diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile new file mode 100644 index 000000000..05f320d5a --- /dev/null +++ b/drivers/pinctrl/mvebu/Makefile @@ -0,0 +1,3 @@ +obj-y += common.o +obj-$(CONFIG_ARCH_DOVE) += dove.o +obj-$(CONFIG_ARCH_KIRKWOOD) += kirkwood.o diff --git a/drivers/pinctrl/mvebu/common.c b/drivers/pinctrl/mvebu/common.c new file mode 100644 index 000000000..532705286 --- /dev/null +++ b/drivers/pinctrl/mvebu/common.c @@ -0,0 +1,115 @@ +/* + * Marvell MVEBU pinctrl core driver + * + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "common.h" + +struct mvebu_pinctrl { + struct mvebu_pinctrl_soc_info *soc; + struct pinctrl_device pinctrl; +}; + +static struct mvebu_mpp_mode *mvebu_pinctrl_find_mode_by_name( + struct mvebu_pinctrl *pctl, const char *name) +{ + unsigned n; + for (n = 0; n < pctl->soc->nmodes; n++) { + if (strcmp(name, pctl->soc->modes[n].name) == 0) + return &pctl->soc->modes[n]; + } + return NULL; +} + +static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name( + struct mvebu_pinctrl *pctl, struct mvebu_mpp_mode *mode, + const char *name) +{ + struct mvebu_mpp_ctrl_setting *setting = mode->settings; + + while (setting->name) { + if (strcmp(name, setting->name) == 0) { + if (!pctl->soc->variant || + (pctl->soc->variant & setting->variant)) + return setting; + } + setting++; + } + return NULL; +} + +static int mvebu_pinctrl_set_state(struct pinctrl_device *pdev, + struct device_node *np) +{ + struct mvebu_pinctrl *pctl = + container_of(pdev, struct mvebu_pinctrl, pinctrl); + struct property *prop; + const char *function; + const char *group; + int ret; + + ret = of_property_read_string(np, "marvell,function", &function); + if (ret) { + dev_err(pdev->dev, "missing marvell,function in node %s\n", + np->full_name); + return -EINVAL; + } + + of_property_for_each_string(np, "marvell,pins", prop, group) { + struct mvebu_mpp_mode *mode = + mvebu_pinctrl_find_mode_by_name(pctl, group); + struct mvebu_mpp_ctrl_setting *set; + + if (!mode) { + dev_err(pdev->dev, "unknown pin group %s", group); + continue; + } + + set = mvebu_pinctrl_find_setting_by_name(pctl, mode, function); + if (!set) { + dev_err(pdev->dev, "unsupported function %s on pin %s", + function, group); + continue; + } + + dev_dbg(pdev->dev, "np = %s, mode = %s, setting = %s (%s)\n", + np->name, mode->name, set->name, set->subname); + + mode->mpp_set(mode->pid, set->val); + } + + return 0; +} + +static struct pinctrl_ops mvebu_pinctrl_ops = { + .set_state = mvebu_pinctrl_set_state, +}; + +int mvebu_pinctrl_probe(struct device_d *dev, + struct mvebu_pinctrl_soc_info *soc) +{ + struct mvebu_pinctrl *pctl; + int ret; + + pctl = xzalloc(sizeof(*pctl)); + pctl->soc = soc; + pctl->pinctrl.dev = dev; + pctl->pinctrl.ops = &mvebu_pinctrl_ops; + + ret = pinctrl_register(&pctl->pinctrl); + if (ret) + free(pctl); + + return ret; +} diff --git a/drivers/pinctrl/mvebu/common.h b/drivers/pinctrl/mvebu/common.h new file mode 100644 index 000000000..8b3c74852 --- /dev/null +++ b/drivers/pinctrl/mvebu/common.h @@ -0,0 +1,146 @@ +/* + * Marvell MVEBU pinctrl driver + * + * Authors: Sebastian Hesselbarth + * Thomas Petazzoni + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __PINCTRL_MVEBU_H__ +#define __PINCTRL_MVEBU_H__ + +#include + +/** + * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting + * @val: ctrl setting value + * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode + * @subname: (optional) additional ctrl setting name, e.g. rts, cts + * @variant: (optional) variant identifier mask + * @flags: (private) flags to store gpi/gpo/gpio capabilities + * + * A ctrl_setting describes a specific internal mux function that a mpp pin + * can be switched to. The value (val) will be written in the corresponding + * register for common mpp pin configuration registers on MVEBU. SoC specific + * mpp_get/_set function may use val to distinguish between different settings. + * + * The name will be used to switch to this setting in DT description, e.g. + * marvell,function = "uart2". subname is only for debugging purposes. + * + * If name is one of "gpi", "gpo", "gpio" gpio capabilities are + * parsed during initialization and stored in flags. + * + * The variant can be used to combine different revisions of one SoC to a + * common pinctrl driver. It is matched (AND) with variant of soc_info to + * determine if a setting is available on the current SoC revision. + */ +struct mvebu_mpp_ctrl_setting { + u8 val; + const char *name; + const char *subname; + u8 variant; + u8 flags; +#define MVEBU_SETTING_GPO (1 << 0) +#define MVEBU_SETTING_GPI (1 << 1) +}; + +/** + * struct mvebu_mpp_mode - link ctrl and settings + * @pid: first pin id handled by this mode + * @name: name of the mpp group + * @mpp_get: function to get mpp setting + * @mpp_set: function to set mpp setting + * @settings: list of settings available for this mode + * + * A mode connects all available settings with the corresponding mpp_ctrl + * given by pid. + */ +struct mvebu_mpp_mode { + u8 pid; + const char *name; + int (*mpp_get)(unsigned pid, unsigned long *config); + int (*mpp_set)(unsigned pid, unsigned long config); + struct mvebu_mpp_ctrl_setting *settings; +}; + +/** + * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu + * @variant: variant mask of soc_info + * @controls: list of available mvebu_mpp_ctrls + * @ncontrols: number of available mvebu_mpp_ctrls + * @modes: list of available mvebu_mpp_modes + * @nmodes: number of available mvebu_mpp_modes + * @gpioranges: list of pinctrl_gpio_ranges + * @ngpioranges: number of available pinctrl_gpio_ranges + * + * This struct describes all pinctrl related information for a specific SoC. + * If variant is unequal 0 it will be matched (AND) with variant of each + * setting and allows to distinguish between different revisions of one SoC. + */ +struct mvebu_pinctrl_soc_info { + u8 variant; + struct mvebu_mpp_mode *modes; + int nmodes; +}; + +#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ + { \ + .val = _val, \ + .name = _name, \ + .subname = _subname, \ + .variant = _mask, \ + .flags = 0, \ + } + +#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \ + _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) + +#define MPP_FUNCTION(_val, _name, _subname) \ + MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1) + +#define MPP_MODE(_id, _name, _func, ...) \ + { \ + .pid = _id, \ + .name = _name, \ + .mpp_get = _func ## _get, \ + .mpp_set = _func ## _set, \ + .settings = (struct mvebu_mpp_ctrl_setting[]){ \ + __VA_ARGS__, { } }, \ + } + +#define MVEBU_MPPS_PER_REG 8 +#define MVEBU_MPP_BITS 4 +#define MVEBU_MPP_MASK 0xf + +static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid, + unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + + *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK; + + return 0; +} + +static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid, + unsigned long config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long reg; + + reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift); + writel(reg | (config << shift), base + off); + + return 0; +} + +int mvebu_pinctrl_probe(struct device_d *dev, + struct mvebu_pinctrl_soc_info *soc); + +#endif diff --git a/drivers/pinctrl/mvebu/dove.c b/drivers/pinctrl/mvebu/dove.c new file mode 100644 index 000000000..bd0a632f1 --- /dev/null +++ b/drivers/pinctrl/mvebu/dove.c @@ -0,0 +1,739 @@ +/* + * Marvell Dove pinctrl driver based on mvebu pinctrl core + * + * Author: Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "common.h" + +/* Internal registers can be configured at any 1 MiB aligned address */ +#define INT_REGS_MASK (SZ_1M - 1) +#define PMU_REGS_OFFS 0xd802c + +/* MPP Base registers */ +#define PMU_MPP_GENERAL_CTRL 0x10 +#define AU0_AC97_SEL BIT(16) + +/* MPP Control 4 register */ +#define SPI_GPIO_SEL BIT(5) +#define UART1_GPIO_SEL BIT(4) +#define AU1_GPIO_SEL BIT(3) +#define CAM_GPIO_SEL BIT(2) +#define SD1_GPIO_SEL BIT(1) +#define SD0_GPIO_SEL BIT(0) + +/* PMU Signal Select registers */ +#define PMU_SIGNAL_SELECT_0 0x00 +#define PMU_SIGNAL_SELECT_1 0x04 + +/* Global Config regmap registers */ +#define GLOBAL_CONFIG_1 0x00 +#define TWSI_ENABLE_OPTION1 BIT(7) +#define GLOBAL_CONFIG_2 0x04 +#define TWSI_ENABLE_OPTION2 BIT(20) +#define TWSI_ENABLE_OPTION3 BIT(21) +#define TWSI_OPTION3_GPIO BIT(22) +#define SSP_CTRL_STATUS_1 0x08 +#define SSP_ON_AU1 BIT(0) +#define MPP_GENERAL_CONFIG 0x10 +#define AU1_SPDIFO_GPIO_EN BIT(1) +#define NAND_GPIO_EN BIT(0) + +#define CONFIG_PMU BIT(4) + +static void __iomem *mpp_base; +static void __iomem *mpp4_base; +static void __iomem *pmu_base; +static void __iomem *gconf_base; + +static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int dove_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long func; + + if ((pmu & BIT(pid)) == 0) + return default_mpp_ctrl_get(mpp_base, pid, config); + + func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); + *config = (func >> shift) & MVEBU_MPP_MASK; + *config |= CONFIG_PMU; + + return 0; +} + +static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS; + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + unsigned long func; + + if ((config & CONFIG_PMU) == 0) { + writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); + return default_mpp_ctrl_set(mpp_base, pid, config); + } + + writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL); + func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off); + func &= ~(MVEBU_MPP_MASK << shift); + func |= (config & MVEBU_MPP_MASK) << shift; + writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off); + + return 0; +} + +static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned long mpp4 = readl(mpp4_base); + unsigned long mask; + + switch (pid) { + case 24: /* mpp_camera */ + mask = CAM_GPIO_SEL; + break; + case 40: /* mpp_sdio0 */ + mask = SD0_GPIO_SEL; + break; + case 46: /* mpp_sdio1 */ + mask = SD1_GPIO_SEL; + break; + case 58: /* mpp_spi0 */ + mask = SPI_GPIO_SEL; + break; + case 62: /* mpp_uart1 */ + mask = UART1_GPIO_SEL; + break; + default: + return -EINVAL; + } + + *config = ((mpp4 & mask) != 0); + + return 0; +} + +static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned long mpp4 = readl(mpp4_base); + unsigned long mask; + + switch (pid) { + case 24: /* mpp_camera */ + mask = CAM_GPIO_SEL; + break; + case 40: /* mpp_sdio0 */ + mask = SD0_GPIO_SEL; + break; + case 46: /* mpp_sdio1 */ + mask = SD1_GPIO_SEL; + break; + case 58: /* mpp_spi0 */ + mask = SPI_GPIO_SEL; + break; + case 62: /* mpp_uart1 */ + mask = UART1_GPIO_SEL; + break; + default: + return -EINVAL; + } + + mpp4 &= ~mask; + if (config) + mpp4 |= mask; + + writel(mpp4, mpp4_base); + + return 0; +} + +static int dove_nand_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned int gmpp; + + gmpp = readl(gconf_base + MPP_GENERAL_CONFIG); + *config = ((gmpp & NAND_GPIO_EN) != 0); + + return 0; +} + +static int dove_nand_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned int gmpp; + + gmpp = readl(gconf_base + MPP_GENERAL_CONFIG); + gmpp &= ~NAND_GPIO_EN; + if (config) + gmpp |= NAND_GPIO_EN; + writel(gmpp, gconf_base + MPP_GENERAL_CONFIG); + + return 0; +} + +static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + + *config = ((pmu & AU0_AC97_SEL) != 0); + + return 0; +} + +static int dove_audio0_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL); + + pmu &= ~AU0_AC97_SEL; + if (config) + pmu |= AU0_AC97_SEL; + writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL); + + return 0; +} + +static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned int mpp4 = readl(mpp4_base); + unsigned int sspc1; + unsigned int gmpp; + unsigned int gcfg2; + + sspc1 = readl(gconf_base + SSP_CTRL_STATUS_1); + gmpp = readl(gconf_base + MPP_GENERAL_CONFIG); + gcfg2 = readl(gconf_base + GLOBAL_CONFIG_2); + + *config = 0; + if (mpp4 & AU1_GPIO_SEL) + *config |= BIT(3); + if (sspc1 & SSP_ON_AU1) + *config |= BIT(2); + if (gmpp & AU1_SPDIFO_GPIO_EN) + *config |= BIT(1); + if (gcfg2 & TWSI_OPTION3_GPIO) + *config |= BIT(0); + + /* SSP/TWSI only if I2S1 not set*/ + if ((*config & BIT(3)) == 0) + *config &= ~(BIT(2) | BIT(0)); + /* TWSI only if SPDIFO not set*/ + if ((*config & BIT(1)) == 0) + *config &= ~BIT(0); + + return 0; +} + +static int dove_audio1_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned int reg = readl(mpp4_base); + + reg &= ~AU1_GPIO_SEL; + if (config & BIT(3)) + reg |= AU1_GPIO_SEL; + writel(reg, mpp4_base); + + reg = readl(gconf_base + SSP_CTRL_STATUS_1); + reg &= ~SSP_ON_AU1; + if (config & BIT(2)) + reg |= SSP_ON_AU1; + + reg = readl(gconf_base + MPP_GENERAL_CONFIG); + reg &= ~AU1_SPDIFO_GPIO_EN; + if (config & BIT(1)) + reg |= AU1_SPDIFO_GPIO_EN; + + reg = readl(gconf_base + GLOBAL_CONFIG_2); + reg &= ~TWSI_OPTION3_GPIO; + if (config & BIT(0)) + reg |= TWSI_OPTION3_GPIO; + + return 0; +} + +static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config) +{ + unsigned int gcfg1 = readl(gconf_base + GLOBAL_CONFIG_1); + unsigned int gcfg2 = readl(gconf_base + GLOBAL_CONFIG_2); + + *config = 0; + if (gcfg1 & TWSI_ENABLE_OPTION1) + *config = 1; + else if (gcfg2 & TWSI_ENABLE_OPTION2) + *config = 2; + else if (gcfg2 & TWSI_ENABLE_OPTION3) + *config = 3; + + return 0; +} + +static int dove_twsi_ctrl_set(unsigned pid, unsigned long config) +{ + unsigned int gcfg1 = readl(gconf_base + GLOBAL_CONFIG_1); + unsigned int gcfg2 = readl(gconf_base + GLOBAL_CONFIG_2); + + gcfg1 &= ~TWSI_ENABLE_OPTION1; + gcfg2 &= ~(TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3); + + switch (config) { + case 1: + gcfg1 = TWSI_ENABLE_OPTION1; + break; + case 2: + gcfg2 = TWSI_ENABLE_OPTION2; + break; + case 3: + gcfg2 = TWSI_ENABLE_OPTION3; + break; + } + + writel(gcfg1, gconf_base + GLOBAL_CONFIG_1); + writel(gcfg2, gconf_base + GLOBAL_CONFIG_2); + + return 0; +} + +static struct mvebu_mpp_mode dove_mpp_modes[] = { + MPP_MODE(0, "mpp0", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart2", "rts"), + MPP_FUNCTION(0x03, "sdio0", "cd"), + MPP_FUNCTION(0x0f, "lcd0", "pwm"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(1, "mpp1", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart2", "cts"), + MPP_FUNCTION(0x03, "sdio0", "wp"), + MPP_FUNCTION(0x0f, "lcd1", "pwm"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(2, "mpp2", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "sata", "prsnt"), + MPP_FUNCTION(0x02, "uart2", "txd"), + MPP_FUNCTION(0x03, "sdio0", "buspwr"), + MPP_FUNCTION(0x04, "uart1", "rts"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(3, "mpp3", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "sata", "act"), + MPP_FUNCTION(0x02, "uart2", "rxd"), + MPP_FUNCTION(0x03, "sdio0", "ledctrl"), + MPP_FUNCTION(0x04, "uart1", "cts"), + MPP_FUNCTION(0x0f, "lcd-spi", "cs1"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(4, "mpp4", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "rts"), + MPP_FUNCTION(0x03, "sdio1", "cd"), + MPP_FUNCTION(0x04, "spi1", "miso"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(5, "mpp5", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "cts"), + MPP_FUNCTION(0x03, "sdio1", "wp"), + MPP_FUNCTION(0x04, "spi1", "cs"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(6, "mpp6", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "txd"), + MPP_FUNCTION(0x03, "sdio1", "buspwr"), + MPP_FUNCTION(0x04, "spi1", "mosi"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(7, "mpp7", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "rxd"), + MPP_FUNCTION(0x03, "sdio1", "ledctrl"), + MPP_FUNCTION(0x04, "spi1", "sck"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "core-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(8, "mpp8", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "watchdog", "rstout"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(9, "mpp9", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x05, "pex1", "clkreq"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(10, "mpp10", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x05, "ssp", "sclk"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(11, "mpp11", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "sata", "prsnt"), + MPP_FUNCTION(0x02, "sata-1", "act"), + MPP_FUNCTION(0x03, "sdio0", "ledctrl"), + MPP_FUNCTION(0x04, "sdio1", "ledctrl"), + MPP_FUNCTION(0x05, "pex0", "clkreq"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(12, "mpp12", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "sata", "act"), + MPP_FUNCTION(0x02, "uart2", "rts"), + MPP_FUNCTION(0x03, "audio0", "extclk"), + MPP_FUNCTION(0x04, "sdio1", "cd"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(13, "mpp13", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart2", "cts"), + MPP_FUNCTION(0x03, "audio1", "extclk"), + MPP_FUNCTION(0x04, "sdio1", "wp"), + MPP_FUNCTION(0x05, "ssp", "extclk"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(14, "mpp14", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart2", "txd"), + MPP_FUNCTION(0x04, "sdio1", "buspwr"), + MPP_FUNCTION(0x05, "ssp", "rxd"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(15, "mpp15", dove_pmu_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart2", "rxd"), + MPP_FUNCTION(0x04, "sdio1", "ledctrl"), + MPP_FUNCTION(0x05, "ssp", "sfrm"), + MPP_FUNCTION(CONFIG_PMU | 0x0, "pmu-nc", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x1, "pmu-low", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x2, "pmu-high", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x3, "pmic", "sdi"), + MPP_FUNCTION(CONFIG_PMU | 0x4, "cpu-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x5, "standby-pwr-down", NULL), + MPP_FUNCTION(CONFIG_PMU | 0x8, "cpu-pwr-good", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xa, "bat-fault", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xb, "ext0-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xc, "ext1-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xd, "ext2-wakeup", NULL), + MPP_FUNCTION(CONFIG_PMU | 0xe, "pmu-blink", NULL)), + MPP_MODE(16, "mpp16", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "rts"), + MPP_FUNCTION(0x03, "sdio0", "cd"), + MPP_FUNCTION(0x04, "lcd-spi", "cs1"), + MPP_FUNCTION(0x05, "ac97", "sdi1")), + MPP_MODE(17, "mpp17", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "ac97-1", "sysclko"), + MPP_FUNCTION(0x02, "uart3", "cts"), + MPP_FUNCTION(0x03, "sdio0", "wp"), + MPP_FUNCTION(0x04, "twsi", "sda"), + MPP_FUNCTION(0x05, "ac97", "sdi2")), + MPP_MODE(18, "mpp18", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "txd"), + MPP_FUNCTION(0x03, "sdio0", "buspwr"), + MPP_FUNCTION(0x04, "lcd0", "pwm"), + MPP_FUNCTION(0x05, "ac97", "sdi3")), + MPP_MODE(19, "mpp19", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "uart3", "rxd"), + MPP_FUNCTION(0x03, "sdio0", "ledctrl"), + MPP_FUNCTION(0x04, "twsi", "sck")), + MPP_MODE(20, "mpp20", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "ac97", "sysclko"), + MPP_FUNCTION(0x02, "lcd-spi", "miso"), + MPP_FUNCTION(0x03, "sdio1", "cd"), + MPP_FUNCTION(0x05, "sdio0", "cd"), + MPP_FUNCTION(0x06, "spi1", "miso")), + MPP_MODE(21, "mpp21", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "uart1", "rts"), + MPP_FUNCTION(0x02, "lcd-spi", "cs0"), + MPP_FUNCTION(0x03, "sdio1", "wp"), + MPP_FUNCTION(0x04, "ssp", "sfrm"), + MPP_FUNCTION(0x05, "sdio0", "wp"), + MPP_FUNCTION(0x06, "spi1", "cs")), + MPP_MODE(22, "mpp22", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x01, "uart1", "cts"), + MPP_FUNCTION(0x02, "lcd-spi", "mosi"), + MPP_FUNCTION(0x03, "sdio1", "buspwr"), + MPP_FUNCTION(0x04, "ssp", "txd"), + MPP_FUNCTION(0x05, "sdio0", "buspwr"), + MPP_FUNCTION(0x06, "spi1", "mosi")), + MPP_MODE(23, "mpp23", dove_mpp_ctrl, + MPP_FUNCTION(0x00, "gpio", NULL), + MPP_FUNCTION(0x02, "lcd-spi", "sck"), + MPP_FUNCTION(0x03, "sdio1", "ledctrl"), + MPP_FUNCTION(0x04, "ssp", "sclk"), + MPP_FUNCTION(0x05, "sdio0", "ledctrl"), + MPP_FUNCTION(0x06, "spi1", "sck")), + MPP_MODE(24, "mpp_camera", dove_mpp4_ctrl, + MPP_FUNCTION(0x00, "camera", NULL), + MPP_FUNCTION(0x01, "gpio", NULL)), + MPP_MODE(40, "mpp_sdio0", dove_mpp4_ctrl, + MPP_FUNCTION(0x00, "sdio0", NULL), + MPP_FUNCTION(0x01, "gpio", NULL)), + MPP_MODE(46, "mpp_sdio1", dove_mpp4_ctrl, + MPP_FUNCTION(0x00, "sdio1", NULL), + MPP_FUNCTION(0x01, "gpio", NULL)), + MPP_MODE(52, "mpp_audio1", dove_audio1_ctrl, + MPP_FUNCTION(0x00, "i2s1/spdifo", NULL), + MPP_FUNCTION(0x02, "i2s1", NULL), + MPP_FUNCTION(0x08, "spdifo", NULL), + MPP_FUNCTION(0x0a, "gpio", NULL), + MPP_FUNCTION(0x0b, "twsi", NULL), + MPP_FUNCTION(0x0c, "ssp/spdifo", NULL), + MPP_FUNCTION(0x0e, "ssp", NULL), + MPP_FUNCTION(0x0f, "ssp/twsi", NULL)), + MPP_MODE(58, "mpp_spi0", dove_mpp4_ctrl, + MPP_FUNCTION(0x00, "spi0", NULL), + MPP_FUNCTION(0x01, "gpio", NULL)), + MPP_MODE(62, "mpp_uart1", dove_mpp4_ctrl, + MPP_FUNCTION(0x00, "uart1", NULL), + MPP_FUNCTION(0x01, "gpio", NULL)), + MPP_MODE(64, "mpp_nand", dove_nand_ctrl, + MPP_FUNCTION(0x00, "nand", NULL), + MPP_FUNCTION(0x01, "gpo", NULL)), + MPP_MODE(72, "audio0", dove_audio0_ctrl, + MPP_FUNCTION(0x00, "i2s", NULL), + MPP_FUNCTION(0x01, "ac97", NULL)), + MPP_MODE(73, "twsi", dove_twsi_ctrl, + MPP_FUNCTION(0x00, "twsi-none", NULL), + MPP_FUNCTION(0x01, "twsi-opt1", NULL), + MPP_FUNCTION(0x02, "twsi-opt2", NULL), + MPP_FUNCTION(0x03, "twsi-opt3", NULL)), +}; + +static struct mvebu_pinctrl_soc_info dove_pinctrl_info = { + .modes = dove_mpp_modes, + .nmodes = ARRAY_SIZE(dove_mpp_modes), + .variant = 0, +}; + +static struct of_device_id dove_pinctrl_of_match[] = { + { + .compatible = "marvell,dove-pinctrl", + .data = (u32)&dove_pinctrl_info + }, + { } +}; + +static int dove_pinctrl_probe(struct device_d *dev) +{ + const struct of_device_id *match = + of_match_node(dove_pinctrl_of_match, dev->device_node); + struct mvebu_pinctrl_soc_info *soc = + (struct mvebu_pinctrl_soc_info *)match->data; + struct device_node *np; + struct clk *clk; + + clk = clk_get(dev, NULL); + clk_enable(clk); + + mpp_base = dev_request_mem_region(dev, 0); + mpp4_base = dev_request_mem_region(dev, 1); + if (!mpp_base || !mpp4_base) + return -EBUSY; + + /* + * Dove PMU does not have a stable binding, yet. + * Derive pmu_base from mpp_base until proper binding is + * available. + */ + pmu_base = (void *)((u32)mpp_base & ~INT_REGS_MASK) + PMU_REGS_OFFS; + + np = of_find_compatible_node(NULL, NULL, "marvell,dove-global-config"); + if (!np) + return -ENODEV; + gconf_base = of_iomap(np, 0); + + return mvebu_pinctrl_probe(dev, soc); +} + +static struct driver_d dove_pinctrl_driver = { + .name = "pinctrl-dove", + .probe = dove_pinctrl_probe, + .of_compatible = dove_pinctrl_of_match, +}; + +static int dove_pinctrl_init(void) +{ + return platform_driver_register(&dove_pinctrl_driver); +} +postcore_initcall(dove_pinctrl_init); diff --git a/drivers/pinctrl/mvebu/kirkwood.c b/drivers/pinctrl/mvebu/kirkwood.c new file mode 100644 index 000000000..94ab10544 --- /dev/null +++ b/drivers/pinctrl/mvebu/kirkwood.c @@ -0,0 +1,456 @@ +/* + * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core + * + * Sebastian Hesselbarth + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +#include "common.h" + +static void __iomem *mpp_base; + +static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config) +{ + return default_mpp_ctrl_get(mpp_base, pid, config); +} + +static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config) +{ + return default_mpp_ctrl_set(mpp_base, pid, config); +} + +#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ + ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ + (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) + +enum kirkwood_variant { + VARIANT_MV88F6180 = V(1, 0, 0, 0, 0, 0), + VARIANT_MV88F6190 = V(0, 1, 0, 0, 0, 0), + VARIANT_MV88F6192 = V(0, 0, 1, 0, 0, 0), + VARIANT_MV88F6281 = V(0, 0, 0, 1, 0, 0), + VARIANT_MV88F6282 = V(0, 0, 0, 0, 1, 0), + VARIANT_MV98DX4122 = V(0, 0, 0, 0, 0, 1), +}; + +static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = { + MPP_MODE(0, "mpp0", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io2", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1))), + MPP_MODE(1, "mpp1", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io3", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1))), + MPP_MODE(2, "mpp2", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io4", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1))), + MPP_MODE(3, "mpp3", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io5", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1))), + MPP_MODE(4, "mpp4", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io6", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0))), + MPP_MODE(5, "mpp5", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io7", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "ptp", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(6, "mpp6", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x1, "sysrst", "out", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "mosi", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0))), + MPP_MODE(7, "mpp7", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V(1, 1, 1, 1, 0, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "cs", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "ptp", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(8, "mpp8", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "twsi0", "sda", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "clk", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))), + MPP_MODE(9, "mpp9", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "twsi0", "sck", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "evreq", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))), + MPP_MODE(10, "mpp10", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "sck", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0X3, "uart0", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xc, "ptp", "trig", V(1, 1, 1, 1, 0, 0))), + MPP_MODE(11, "mpp11", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "spi", "miso", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart0", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xc, "ptp-2", "trig", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0xd, "ptp", "clk", V(1, 1, 1, 1, 0, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0))), + MPP_MODE(12, "mpp12", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 0, 1, 0)), + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0x1, "sdio", "clk", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "spi", "mosi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(13, "mpp13", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "cmd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "pwm", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(14, "mpp14", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d0", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x4, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "audio-1", "sdi", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "col", V(1, 1, 1, 1, 1, 0))), + MPP_MODE(15, "mpp15", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d1", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "uart0", "rts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "spi", "cs", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(16, "mpp16", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "sdio", "d2", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "uart0", "cts", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "extclk", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "mii", "crs", V(1, 1, 1, 1, 1, 0))), + MPP_MODE(17, "mpp17", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "sdio", "d3", V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xd, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(18, "mpp18", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io0", V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "pex", "clkreq", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(19, "mpp19", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(1, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "nand", "io1", V(1, 1, 1, 1, 1, 1))), + MPP_MODE(20, "mpp20", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd0", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d0", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(1, 0, 0, 0, 0, 0))), + MPP_MODE(21, "mpp21", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd1", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d1", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(22, "mpp22", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd2", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "prsnt", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d2", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(23, "mpp23", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txd3", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "prsnt", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d3", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(24, "mpp24", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd0", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d4", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(25, "mpp25", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd1", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d5", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(26, "mpp26", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd2", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d6", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(27, "mpp27", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxd3", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d7", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(28, "mpp28", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "col", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d8", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(29, "mpp29", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(1, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txclk", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d9", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(30, "mpp30", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxctl", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d10", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(31, "mpp31", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxclk", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d11", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(32, "mpp32", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txclko", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d12", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(33, "mpp33", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txctl", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d13", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(34, "mpp34", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "txen", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata1", "act", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d14", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(35, "mpp35", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 1, 1, 1, 1, 1)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql", V(0, 0, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x3, "ge1", "rxerr", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "sata0", "act", V(0, 1, 1, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d15", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xc, "mii", "rxerr", V(0, 1, 1, 1, 1, 0))), + MPP_MODE(36, "mpp36", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp0", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "twsi1", "sda", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(37, "mpp37", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp1", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "twsi1", "sck", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(38, "mpp38", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp2", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "rmclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d18", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(39, "mpp39", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp3", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "bclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d19", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(40, "mpp40", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp4", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdo", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d20", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(41, "mpp41", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp5", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "lrclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d21", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(42, "mpp42", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp6", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "mclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d22", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(43, "mpp43", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp7", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "int", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "sdi", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d23", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(44, "mpp44", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp8", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rst", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "clk", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(45, "mpp45", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 1)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "pclk", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "e", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(46, "mpp46", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp10", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "fs", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "hsync", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(47, "mpp47", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp11", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "drx", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "vsync", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(48, "mpp48", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp12", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "dtx", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d16", V(0, 0, 0, 0, 1, 0))), + MPP_MODE(49, "mpp49", kirkwood_mpp_ctrl, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V(0, 0, 0, 1, 0, 1)), + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0x1, "ts", "mp9", V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql", V(0, 0, 0, 1, 1, 0)), + MPP_VAR_FUNCTION(0x5, "ptp", "clk", V(0, 0, 0, 1, 0, 0)), + MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0)), + MPP_VAR_FUNCTION(0xb, "lcd", "d17", V(0, 0, 0, 0, 1, 0))), +}; + +static struct mvebu_pinctrl_soc_info mv88f6180_info = { + .variant = VARIANT_MV88F6180, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct mvebu_pinctrl_soc_info mv88f6190_info = { + .variant = VARIANT_MV88F6190, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct mvebu_pinctrl_soc_info mv88f6192_info = { + .variant = VARIANT_MV88F6192, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct mvebu_pinctrl_soc_info mv88f6281_info = { + .variant = VARIANT_MV88F6281, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct mvebu_pinctrl_soc_info mv88f6282_info = { + .variant = VARIANT_MV88F6282, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct mvebu_pinctrl_soc_info mv98dx4122_info = { + .variant = VARIANT_MV98DX4122, + .modes = mv88f6xxx_mpp_modes, + .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes), +}; + +static struct of_device_id kirkwood_pinctrl_of_match[] = { + { + .compatible = "marvell,88f6180-pinctrl", + .data = (u32)&mv88f6180_info + }, + { + .compatible = "marvell,88f6190-pinctrl", + .data = (u32)&mv88f6190_info + }, + { + .compatible = "marvell,88f6192-pinctrl", + .data = (u32)&mv88f6192_info + }, + { + .compatible = "marvell,88f6281-pinctrl", + .data = (u32)&mv88f6281_info + }, + { + .compatible = "marvell,88f6282-pinctrl", + .data = (u32)&mv88f6282_info + }, + { + .compatible = "marvell,98dx4122-pinctrl", + .data = (u32)&mv98dx4122_info + }, + { } +}; + +static int kirkwood_pinctrl_probe(struct device_d *dev) +{ + const struct of_device_id *match = + of_match_node(kirkwood_pinctrl_of_match, dev->device_node); + struct mvebu_pinctrl_soc_info *soc = + (struct mvebu_pinctrl_soc_info *)match->data; + + mpp_base = dev_request_mem_region(dev, 0); + if (!mpp_base) + return -EBUSY; + + return mvebu_pinctrl_probe(dev, soc); +} + +static struct driver_d kirkwood_pinctrl_driver = { + .name = "pinctrl-kirkwood", + .probe = kirkwood_pinctrl_probe, + .of_compatible = kirkwood_pinctrl_of_match, +}; + +static int kirkwood_pinctrl_init(void) +{ + return platform_driver_register(&kirkwood_pinctrl_driver); +} +postcore_initcall(kirkwood_pinctrl_init); diff --git a/images/Makefile.mvebu b/images/Makefile.mvebu index fe92cc2f5..009807d7c 100644 --- a/images/Makefile.mvebu +++ b/images/Makefile.mvebu @@ -11,16 +11,74 @@ $(obj)/%.kwbuartimg: $(obj)/% FORCE board = $(srctree)/arch/$(ARCH)/boards +KWBOPTS = -c -d 0x1000000 -e 0x1000000 + +# ----------------------- Armada 370 based boards --------------------------- +GLOBALSCALE_MIRABOX_KWBOPTS = ${KWBOPTS} -i $(board)/globalscale-mirabox/kwbimage.cfg +OPTS_start_globalscale_mirabox.pblx.kwbimg = $(GLOBALSCALE_MIRABOX_KWBOPTS) +OPTS_start_globalscale_mirabox.pblx.kwbuartimg = -m uart $(GLOBALSCALE_MIRABOX_KWBOPTS) +FILE_barebox-globalscale-mirabox.img = start_globalscale_mirabox.pblx.kwbimg +FILE_barebox-globalscale-mirabox-uart.img = start_globalscale_mirabox.pblx.kwbuartimg +FILE_barebox-globalscale-mirabox-2nd.img = start_globalscale_mirabox.pblx +pblx-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += start_globalscale_mirabox +image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox.img +image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-uart.img +image-$(CONFIG_MACH_GLOBALSCALE_MIRABOX) += barebox-globalscale-mirabox-2nd.img + +# ----------------------- Armada XP based boards --------------------------- +PLATHOME_OPENBLOCKS_AX3_KWBOPTS = ${KWBOPTS} -i $(board)/plathome-openblocks-ax3/kwbimage.cfg +OPTS_start_plathome_openblocks_ax3.pblx.kwbimg = $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS) +OPTS_start_plathome_openblocks_ax3.pblx.kwbuartimg = -m uart $(PLATHOME_OPENBLOCKS_AX3_KWBOPTS) +FILE_barebox-plathome-openblocks-ax3.img = start_plathome_openblocks_ax3.pblx.kwbimg +FILE_barebox-plathome-openblocks-ax3-uart.img = start_plathome_openblocks_ax3.pblx.kwbuartimg +FILE_barebox-plathome-openblocks-ax3-2nd.img = start_plathome_openblocks_ax3.pblx +pblx-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += start_plathome_openblocks_ax3 +image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3.img +image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-uart.img +image-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += barebox-plathome-openblocks-ax3-2nd.img + +MARVELL_ARMADA_XP_GP_KWBOPTS = ${KWBOPTS} -i $(board)/marvell-armada-xp-gp/kwbimage.cfg +OPTS_start_marvell_armada_xp_gp.pblx.kwbimg = $(MARVELL_ARMADA_XP_GP_KWBOPTS) +OPTS_start_marvell_armada_xp_gp.pblx.kwbuartimg = -m uart $(MARVELL_ARMADA_XP_GP_KWBOPTS) +FILE_barebox-marvell-armada-xp-gp.img = start_marvell_armada_xp_gp.pblx.kwbimg +FILE_barebox-marvell-armada-xp-gp-uart.img = start_marvell_armada_xp_gp.pblx.kwbuartimg +FILE_barebox-marvell-armada-xp-gp-2nd.img = start_marvell_armada_xp_gp.pblx +pblx-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += start_marvell_armada_xp_gp +image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp.img +image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp-uart.img +image-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += barebox-marvell-armada-xp-gp-2nd.img + # ----------------------- Dove 88AP510 based boards --------------------------- -SOLIDRUN_CUBOX_KWBOPTS = -c -i $(board)/solidrun-cubox/kwbimage.cfg -d 0x1000000 -e 0x1000000 -pblx-$(CONFIG_MACH_SOLIDRUN_CUBOX) += start_solidrun_cubox +SOLIDRUN_CUBOX_KWBOPTS = ${KWBOPTS} -i $(board)/solidrun-cubox/kwbimage.cfg OPTS_start_solidrun_cubox.pblx.kwbimg = $(SOLIDRUN_CUBOX_KWBOPTS) -FILE_barebox-solidrun-cubox.img = start_solidrun_cubox.pblx.kwbimg -image-$(CONFIG_MACH_SOLIDRUN_CUBOX) += barebox-solidrun-cubox.img - OPTS_start_solidrun_cubox.pblx.kwbuartimg = -m uart $(SOLIDRUN_CUBOX_KWBOPTS) +FILE_barebox-solidrun-cubox.img = start_solidrun_cubox.pblx.kwbimg FILE_barebox-solidrun-cubox-uart.img = start_solidrun_cubox.pblx.kwbuartimg -image-$(CONFIG_MACH_SOLIDRUN_CUBOX) += barebox-solidrun-cubox-uart.img - FILE_barebox-solidrun-cubox-2nd.img = start_solidrun_cubox.pblx +pblx-$(CONFIG_MACH_SOLIDRUN_CUBOX) += start_solidrun_cubox +image-$(CONFIG_MACH_SOLIDRUN_CUBOX) += barebox-solidrun-cubox.img +image-$(CONFIG_MACH_SOLIDRUN_CUBOX) += barebox-solidrun-cubox-uart.img image-$(CONFIG_MACH_SOLIDRUN_CUBOX) += barebox-solidrun-cubox-2nd.img + +# ----------------------- Kirkwood based boards --------------------------- +GLOBALSCALE_GURUPLUG_KWBOPTS = ${KWBOPTS} -i $(board)/globalscale-guruplug/kwbimage.cfg +OPTS_start_globalscale_guruplug.pblx.kwbimg = $(GLOBALSCALE_GURUPLUG_KWBOPTS) +OPTS_start_globalscale_guruplug.pblx.kwbuartimg = -m uart $(GLOBALSCALE_GURUPLUG_KWBOPTS) +FILE_barebox-globalscale-guruplug.img = start_globalscale_guruplug.pblx.kwbimg +FILE_barebox-globalscale-guruplug-uart.img = start_globalscale_guruplug.pblx.kwbuartimg +FILE_barebox-globalscale-guruplug-2nd.img = start_globalscale_guruplug.pblx +pblx-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += start_globalscale_guruplug +image-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += barebox-globalscale-guruplug.img +image-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += barebox-globalscale-guruplug-uart.img +image-$(CONFIG_MACH_GLOBALSCALE_GURUPLUG) += barebox-globalscale-guruplug-2nd.img + +USI_TOPKICK_KWBOPTS = ${KWBOPTS} -i $(board)/usi-topkick/kwbimage.cfg +OPTS_start_usi_topkick.pblx.kwbimg = $(USI_TOPKICK_KWBOPTS) +OPTS_start_usi_topkick.pblx.kwbuartimg = -m uart $(USI_TOPKICK_KWBOPTS) +FILE_barebox-usi-topkick.img = start_usi_topkick.pblx.kwbimg +FILE_barebox-usi-topkick-uart.img = start_usi_topkick.pblx.kwbuartimg +FILE_barebox-usi-topkick-2nd.img = start_usi_topkick.pblx +pblx-$(CONFIG_MACH_USI_TOPKICK) += start_usi_topkick +image-$(CONFIG_MACH_USI_TOPKICK) += barebox-usi-topkick.img +image-$(CONFIG_MACH_USI_TOPKICK) += barebox-usi-topkick-uart.img +image-$(CONFIG_MACH_USI_TOPKICK) += barebox-usi-topkick-2nd.img