net: fec_imx: refactor R_CNTRL setup
Introduce a variable which gets updated when needed and only written once. Will make further additions easier. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -274,6 +274,7 @@ static int fec_set_hwaddr(struct eth_device *dev, unsigned char *mac)
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static int fec_init(struct eth_device *dev)
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{
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struct fec_priv *fec = (struct fec_priv *)dev->priv;
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u32 rcntl;
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/*
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* Clear FEC-Lite interrupt event register(IEVENT)
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@ -288,17 +289,9 @@ static int fec_init(struct eth_device *dev)
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/*
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* Set FEC-Lite receive control register(R_CNTRL):
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*/
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if (fec->xcv_type == SEVENWIRE) {
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/*
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* Frame length=1518; 7-wire mode
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*/
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writel(FEC_R_CNTRL_MAX_FL(1518), fec->regs + FEC_R_CNTRL);
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} else {
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/*
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* Frame length=1518; MII mode;
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*/
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writel(FEC_R_CNTRL_MAX_FL(1518) | FEC_R_CNTRL_MII_MODE,
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fec->regs + FEC_R_CNTRL);
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rcntl = FEC_R_CNTRL_MAX_FL(1518);
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if (fec->xcv_type != SEVENWIRE) {
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rcntl |= FEC_R_CNTRL_MII_MODE;
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/*
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* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
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* and do not drop the Preamble.
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@ -309,13 +302,10 @@ static int fec_init(struct eth_device *dev)
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if (fec->xcv_type == RMII) {
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if (cpu_is_mx28()) {
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/* just another way to enable RMII */
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uint32_t reg = readl(fec->regs + FEC_R_CNTRL);
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writel(reg | FEC_R_CNTRL_RMII_MODE
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rcntl |= FEC_R_CNTRL_RMII_MODE;
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/* the linux driver add these bits, why not we? */
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/* | FEC_R_CNTRL_FCE | */
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/* FEC_R_CNTRL_NO_LGTH_CHECK */,
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fec->regs + FEC_R_CNTRL);
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/* FEC_R_CNTRL_NO_LGTH_CHECK */
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} else {
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/* disable the gasket and wait */
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writel(0, fec->regs + FEC_MIIGSK_ENR);
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@ -329,6 +319,7 @@ static int fec_init(struct eth_device *dev)
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writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR);
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}
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}
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writel(rcntl, fec->regs + FEC_R_CNTRL);
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/*
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* Set Opcode/Pause Duration Register
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