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barebox
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Merge branch 'next'

This commit is contained in:
Sascha Hauer 2011-06-06 11:29:45 +02:00
parent b65e45eccd cbf46b2dad
commit 6e27bfb15e
29 changed files with 2463 additions and 1 deletions
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1
arch/arm/Makefile
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@ -57,6 +57,7 @@ machine-$(CONFIG_ARCH_VERSATILE) := versatile
# by CONFIG_* macro name.
board-$(CONFIG_MACH_A9M2410) := a9m2410
board-$(CONFIG_MACH_A9M2440) := a9m2440
board-$(CONFIG_MACH_AT91RM9200EK) := at91rm9200ek
board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek
board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek
board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek

1
arch/arm/boards/at91rm9200ek/Makefile Normal file
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@ -0,0 +1 @@
obj-y += init.o

68
arch/arm/boards/at91rm9200ek/config.h Normal file
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@ -0,0 +1,68 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#define MASTER_PLL_MUL 39
#define MASTER_PLL_DIV 4
/* clocks */
#define CONFIG_SYS_MOR_VAL \
(AT91_PMC_MOSCEN | \
(255 << 8)) /* Main Oscillator Start-up Time */
#define CONFIG_SYS_PLLAR_VAL \
(AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
(0x3e << 8) | /* PLL Counter */ \
(0 << 14) | /* Divider A */ \
((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
/* PCK/2 = MCK Master Clock from SLOW */
#define CONFIG_SYS_MCKR2_VAL1 \
(AT91_PMC_CSS_SLOW | \
AT91RM9200_PMC_MDIV_2) \
/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
#define CONFIG_SYS_MCKR2_VAL2 \
(AT91_PMC_CSS_PLLA | \
AT91_PMC_PRES_1 | \
AT91RM9200_PMC_MDIV_3 |\
AT91_PMC_PDIV_1)
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL \
(AT91_SMC_NWS_(4) | /* Number of Wait States */ \
AT91_SMC_WSEN | /* Wait State Enable */ \
AT91_SMC_TDF_(2) | /* Data Float Time */ \
AT91_SMC_BAT | /* Byte Access Type */ \
AT91_SMC_DBW_16) /* Data Bus Width */
/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL \
(AT91_EBI_CS0A_SMC | \
AT91_EBI_CS1A_SDRAMC | \
AT91_EBI_CS3A_SMC | \
AT91_EBI_CS4A_SMC) \
/* SDRAM */
/* SDRAMC_MR Mode register */
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
(AT91_SDRAMC_NC_9 | \
AT91_SDRAMC_NR_12 | \
AT91_SDRAMC_NB_4 | \
AT91_SDRAMC_CAS_2 | \
(1 << 8) | /* Write Recovery Delay */ \
(12 << 12) | /* Row Cycle Delay */ \
(8 << 16) | /* Row Precharge Delay */ \
(8 << 20) | /* Row to Column Delay */ \
(1 << 24) | /* Active to Precharge Delay */ \
(2 << 28)) /* Exit Self Refresh to Active Delay */
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
#endif /* __CONFIG_H */

41
arch/arm/boards/at91rm9200ek/env/config vendored Normal file
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@ -0,0 +1,41 @@
#!/bin/sh
# use 'dhcp' to do dhcp in barebox and in kernel
# use 'none' if you want to skip kernel ip autoconfiguration
ip=dhcp
# or set your networking parameters here
#eth0.ipaddr=a.b.c.d
#eth0.netmask=a.b.c.d
#eth0.gateway=a.b.c.d
#eth0.serverip=a.b.c.d
# can be either 'nfs', 'tftp' or 'nor'
kernel_loc=tftp
# can be either 'net', 'nor' or 'initrd'
rootfs_loc=net
# can be either 'jffs2' or 'ubifs'
rootfs_type=ubifs
rootfsimage=root.$rootfs_type
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
#kernelimage_type=zimage
#kernelimage=zImage
kernelimage_type=uimage
kernelimage=uImage
#kernelimage_type=raw
#kernelimage=Image
#kernelimage_type=raw_lzo
#kernelimage=Image.lzo
nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)"
rootfs_mtdblock_nor=3
autoboot_timeout=3
bootargs="console=ttyS0,115200"
# set a fancy prompt (if support is compiled in)
PS1="\e[1;31m[barebox@\h]:\w\e[0m\n# "

77
arch/arm/boards/at91rm9200ek/init.c Normal file
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@ -0,0 +1,77 @@
/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <net.h>
#include <init.h>
#include <environment.h>
#include <asm/armlinux.h>
#include <generated/mach-types.h>
#include <partition.h>
#include <fs.h>
#include <fcntl.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/io.h>
static struct device_d cfi_dev = {
.id = 0,
.name = "cfi_flash",
.map_base = AT91_CHIPSELECT_0,
};
static struct at91_ether_platform_data ether_pdata = {
.flags = AT91SAM_ETHER_RMII,
.phy_addr = 0,
};
static int at91rm9200ek_devices_init(void)
{
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
at91_set_gpio_output(AT91_PIN_PA23, 1);
at91_add_device_sdram(64 * 1024 * 1024);
at91_add_device_eth(&ether_pdata);
register_device(&cfi_dev);
#if defined(CONFIG_DRIVER_CFI) || defined(CONFIG_DRIVER_CFI_OLD)
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
#endif
armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100));
armlinux_set_architecture(MACH_TYPE_AT91RM9200EK);
return 0;
}
device_initcall(at91rm9200ek_devices_init);
static int at91rm9200ek_console_init(void)
{
at91_register_uart(0, 0);
return 0;
}
console_initcall(at91rm9200ek_console_init);

28
arch/arm/boards/mini2440/Kconfig Normal file
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@ -0,0 +1,28 @@
if MACH_MINI2440
config MINI2440_VIDEO
bool
select VIDEO
select DRIVER_VIDEO_S3C
config MINI2440_VIDEO_N35
bool "Support N35 display (240x320)"
select MINI2440_VIDEO
help
This adds support for NEC 3.5 inch TFT display,
the most common one used with MINI2440 board.
config MINI2440_VIDEO_A70
bool "Support A70 display (800x480)"
select MINI2440_VIDEO
help
This adds support for Innolux 7.0 inch TFT display.
config MINI2440_VIDEO_SVGA
bool "Support SVGA video adapter"
select MINI2440_VIDEO
help
This adds support for MINI2440 SVGA (1024x768) video output adapter.
endif

74
arch/arm/boards/mini2440/mini2440.c
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@ -34,6 +34,7 @@
#include <dm9000.h>
#include <nand.h>
#include <mci.h>
#include <fb.h>
#include <asm/armlinux.h>
#include <asm/io.h>
#include <mach/gpio.h>
@ -41,6 +42,7 @@
#include <mach/s3c24x0-nand.h>
#include <mach/s3c24xx-generic.h>
#include <mach/mci.h>
#include <mach/fb.h>
static struct memory_platform_data ram_pdata = {
.name = "ram0",
@ -99,6 +101,77 @@ static struct device_d mci_dev = {
.platform_data = &mci_data,
};
static struct fb_videomode s3c24x0_fb_modes[] = {
#ifdef CONFIG_MINI2440_VIDEO_N35
{
.name = "N35",
.refresh = 60,
.xres = 240,
.left_margin = 21,
.right_margin = 38,
.hsync_len = 6,
.yres = 320,
.upper_margin = 4,
.lower_margin = 4,
.vsync_len = 2,
.pixclock = 115913,
.sync = FB_SYNC_USE_PWREN,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
#endif
#ifdef CONFIG_MINI2440_VIDEO_A70
{
.name = "A70",
.refresh = 50,
.xres = 800,
.left_margin = 40,
.right_margin = 40,
.hsync_len = 48,
.yres = 480,
.upper_margin = 29,
.lower_margin = 3,
.vsync_len = 3,
.pixclock = 41848,
.sync = FB_SYNC_USE_PWREN | FB_SYNC_DE_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
#endif
#ifdef CONFIG_MINI2440_VIDEO_SVGA
{
.name = "SVGA",
.refresh = 24,
.xres = 1024,
.left_margin = 1,
.right_margin = 2,
.hsync_len = 2,
.yres = 768,
.upper_margin = 200,
.lower_margin = 16,
.vsync_len = 16,
.pixclock = 40492,
.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT
/* | FB_SYNC_SWAP_HW */ /* FIXME maybe */ ,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
#endif
};
static struct s3c_fb_platform_data s3c24x0_fb_data = {
.mode_list = s3c24x0_fb_modes,
.mode_cnt = sizeof(s3c24x0_fb_modes) / sizeof(struct fb_videomode),
.bits_per_pixel = 16,
.passive_display = 0,
};
static struct device_d s3cfb_dev = {
.name = "s3c_fb",
.map_base = S3C2410_LCD_BASE,
.platform_data = &s3c24x0_fb_data,
};
static const unsigned pin_usage[] = {
/* address bus, used by NOR, SDRAM */
GPA1_ADDR16,
@ -269,6 +342,7 @@ static int mini2440_devices_init(void)
dev_add_bb_dev("env_raw", "env0");
#endif
register_device(&mci_dev);
register_device(&s3cfb_dev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100);
armlinux_set_architecture(MACH_TYPE_MINI2440);

47
arch/arm/configs/at91rm9200ek_defconfig Normal file
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@ -0,0 +1,47 @@
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_PROMPT="9200-EK:"
CONFIG_LONGHELP=y
CONFIG_GLOB=y
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_MENU=y
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91rm9200ek/env"
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_PASSWD=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MTEST=y
CONFIG_CMD_MTEST_ALTERNATIVE=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNLZO=y
# CONFIG_SPI is not set
CONFIG_DRIVER_CFI=y
# CONFIG_DRIVER_CFI_INTEL is not set
# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set
# CONFIG_DRIVER_CFI_BANK_WIDTH_4 is not set
CONFIG_CFI_BUFFER_WRITE=y
CONFIG_MTD=y
CONFIG_UBI=y
CONFIG_FS_CRAMFS=y
CONFIG_SHA1=y
CONFIG_SHA256=y

27
arch/arm/mach-at91/Kconfig
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@ -6,6 +6,7 @@ config ARCH_TEXT_BASE
default 0x23f00000
config BOARDINFO
default "Atmel at91rm9200-ek" if MACH_AT91RM9200EK
default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260EK
default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK
default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK
@ -25,6 +26,14 @@ comment "Atmel AT91 System-on-Chip"
choice
prompt "Atmel AT91 Processor"
config ARCH_AT91RM9200
bool "AT91RM9200"
select CPU_ARM920T
select HAS_AT91_ETHER
select ARCH_HAS_LOWLEVEL_INIT
select MACH_HAS_LOWLEVEL_INIT
select MACH_DO_LOWLEVEL_INIT
config ARCH_AT91SAM9260
bool "AT91SAM9260"
select CPU_ARM926T
@ -57,6 +66,24 @@ endchoice
# ----------------------------------------------------------
if ARCH_AT91RM9200
choice
prompt "AT91RM9200 Board Type"
config MACH_AT91RM9200EK
bool "Atmel AT91RM9200-EK Evaluation Kit"
help
Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
endchoice
endif
# ----------------------------------------------------------
if ARCH_AT91SAM9260
choice

5
arch/arm/mach-at91/Makefile
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@ -1,8 +1,11 @@
obj-y += clock.o gpio.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
lowlevel_init-y = at91sam926x_lowlevel_init.o
lowlevel_init-$(CONFIG_ARCH_AT91RM9200) = at91rm9200_lowlevel_init.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += $(lowlevel_init-y)
# CPU-specific support
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o

245
arch/arm/mach-at91/at91rm9200.c Normal file
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@ -0,0 +1,245 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
#include "clock.h"
#include "generic.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91RM9200_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91RM9200_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ether_clk = {
.name = "ether_clk",
.pmc_mask = 1 << AT91RM9200_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
.name = "mci_clk",
.pmc_mask = 1 << AT91RM9200_ID_MCI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91RM9200_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91RM9200_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91RM9200_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91RM9200_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91RM9200_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
.name = "spi_clk",
.pmc_mask = 1 << AT91RM9200_ID_SPI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
.name = "pioD_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
.name = "ssc2_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
.name = "tc3_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
.name = "tc4_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
.name = "tc5_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&pioD_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&mmc_clk,
&udc_clk,
&twi_clk,
&spi_clk,
&ssc0_clk,
&ssc1_clk,
&ssc2_clk,
&tc0_clk,
&tc1_clk,
&tc2_clk,
&tc3_clk,
&tc4_clk,
&tc5_clk,
&ohci_clk,
&ether_clk,
// irq0 .. irq6
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91rm9200_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91rm9200_gpio[] = {
{
.id = AT91RM9200_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91RM9200_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91RM9200_ID_PIOC,
.offset = AT91_PIOC,
.clock = &pioC_clk,
}, {
.id = AT91RM9200_ID_PIOD,
.offset = AT91_PIOD,
.clock = &pioD_clk,
}
};
/* --------------------------------------------------------------------
* AT91RM9200 processor initialization
* -------------------------------------------------------------------- */
static int __init at91rm9200_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
/* Register the processor-specific clocks */
at91rm9200_register_clocks();
/* Initialize GPIO subsystem */
at91_gpio_init(at91rm9200_gpio, ARRAY_SIZE(at91rm9200_gpio));
return 0;
}
core_initcall(at91rm9200_initialize);

276
arch/arm/mach-at91/at91rm9200_devices.c Normal file
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@ -0,0 +1,276 @@
/*
* arch/arm/mach-at91/at91rm9200_devices.c
*
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
* Copyright (C) 2005 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <common.h>
#include <asm/armlinux.h>
#include <mach/hardware.h>
#include <mach/at91rm9200.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/io.h>
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.id = -1,
.name = "mem",
.map_base = AT91_CHIPSELECT_1,
.platform_data = &ram_pdata,
};
void at91_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
}
/* --------------------------------------------------------------------
* Ethernet
* -------------------------------------------------------------------- */
#if defined(CONFIG_DRIVER_NET_AT91_ETHER)
static struct device_d at91rm9200_eth_device = {
.id = 0,
.name = "at91_ether",
.map_base = AT91_VA_BASE_EMAC,
.size = 0x1000,
};
void __init at91_add_device_eth(struct at91_ether_platform_data *data)
{
if (!data)
return;
/* Pins used for MII and RMII */
at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
if (!(data->flags & AT91SAM_ETHER_RMII)) {
at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
}
at91rm9200_eth_device.platform_data = data;
register_device(&at91rm9200_eth_device);
}
#else
void __init at91_add_device_eth(struct at91_ether_platform_data *data) {}
#endif
/* --------------------------------------------------------------------
* NAND / SmartMedia
* -------------------------------------------------------------------- */
#if defined(CONFIG_NAND_ATMEL)
static struct device_d at91rm9200_nand_device = {
.id = -1,
.name = "atmel_nand",
.map_base = AT91_CHIPSELECT_3,
.size = 0x10,
};
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned int csa;
if (!data)
return;
/* enable the address range of CS3 */
csa = at91_sys_read(AT91_EBI_CSA);
at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
| AT91_SMC_NWS_(5)
| AT91_SMC_TDF_(1)
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
| AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
);
/* enable pin */
if (data->enable_pin)
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
if (data->rdy_pin)
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
at91rm9200_nand_device.platform_data = data;
platform_device_register(&at91rm9200_nand_device);
}
#else
void __init at91_add_device_nand(struct atmel_nand_data *data) {}
#endif
/* --------------------------------------------------------------------
* UART
* -------------------------------------------------------------------- */
static struct device_d dbgu_serial_device = {
.id = 0,
.name = "atmel_serial",
.map_base = (AT91_BASE_SYS + AT91_DBGU),
.size = 4096,
};
static inline void configure_dbgu_pins(void)
{
at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
}
static struct device_d uart0_serial_device = {
.id = 1,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US0,
.size = 4096,
};
static inline void configure_usart0_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
if (pins & ATMEL_UART_CTS)
at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
if (pins & ATMEL_UART_RTS) {
/*
* AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
* We need to drive the pin manually. Default is off (RTS is active low).
*/
at91_set_gpio_output(AT91_PIN_PA21, 1);
}
}
static struct device_d uart1_serial_device = {
.id = 2,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US1,
.size = 4096,
};
static inline void configure_usart1_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
if (pins & ATMEL_UART_RI)
at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
if (pins & ATMEL_UART_DTR)
at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
if (pins & ATMEL_UART_DCD)
at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
if (pins & ATMEL_UART_CTS)
at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
if (pins & ATMEL_UART_DSR)
at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
if (pins & ATMEL_UART_RTS)
at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
}
static struct device_d uart2_serial_device = {
.id = 3,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US2,
.size = 4096,
};
static inline void configure_usart2_pins(unsigned pins)
{
at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
if (pins & ATMEL_UART_CTS)
at91_set_B_periph(AT91_PIN_PA30, 0); /* CTS2 */
if (pins & ATMEL_UART_RTS)
at91_set_B_periph(AT91_PIN_PA31, 0); /* RTS2 */
}
static struct device_d uart3_serial_device = {
.id = 4,
.name = "atmel_serial",
.map_base = AT91RM9200_BASE_US3,
.size = 4096,
};
static inline void configure_usart3_pins(unsigned pins)
{
at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
if (pins & ATMEL_UART_CTS)
at91_set_B_periph(AT91_PIN_PB1, 0); /* CTS3 */
if (pins & ATMEL_UART_RTS)
at91_set_B_periph(AT91_PIN_PB0, 0); /* RTS3 */
}
void __init at91_register_uart(unsigned id, unsigned pins)
{
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
break;
case AT91RM9200_ID_US0:
configure_usart0_pins(pins);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
break;
case AT91RM9200_ID_US1:
configure_usart1_pins(pins);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
break;
case AT91RM9200_ID_US2:
configure_usart2_pins(pins);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
break;
case AT91RM9200_ID_US3:
configure_usart3_pins(pins);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
break;
default:
return;
}
}

146
arch/arm/mach-at91/at91rm9200_lowlevel_init.c Normal file
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/*
* Copyright (C) 2009-2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
*
* Under GPLv2
*/
#include <common.h>
#include <asm/system.h>
#include <asm/barebox-arm.h>
#include <mach/hardware.h>
#include <mach/at91rm9200.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_pio.h>
#include <mach/at91_pmc.h>
#include <mach/io.h>
#include <init.h>
void static inline access_sdram(void)
{
writel(0x00000000, AT91_SDRAM_BASE);
}
void __naked __bare_init arch_init_lowlevel(void)
{
/*
* relocate exception table
*/
__asm__ __volatile__ (
" ldr r0, =exception_vectors\n"
" ldr r1, =0x0\n"
" mov r2, #16\n"
"loopev:\n"
" subs r2, r2, #1\n"
" ldr r3, [r0], #4\n"
" str r3, [r1], #4\n"
" bne loopev\n"
" mov pc, lr\n"
);
}
void __naked __bare_init board_init_lowlevel(void)
{
u32 r;
int i;
/*
* PMC Check if the PLL is already initialized
*/
r = at91_sys_read(AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
do {
r = at91_sys_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
* EBI_CFGR
*/
at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL);
/*
* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
*/
at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL);
/*
* Init Clocks
*/
/*
* PLLAR: x MHz for PCK
*/
at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
do {
r = at91_sys_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
/*
* PCK/x = MCK Master Clock from PLLA
*/
at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
do {
r = at91_sys_read(AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
* Init SDRAM
*/
/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
at91_sys_write(AT91_PIOC + PIO_ASR, CONFIG_SYS_PIOC_ASR_VAL);
/* PIOC_BSR */
at91_sys_write(AT91_PIOC + PIO_BSR, CONFIG_SYS_PIOC_BSR_VAL);
/* PIOC_PDR */
at91_sys_write(AT91_PIOC + PIO_PDR, CONFIG_SYS_PIOC_PDR_VAL);
/* EBI_CSA : CS1=SDRAM */
at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
/* SDRC_CR */
at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
/* SDRC_MR : Precharge All */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
/* access SDRAM */
access_sdram();
/* SDRC_MR : refresh */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRC_MR : Load Mode Register */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
/* access SDRAM */
access_sdram();
/* SDRC_TR : Write refresh rate */
at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL);
/* access SDRAM */
access_sdram();
/* SDRC_MR : Normal Mode */
at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
/* access SDRAM */
access_sdram();
/* switch from FastBus to Asynchronous clock mode */
r = get_cr();
r |= 0xC0000000; /* set bit 31 (iA) and 30 (nF) */
set_cr(r);
end:
board_init_lowlevel_return();
}

97
arch/arm/mach-at91/at91rm9200_time.c Normal file
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/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <init.h>
#include <clock.h>
#include <mach/hardware.h>
#include <mach/at91_tc.h>
#include <mach/at91_st.h>
#include <mach/at91_pmc.h>
#include <mach/io.h>
#include <asm/io.h>
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
* the updates as seen by the CPU don't seem to be strictly monotonic.
* Waiting until we read the same value twice avoids glitching.
*/
uint64_t at91rm9200_clocksource_read(void)
{
unsigned long x1, x2;
x1 = at91_sys_read(AT91_ST_CRTR);
do {
x2 = at91_sys_read(AT91_ST_CRTR);
if (x1 == x2)
break;
x1 = x2;
} while (1);
return x1;
}
static struct clocksource cs = {
.mask = CLOCKSOURCE_MASK(20),
.read = at91rm9200_clocksource_read,
.shift = 10,
};
static int clocksource_init (void)
{
/* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
at91_sys_write(AT91_ST_RTMR, 1);
cs.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, cs.shift);
init_clock(&cs);
return 0;
}
core_initcall(clocksource_init);
/*
* Reset the cpu through the reset controller
*/
void __noreturn reset_cpu (unsigned long ignored)
{
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
/* Not reached */
while (1);
}
EXPORT_SYMBOL(reset_cpu);

0
arch/arm/mach-at91/lowlevel_init.S → arch/arm/mach-at91/at91sam926x_lowlevel_init.S
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49
arch/arm/mach-at91/include/mach/at91_st.h Normal file
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/*
* arch/arm/mach-at91/include/mach/at91_st.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System Timer (ST) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_ST_H
#define AT91_ST_H
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
#endif

146
arch/arm/mach-at91/include/mach/at91_tc.h Normal file
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/*
* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_tc.h]
*
* Copyright (C) SAN People
*
* Timer/Counter Unit (TC) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_TC_H
#define AT91_TC_H
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
#define AT91_TC_TC0XC0S_NONE (1 << 0)
#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
#define AT91_TC_TC1XC1S_NONE (1 << 2)
#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
#define AT91_TC_TC2XC2S_NONE (1 << 4)
#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
#define AT91_TC_CCR 0x00 /* Channel Control Register */
#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
#define AT91_TC_CMR 0x04 /* Channel Mode Register */
#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
#define AT91_TC_TIMER_CLOCK1 (0 << 0)
#define AT91_TC_TIMER_CLOCK2 (1 << 0)
#define AT91_TC_TIMER_CLOCK3 (2 << 0)
#define AT91_TC_TIMER_CLOCK4 (3 << 0)
#define AT91_TC_TIMER_CLOCK5 (4 << 0)
#define AT91_TC_XC0 (5 << 0)
#define AT91_TC_XC1 (6 << 0)
#define AT91_TC_XC2 (7 << 0)
#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
#define AT91_TC_EEVTEDG_NONE (0 << 8)
#define AT91_TC_EEVTEDG_RISING (1 << 8)
#define AT91_TC_EEVTEDG_FALLING (2 << 8)
#define AT91_TC_EEVTEDG_BOTH (3 << 8)
#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
#define AT91_TC_EEVT_TIOB (0 << 10)
#define AT91_TC_EEVT_XC0 (1 << 10)
#define AT91_TC_EEVT_XC1 (2 << 10)
#define AT91_TC_EEVT_XC2 (3 << 10)
#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
#define AT91_TC_WAVESEL_UP (0 << 13)
#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
#define AT91_TC_ACPA_NONE (0 << 16)
#define AT91_TC_ACPA_SET (1 << 16)
#define AT91_TC_ACPA_CLEAR (2 << 16)
#define AT91_TC_ACPA_TOGGLE (3 << 16)
#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
#define AT91_TC_ACPC_NONE (0 << 18)
#define AT91_TC_ACPC_SET (1 << 18)
#define AT91_TC_ACPC_CLEAR (2 << 18)
#define AT91_TC_ACPC_TOGGLE (3 << 18)
#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
#define AT91_TC_AEEVT_NONE (0 << 20)
#define AT91_TC_AEEVT_SET (1 << 20)
#define AT91_TC_AEEVT_CLEAR (2 << 20)
#define AT91_TC_AEEVT_TOGGLE (3 << 20)
#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
#define AT91_TC_ASWTRG_NONE (0 << 22)
#define AT91_TC_ASWTRG_SET (1 << 22)
#define AT91_TC_ASWTRG_CLEAR (2 << 22)
#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
#define AT91_TC_BCPB_NONE (0 << 24)
#define AT91_TC_BCPB_SET (1 << 24)
#define AT91_TC_BCPB_CLEAR (2 << 24)
#define AT91_TC_BCPB_TOGGLE (3 << 24)
#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
#define AT91_TC_BCPC_NONE (0 << 26)
#define AT91_TC_BCPC_SET (1 << 26)
#define AT91_TC_BCPC_CLEAR (2 << 26)
#define AT91_TC_BCPC_TOGGLE (3 << 26)
#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
#define AT91_TC_BEEVT_NONE (0 << 28)
#define AT91_TC_BEEVT_SET (1 << 28)
#define AT91_TC_BEEVT_CLEAR (2 << 28)
#define AT91_TC_BEEVT_TOGGLE (3 << 28)
#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
#define AT91_TC_BSWTRG_NONE (0 << 30)
#define AT91_TC_BSWTRG_SET (1 << 30)
#define AT91_TC_BSWTRG_CLEAR (2 << 30)
#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
#define AT91_TC_CV 0x10 /* Counter Value */
#define AT91_TC_RA 0x14 /* Register A */
#define AT91_TC_RB 0x18 /* Register B */
#define AT91_TC_RC 0x1c /* Register C */
#define AT91_TC_SR 0x20 /* Status Register */
#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
#endif

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/*
* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91rm9200.h]
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
#define AT91RM9200_ID_US0 6 /* USART 0 */
#define AT91RM9200_ID_US1 7 /* USART 1 */
#define AT91RM9200_ID_US2 8 /* USART 2 */
#define AT91RM9200_ID_US3 9 /* USART 3 */
#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
#define AT91RM9200_ID_UDP 11 /* USB Device Port */
#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
#define AT91RM9200_ID_UHP 23 /* USB Host port */
#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
/*
* Peripheral physical base addresses.
*/
#define AT91RM9200_BASE_TCB0 0xfffa0000
#define AT91RM9200_BASE_TC0 0xfffa0000
#define AT91RM9200_BASE_TC1 0xfffa0040
#define AT91RM9200_BASE_TC2 0xfffa0080
#define AT91RM9200_BASE_TCB1 0xfffa4000
#define AT91RM9200_BASE_TC3 0xfffa4000
#define AT91RM9200_BASE_TC4 0xfffa4040
#define AT91RM9200_BASE_TC5 0xfffa4080
#define AT91RM9200_BASE_UDP 0xfffb0000
#define AT91RM9200_BASE_MCI 0xfffb4000
#define AT91RM9200_BASE_TWI 0xfffb8000
#define AT91RM9200_BASE_EMAC 0xfffbc000
#define AT91RM9200_BASE_US0 0xfffc0000
#define AT91RM9200_BASE_US1 0xfffc4000
#define AT91RM9200_BASE_US2 0xfffc8000
#define AT91RM9200_BASE_US3 0xfffcc000
#define AT91RM9200_BASE_SSC0 0xfffd0000
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91_USART0 AT91RM9200_BASE_US0
#define AT91_USART1 AT91RM9200_BASE_US1
#define AT91_USART2 AT91RM9200_BASE_US2
#define AT91_USART3 AT91RM9200_BASE_US3
#define AT91_BASE_SPI AT91RM9200_BASE_SPI
#define AT91_BASE_TWI AT91RM9200_BASE_TWI
#define AT91_ID_UHP AT91RM9200_ID_UHP
#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#define AT91_TC (AT91RM9200_BASE_TC0 - AT91_BASE_SYS)
#define AT91_MATRIX 0 /* not supported */
/*
* Internal Memory.
*/
#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
#define AT91_VA_BASE_EMAC AT91RM9200_BASE_EMAC
/*
* Cpu Name
*/
#define AT91_CPU_NAME "AT91RM9200"
#endif

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/*
* [origin: arch/arm/mach-at91/include/mach/at91rm9200_emac.h]
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Ethernet MAC registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_EMAC_H
#define AT91RM9200_EMAC_H
#define AT91_EMAC_CTL 0x00 /* Control Register */
#define AT91_EMAC_LB (1 << 0) /* Loopback */
#define AT91_EMAC_LBL (1 << 1) /* Loopback Local */
#define AT91_EMAC_RE (1 << 2) /* Receive Enable */
#define AT91_EMAC_TE (1 << 3) /* Transmit Enable */
#define AT91_EMAC_MPE (1 << 4) /* Management Port Enable */
#define AT91_EMAC_CSR (1 << 5) /* Clear Statistics Registers */
#define AT91_EMAC_INCSTAT (1 << 6) /* Increment Statistics Registers */
#define AT91_EMAC_WES (1 << 7) /* Write Enable for Statistics Registers */
#define AT91_EMAC_BP (1 << 8) /* Back Pressure */
#define AT91_EMAC_CFG 0x04 /* Configuration Register */
#define AT91_EMAC_SPD (1 << 0) /* Speed */
#define AT91_EMAC_FD (1 << 1) /* Full Duplex */
#define AT91_EMAC_BR (1 << 2) /* Bit Rate */
#define AT91_EMAC_CAF (1 << 4) /* Copy All Frames */
#define AT91_EMAC_NBC (1 << 5) /* No Broadcast */
#define AT91_EMAC_MTI (1 << 6) /* Multicast Hash Enable */
#define AT91_EMAC_UNI (1 << 7) /* Unicast Hash Enable */
#define AT91_EMAC_BIG (1 << 8) /* Receive 1522 Bytes */
#define AT91_EMAC_EAE (1 << 9) /* External Address Match Enable */
#define AT91_EMAC_CLK (3 << 10) /* MDC Clock Divisor */
#define AT91_EMAC_CLK_DIV8 (0 << 10)
#define AT91_EMAC_CLK_DIV16 (1 << 10)
#define AT91_EMAC_CLK_DIV32 (2 << 10)
#define AT91_EMAC_CLK_DIV64 (3 << 10)
#define AT91_EMAC_RTY (1 << 12) /* Retry Test */
#define AT91_EMAC_RMII (1 << 13) /* Reduce MII (RMII) */
#define AT91_EMAC_SR 0x08 /* Status Register */
#define AT91_EMAC_SR_LINK (1 << 0) /* Link */
#define AT91_EMAC_SR_MDIO (1 << 1) /* MDIO pin */
#define AT91_EMAC_SR_IDLE (1 << 2) /* PHY idle */
#define AT91_EMAC_TAR 0x0c /* Transmit Address Register */
#define AT91_EMAC_TCR 0x10 /* Transmit Control Register */
#define AT91_EMAC_LEN (0x7ff << 0) /* Transmit Frame Length */
#define AT91_EMAC_NCRC (1 << 15) /* No CRC */
#define AT91_EMAC_TSR 0x14 /* Transmit Status Register */
#define AT91_EMAC_TSR_OVR (1 << 0) /* Transmit Buffer Overrun */
#define AT91_EMAC_TSR_COL (1 << 1) /* Collision Occurred */
#define AT91_EMAC_TSR_RLE (1 << 2) /* Retry Limit Exceeded */
#define AT91_EMAC_TSR_IDLE (1 << 3) /* Transmitter Idle */
#define AT91_EMAC_TSR_BNQ (1 << 4) /* Transmit Buffer not Queued */
#define AT91_EMAC_TSR_COMP (1 << 5) /* Transmit Complete */
#define AT91_EMAC_TSR_UND (1 << 6) /* Transmit Underrun */
#define AT91_EMAC_RBQP 0x18 /* Receive Buffer Queue Pointer */
#define AT91_EMAC_RSR 0x20 /* Receive Status Register */
#define AT91_EMAC_RSR_BNA (1 << 0) /* Buffer Not Available */
#define AT91_EMAC_RSR_REC (1 << 1) /* Frame Received */
#define AT91_EMAC_RSR_OVR (1 << 2) /* RX Overrun */
#define AT91_EMAC_ISR 0x24 /* Interrupt Status Register */
#define AT91_EMAC_DONE (1 << 0) /* Management Done */
#define AT91_EMAC_RCOM (1 << 1) /* Receive Complete */
#define AT91_EMAC_RBNA (1 << 2) /* Receive Buffer Not Available */
#define AT91_EMAC_TOVR (1 << 3) /* Transmit Buffer Overrun */
#define AT91_EMAC_TUND (1 << 4) /* Transmit Buffer Underrun */
#define AT91_EMAC_RTRY (1 << 5) /* Retry Limit */
#define AT91_EMAC_TBRE (1 << 6) /* Transmit Buffer Register Empty */
#define AT91_EMAC_TCOM (1 << 7) /* Transmit Complete */
#define AT91_EMAC_TIDLE (1 << 8) /* Transmit Idle */
#define AT91_EMAC_LINK (1 << 9) /* Link */
#define AT91_EMAC_ROVR (1 << 10) /* RX Overrun */
#define AT91_EMAC_ABT (1 << 11) /* Abort */
#define AT91_EMAC_IER 0x28 /* Interrupt Enable Register */
#define AT91_EMAC_IDR 0x2c /* Interrupt Disable Register */
#define AT91_EMAC_IMR 0x30 /* Interrupt Mask Register */
#define AT91_EMAC_MAN 0x34 /* PHY Maintenance Register */
#define AT91_EMAC_DATA (0xffff << 0) /* MDIO Data */
#define AT91_EMAC_REGA (0x1f << 18) /* MDIO Register */
#define AT91_EMAC_PHYA (0x1f << 23) /* MDIO PHY Address */
#define AT91_EMAC_RW (3 << 28) /* Read/Write operation */
#define AT91_EMAC_RW_W (1 << 28)
#define AT91_EMAC_RW_R (2 << 28)
#define AT91_EMAC_MAN_802_3 0x40020000 /* IEEE 802.3 value */
/*
* Statistics Registers.
*/
#define AT91_EMAC_FRA 0x40 /* Frames Transmitted OK */
#define AT91_EMAC_SCOL 0x44 /* Single Collision Frame */
#define AT91_EMAC_MCOL 0x48 /* Multiple Collision Frame */
#define AT91_EMAC_OK 0x4c /* Frames Received OK */
#define AT91_EMAC_SEQE 0x50 /* Frame Check Sequence Error */
#define AT91_EMAC_ALE 0x54 /* Alignmemt Error */
#define AT91_EMAC_DTE 0x58 /* Deffered Transmission Frame */
#define AT91_EMAC_LCOL 0x5c /* Late Collision */
#define AT91_EMAC_ECOL 0x60 /* Excessive Collision */
#define AT91_EMAC_TUE 0x64 /* Transmit Underrun Error */
#define AT91_EMAC_CSE 0x68 /* Carrier Sense Error */
#define AT91_EMAC_DRFC 0x6c /* Discard RX Frame */
#define AT91_EMAC_ROV 0x70 /* Receive Overrun */
#define AT91_EMAC_CDE 0x74 /* Code Error */
#define AT91_EMAC_ELR 0x78 /* Excessive Length Error */
#define AT91_EMAC_RJB 0x7c /* Receive Jabber */
#define AT91_EMAC_USF 0x80 /* Undersize Frame */
#define AT91_EMAC_SQEE 0x84 /* SQE Test Error */
/*
* Address Registers.
*/
#define AT91_EMAC_HSL 0x90 /* Hash Address Low [31:0] */
#define AT91_EMAC_HSH 0x94 /* Hash Address High [63:32] */
#define AT91_EMAC_SA1L 0x98 /* Specific Address 1 Low, bytes 0-3 */
#define AT91_EMAC_SA1H 0x9c /* Specific Address 1 High, bytes 4-5 */
#define AT91_EMAC_SA2L 0xa0 /* Specific Address 2 Low, bytes 0-3 */
#define AT91_EMAC_SA2H 0xa4 /* Specific Address 2 High, bytes 4-5 */
#define AT91_EMAC_SA3L 0xa8 /* Specific Address 3 Low, bytes 0-3 */
#define AT91_EMAC_SA3H 0xac /* Specific Address 3 High, bytes 4-5 */
#define AT91_EMAC_SA4L 0xb0 /* Specific Address 4 Low, bytes 0-3 */
#define AT91_EMAC_SA4H 0xb4 /* Specific Address 4 High, bytes 4-5 */
#endif

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/*
* arch/arm/mach-at91/include/mach/at91rm9200_mc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_MC_H
#define AT91RM9200_MC_H
/* Memory Controller */
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91_SDRAMC_MODE_NOP (1 << 0)
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91_SDRAMC_MODE_LMR (3 << 0)
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 4)
#define AT91_SDRAMC_DBW_16 (1 << 4)
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif

2
arch/arm/mach-s3c24xx/Kconfig
View File

@ -67,6 +67,8 @@ config MACH_A9M2410DEV
endchoice
source arch/arm/boards/mini2440/Kconfig
endmenu
menu "S3C24X0 Features "

59
arch/arm/mach-s3c24xx/include/mach/fb.h Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright (C) 2010 Juergen Beisert
* Copyright (C) 2011 Alexey Galakhov
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __MACH_FB_H_
# define __MACH_FB_H_
#include <fb.h>
/** Proprietary flags corresponding to S3C24x0 LCDCON5 register */
/** ! INVVDEN - DE active high */
#define FB_SYNC_DE_HIGH_ACT (1 << 23)
/** INVVCLK - invert CLK signal */
#define FB_SYNC_CLK_INVERT (1 << 24)
/** INVVD - invert data */
#define FB_SYNC_DATA_INVERT (1 << 25)
/** INVPWREN - use PWREN signal */
#define FB_SYNC_INVERT_PWREN (1 << 26)
/** INVLEND - use LEND signal */
#define FB_SYNC_INVERT_LEND (1 << 27)
/** PWREN - use PWREN signal */
#define FB_SYNC_USE_PWREN (1 << 28)
/** ENLEND - use LEND signal */
#define FB_SYNC_USE_LEND (1 << 29)
/** BSWP - swap bytes */
#define FB_SYNC_SWAP_BYTES (1 << 30)
/** HWSWP - swap half words */
#define FB_SYNC_SWAP_HW (1 << 31)
struct s3c_fb_platform_data {
struct fb_videomode *mode_list;
unsigned mode_cnt;
unsigned bits_per_pixel;
int passive_display; /**< enable support for STN or CSTN displays */
/** hook to enable backlight and stuff */
void (*enable)(int enable);
};
#endif /* __MACH_FB_H_ */

1
arch/sandbox/board/hostfile.c
View File

@ -66,6 +66,7 @@ static void hf_info(struct device_d *dev)
static struct file_operations hf_fops = {
.read = hf_read,
.write = hf_write,
.lseek = dev_lseek_default,
};
static int hf_probe(struct device_d *dev)

22
commands/Kconfig
View File

@ -222,6 +222,28 @@ config CMD_CRC_CMP
depends on CMD_CRC
prompt "compare 2 files crc"
config CMD_DIGEST
tristate
select DIGEST
config CMD_MD5SUM
tristate
select CMD_DIGEST
select MD5
prompt "md5sum"
config CMD_SHA1SUM
tristate
select CMD_DIGEST
select SHA1
prompt "sha1sum"
config CMD_SHA256SUM
tristate
select CMD_DIGEST
select SHA256
prompt "sha256sum"
config CMD_MTEST
tristate
prompt "mtest"

1
commands/Makefile
View File

@ -26,6 +26,7 @@ obj-$(CONFIG_CMD_MOUNT) += mount.o
obj-$(CONFIG_CMD_UMOUNT) += umount.o
obj-$(CONFIG_CMD_REGINFO) += reginfo.o
obj-$(CONFIG_CMD_CRC) += crc.o
obj-$(CONFIG_CMD_DIGEST) += digest.o
obj-$(CONFIG_CMD_CLEAR) += clear.o
obj-$(CONFIG_CMD_TEST) += test.o
obj-$(CONFIG_CMD_FLASH) += flash.o

183
commands/digest.c Normal file
View File

@ -0,0 +1,183 @@
/*
* digest.c - Calculate a md5/sha1/sha256 checksum of a memory area
*
* Copyright (c) 2011 Peter Korsgaard <jacmet@sunsite.dk>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <fs.h>
#include <fcntl.h>
#include <errno.h>
#include <xfuncs.h>
#include <malloc.h>
#include <digest.h>
static int file_digest(struct digest *d, char *filename,
ulong start, ulong size)
{
ulong len = 0;
int fd, now, i, ret = 0;
unsigned char *buf;
d->init(d);
fd = open(filename, O_RDONLY);
if (fd < 0) {
perror(filename);
return fd;
}
if (start > 0) {
ret = lseek(fd, start, SEEK_SET);
if (ret == -1) {
perror("lseek");
goto out;
}
}
buf = xmalloc(4096);
while (size) {
now = min((ulong)4096, size);
now = read(fd, buf, now);
if (now < 0) {
ret = now;
perror("read");
goto out_free;
}
if (!now)
break;
if (ctrlc()) {
ret = -EINTR;
goto out_free;
}
d->update(d, buf, now);
size -= now;
len += now;
}
d->final(d, buf);
for (i = 0; i < d->length; i++)
printf("%02x", buf[i]);
printf(" %s\t0x%08lx ... 0x%08lx\n", filename, start, start + len);
out_free:
free(buf);
out:
close(fd);
return ret;
}
static int do_digest(char *algorithm, int argc, char *argv[])
{
struct digest *d;
int ret = 0;
d = digest_get_by_name(algorithm);
BUG_ON(!d);
if (argc < 2)
return COMMAND_ERROR_USAGE;
argv++;
while (*argv) {
char *filename = "/dev/mem";
ulong start = 0, size = ~0;
/* arguments are either file, file+area or area */
if (parse_area_spec(*argv, &start, &size)) {
filename = *argv;
if (argv[1] && !parse_area_spec(argv[1], &start, &size))
argv++;
}
if (file_digest(d, filename, start, size) < 0)
ret = 1;
argv++;
}
return ret;
}
#ifdef CONFIG_CMD_MD5SUM
static int do_md5(struct command *cmdtp, int argc, char *argv[])
{
return do_digest("md5", argc, argv);
}
BAREBOX_CMD_HELP_START(md5sum)
BAREBOX_CMD_HELP_USAGE("md5sum [[FILE] [AREA]]...\n")
BAREBOX_CMD_HELP_SHORT("Calculate a md5 checksum of a memory area.\n")
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(md5sum)
.cmd = do_md5,
.usage = "md5 checksum calculation",
BAREBOX_CMD_HELP(cmd_md5sum_help)
BAREBOX_CMD_END
#endif /* CMD_CMD_MD5SUM */
#ifdef CONFIG_CMD_SHA1SUM
static int do_sha1(struct command *cmdtp, int argc, char *argv[])
{
return do_digest("sha1", argc, argv);
}
BAREBOX_CMD_HELP_START(sha1sum)
BAREBOX_CMD_HELP_USAGE("sha1sum [[FILE] [AREA]]...\n")
BAREBOX_CMD_HELP_SHORT("Calculate a sha1 checksum of a memory area.\n")
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(sha1sum)
.cmd = do_sha1,
.usage = "sha1 checksum calculation",
BAREBOX_CMD_HELP(cmd_sha1sum_help)
BAREBOX_CMD_END
#endif /* CMD_CMD_SHA1SUM */
#ifdef CONFIG_CMD_SHA256SUM
static int do_sha256(struct command *cmdtp, int argc, char *argv[])
{
return do_digest("sha256", argc, argv);
}
BAREBOX_CMD_HELP_START(sha256sum)
BAREBOX_CMD_HELP_USAGE("sha256sum [[FILE] [AREA]]...\n")
BAREBOX_CMD_HELP_SHORT("Calculate a sha256 checksum of a memory area.\n")
BAREBOX_CMD_HELP_END
BAREBOX_CMD_START(sha256sum)
.cmd = do_sha256,
.usage = "sha256 checksum calculation",
BAREBOX_CMD_HELP(cmd_sha256sum_help)
BAREBOX_CMD_END
#endif /* CMD_CMD_SHA256SUM */

13
drivers/video/Kconfig
View File

@ -27,4 +27,17 @@ config DRIVER_VIDEO_STM
Say 'Y' here to enable framebuffer and splash screen support for
i.MX23 and i.MX28 based systems.
config DRIVER_VIDEO_S3C
bool "S3C244x framebuffer driver"
depends on ARCH_S3C24xx
help
Add support for the S3C244x LCD controller.
if DRIVER_VIDEO_S3C
config DRIVER_VIDEO_S3C_VERBOSE
bool "S3C244x verbose framebuffer info"
endif
endif

1
drivers/video/Makefile
View File

@ -3,3 +3,4 @@ obj-$(CONFIG_VIDEO) += fb.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += stm.o
obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o
obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o
obj-$(CONFIG_DRIVER_VIDEO_S3C) += s3c.o

429
drivers/video/s3c.c Normal file
View File

@ -0,0 +1,429 @@
/*
* Copyright (C) 2010 Juergen Beisert
* Copyright (C) 2011 Alexey Galakhov
*
* This driver is based on a patch found in the web:
* (C) Copyright 2006 by OpenMoko, Inc.
* Author: Harald Welte <laforge at openmoko.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <init.h>
#include <fb.h>
#include <driver.h>
#include <malloc.h>
#include <errno.h>
#include <asm/io.h>
#include <mach/gpio.h>
#include <mach/s3c24xx-generic.h>
#include <mach/fb.h>
#define LCDCON1 0x00
# define PNRMODE(x) (((x) & 3) << 5)
# define BPPMODE(x) (((x) & 0xf) << 1)
# define SET_CLKVAL(x) (((x) & 0x3ff) << 8)
# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff)
# define ENVID (1 << 0)
#define LCDCON2 0x04
# define SET_VBPD(x) (((x) & 0xff) << 24)
# define SET_LINEVAL(x) (((x) & 0x3ff) << 14)
# define SET_VFPD(x) (((x) & 0xff) << 6)
# define SET_VSPW(x) ((x) & 0x3f)
#define LCDCON3 0x08
# define SET_HBPD(x) (((x) & 0x7f) << 19)
# define SET_HOZVAL(x) (((x) & 0x7ff) << 8)
# define SET_HFPD(x) ((x) & 0xff)
#define LCDCON4 0x0c
# define SET_HSPW(x) ((x) & 0xff)
#define LCDCON5 0x10
# define BPP24BL (1 << 12)
# define FRM565 (1 << 11)
# define INV_CLK (1 << 10)
# define INV_HS (1 << 9)
# define INV_VS (1 << 8)
# define INV_DTA (1 << 7)
# define INV_DE (1 << 6)
# define INV_PWREN (1 << 5)
# define INV_LEND (1 << 4)
# define ENA_PWREN (1 << 3)
# define ENA_LEND (1 << 2)
# define BSWP (1 << 1)
# define HWSWP (1 << 0)
#define LCDSADDR1 0x14
# define SET_LCDBANK(x) (((x) & 0x1ff) << 21)
# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff)
# define SET_LCDBASEU(x) ((x) & 0x1fffff)
# define GET_LCDBASEU(x) ((x) & 0x1fffff)
#define LCDSADDR2 0x18
# define SET_LCDBASEL(x) ((x) & 0x1fffff)
# define GET_LCDBASEL(x) ((x) & 0x1fffff)
#define LCDSADDR3 0x1c
# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11)
# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff)
# define SET_PAGE_WIDTH(x) ((x) & 0x3ff)
# define GET_PAGE_WIDTH(x) ((x) & 0x3ff)
#define RED_LUT 0x20
#define GREEN_LUT 0x24
#define BLUE_LUT 0x28
#define DITHMODE 0x4c
#define TPAL 0x50
#define LCDINTPND 0x54
#define LCDSRCPND 0x58
#define LCDINTMSK 0x5c
# define FIWSEL (1 << 2)
# define INT_FrSyn (1 << 1)
# define INT_FiCnt (1 << 0)
#define TCONSEL 0x60
#define RED 0
#define GREEN 1
#define BLUE 2
#define TRANSP 3
struct s3cfb_info {
void __iomem *base;
unsigned memory_size;
struct fb_info info;
struct device_d *hw_dev;
int passive_display;
void (*enable)(int enable);
};
/* the RGB565 true colour mode */
static const struct fb_bitfield def_rgb565[] = {
[RED] = {
.offset = 11,
.length = 5,
},
[GREEN] = {
.offset = 5,
.length = 6,
},
[BLUE] = {
.offset = 0,
.length = 5,
},
[TRANSP] = { /* no support for transparency */
.length = 0,
}
};
/* the RGB888 true colour mode */
static const struct fb_bitfield def_rgb888[] = {
[RED] = {
.offset = 16,
.length = 8,
},
[GREEN] = {
.offset = 8,
.length = 8,
},
[BLUE] = {
.offset = 0,
.length = 8,
},
[TRANSP] = { /* no support for transparency */
.length = 0,
}
};
/**
* @param fb_info Framebuffer information
*/
static void s3cfb_enable_controller(struct fb_info *fb_info)
{
struct s3cfb_info *fbi = fb_info->priv;
uint32_t con1;
con1 = readl(fbi->base + LCDCON1);
con1 |= ENVID;
writel(con1, fbi->base + LCDCON1);
if (fbi->enable)
fbi->enable(1);
}
/**
* @param fb_info Framebuffer information
*/
static void s3cfb_disable_controller(struct fb_info *fb_info)
{
struct s3cfb_info *fbi = fb_info->priv;
uint32_t con1;
if (fbi->enable)
fbi->enable(0);
con1 = readl(fbi->base + LCDCON1);
con1 &= ~ENVID;
writel(con1, fbi->base + LCDCON1);
}
/**
* Prepare the video hardware for a specified video mode
* @param fb_info Framebuffer information
* @param mode The video mode description to initialize
* @return 0 on success
*/
static int s3cfb_activate_var(struct fb_info *fb_info)
{
struct s3cfb_info *fbi = fb_info->priv;
struct fb_videomode *mode = fb_info->mode;
unsigned size, hclk, div;
uint32_t con1, con2, con3, con4, con5 = 0;
if (fbi->passive_display != 0) {
dev_err(fbi->hw_dev, "Passive displays are currently not supported\n");
return -EINVAL;
}
/*
* we need at least this amount of memory for the framebuffer
*/
size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3);
if (fbi->memory_size != size || fb_info->screen_base == NULL) {
if (fb_info->screen_base)
free(fb_info->screen_base);
fbi->memory_size = 0;
fb_info->screen_base = malloc(size);
if (! fb_info->screen_base)
return -ENOMEM;
memset(fb_info->screen_base, 0, size);
fbi->memory_size = size;
}
/* ensure video output is _off_ */
writel(0x00000000, fbi->base + LCDCON1);
hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */
div = hclk / PICOS2KHZ(mode->pixclock);
if (div < 3)
div = 3;
/* pixel clock is: (hclk) / ((div + 1) * 2) */
div += 1;
div >>= 1;
div -= 1;
con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */
switch (fb_info->bits_per_pixel) {
case 16:
con1 |= BPPMODE(12);
con5 |= FRM565;
con5 |= HWSWP;
fb_info->red = def_rgb565[RED];
fb_info->green = def_rgb565[GREEN];
fb_info->blue = def_rgb565[BLUE];
fb_info->transp = def_rgb565[TRANSP];
break;
case 24:
con1 |= BPPMODE(13);
/* con5 |= BPP24BL; */ /* FIXME maybe needed, check alignment */
fb_info->red = def_rgb888[RED];
fb_info->green = def_rgb888[GREEN];
fb_info->blue = def_rgb888[BLUE];
fb_info->transp = def_rgb888[TRANSP];
break;
default:
dev_err(fbi->hw_dev, "Invalid bits per pixel value: %u\n", fb_info->bits_per_pixel);
return -EINVAL;
}
/* 'normal' in register description means positive logic */
if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
con5 |= INV_HS;
if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))
con5 |= INV_VS;
if (!(mode->sync & FB_SYNC_DE_HIGH_ACT))
con5 |= INV_DE;
if (mode->sync & FB_SYNC_CLK_INVERT)
con5 |= INV_CLK; /* display should latch at the rising edge */
if (mode->sync & FB_SYNC_DATA_INVERT)
con5 |= INV_DTA;
if (mode->sync & FB_SYNC_INVERT_PWREN)
con5 |= INV_PWREN;
if (mode->sync & FB_SYNC_INVERT_LEND)
con5 |= INV_LEND;
if (mode->sync & FB_SYNC_USE_PWREN)
con5 |= ENA_PWREN; /* FIXME should this be done conditionally/later? */
if (mode->sync & FB_SYNC_USE_LEND)
con5 |= ENA_LEND;
if (mode->sync & FB_SYNC_SWAP_BYTES)
con5 ^= BSWP;
if (mode->sync & FB_SYNC_SWAP_HW)
con5 ^= HWSWP;
/* vertical timing */
con2 = SET_VBPD(mode->upper_margin - 1) |
SET_LINEVAL(mode->yres - 1) |
SET_VFPD(mode->lower_margin - 1) |
SET_VSPW(mode->vsync_len - 1);
/* horizontal timing */
con3 = SET_HBPD(mode->left_margin - 1) |
SET_HOZVAL(mode->xres - 1) |
SET_HFPD(mode->right_margin - 1);
con4 = SET_HSPW(mode->hsync_len - 1);
/* basic timing setup */
writel(con1, fbi->base + LCDCON1);
dev_dbg(fbi->hw_dev, "writing %08X into %p (con1)\n", con1, fbi->base + LCDCON1);
writel(con2, fbi->base + LCDCON2);
dev_dbg(fbi->hw_dev, "writing %08X into %p (con2)\n", con2, fbi->base + LCDCON2);
writel(con3, fbi->base + LCDCON3);
dev_dbg(fbi->hw_dev, "writing %08X into %p (con3)\n", con3, fbi->base + LCDCON3);
writel(con4, fbi->base + LCDCON4);
dev_dbg(fbi->hw_dev, "writing %08X into %p (con4)\n", con4, fbi->base + LCDCON4);
writel(con5, fbi->base + LCDCON5);
dev_dbg(fbi->hw_dev, "writing %08X into %p (con5)\n", con5, fbi->base + LCDCON5);
dev_dbg(fbi->hw_dev, "setting up the fb baseadress to %p\n", fb_info->screen_base);
/* framebuffer memory setup */
writel((unsigned)fb_info->screen_base >> 1, fbi->base + LCDSADDR1);
size = mode->xres * (fb_info->bits_per_pixel >> 3) * (mode->yres);
writel(SET_LCDBASEL(((unsigned)fb_info->screen_base + size) >> 1), fbi->base + LCDSADDR2);
writel(SET_OFFSIZE(0) |
SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4),
fbi->base + LCDSADDR3);
writel(FIWSEL | INT_FrSyn | INT_FiCnt, fbi->base + LCDINTMSK);
return 0;
}
/**
* Print some information about the current hardware state
* @param hw_dev S3C video device
*/
#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
static void s3cfb_info(struct device_d *hw_dev)
{
uint32_t con1, addr1, addr2, addr3;
con1 = readl(hw_dev->map_base + LCDCON1);
addr1 = readl(hw_dev->map_base + LCDSADDR1);
addr2 = readl(hw_dev->map_base + LCDSADDR2);
addr3 = readl(hw_dev->map_base + LCDSADDR3);
printf(" Video hardware info:\n");
printf(" Video clock is running at %u Hz\n", s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2));
printf(" Video memory bank starts at 0x%08X\n", GET_LCDBANK(addr1) << 22);
printf(" Video memory bank offset: 0x%08X\n", GET_LCDBASEU(addr1));
printf(" Video memory end: 0x%08X\n", GET_LCDBASEU(addr2));
printf(" Virtual screen offset size: %u half words\n", GET_OFFSIZE(addr3));
printf(" Virtual screen page width: %u half words\n", GET_PAGE_WIDTH(addr3));
}
#endif
/*
* There is only one video hardware instance available.
* It makes no sense to dynamically allocate this data
*/
static struct fb_ops s3cfb_ops = {
.fb_activate_var = s3cfb_activate_var,
.fb_enable = s3cfb_enable_controller,
.fb_disable = s3cfb_disable_controller,
};
static struct s3cfb_info fbi = {
.info = {
.fbops = &s3cfb_ops,
},
};
static int s3cfb_probe(struct device_d *hw_dev)
{
struct s3c_fb_platform_data *pdata = hw_dev->platform_data;
int ret;
if (! pdata)
return -ENODEV;
writel(0, hw_dev->map_base + LCDCON1);
writel(0, hw_dev->map_base + LCDCON5); /* FIXME not 0 for some displays */
/* just init */
fbi.info.priv = &fbi;
/* add runtime hardware info */
fbi.hw_dev = hw_dev;
fbi.base = (void*)hw_dev->map_base;
/* add runtime video info */
fbi.info.mode_list = pdata->mode_list;
fbi.info.num_modes = pdata->mode_cnt;
fbi.info.mode = &fbi.info.mode_list[1];
fbi.info.xres = fbi.info.mode->xres;
fbi.info.yres = fbi.info.mode->yres;
if (pdata->bits_per_pixel)
fbi.info.bits_per_pixel = pdata->bits_per_pixel;
else
fbi.info.bits_per_pixel = 16;
fbi.passive_display = pdata->passive_display;
fbi.enable = pdata->enable;
ret = register_framebuffer(&fbi.info);
if (ret != 0) {
dev_err(hw_dev, "Failed to register framebuffer\n");
return -EINVAL;
}
return 0;
}
static struct driver_d s3cfb_driver = {
.name = "s3c_fb",
.probe = s3cfb_probe,
#ifdef CONFIG_DRIVER_VIDEO_S3C_VERBOSE
.info = s3cfb_info,
#endif
};
static int s3cfb_init(void)
{
return register_driver(&s3cfb_driver);
}
device_initcall(s3cfb_init);
/**
* The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) LC displays
*
* The driver itself currently supports only active TFT LC displays in the follwing manner:
*
* * True colours
* - 16 bpp
* - 24 bpp (untested)
*/