spi: mvebu: add LSB support
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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34e083ea64
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7251966266
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@ -31,8 +31,13 @@
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#define IF_READ_READY BIT(1)
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#define IF_CS_ENABLE BIT(0)
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#define SPI_IF_CONFIG 0x04
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#define IF_RXLSBF BIT(14)
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#define IF_TXLSBF BIT(13)
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#define IF_CLK_DIV(x) ((x) << 11)
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#define IF_CLK_DIV_MASK (0x7 << 11)
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#define IF_FAST_READ BIT(10)
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#define IF_ADDRESS_LEN_4BYTE (3 << 8)
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#define IF_ADDRESS_LEN_3BYTE (2 << 8)
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@ -192,6 +197,8 @@ static int dove_spi_set_baudrate(struct mvebu_spi *p, u32 speed)
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static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
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{
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u32 val;
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/*
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* From public datasheets of Orion SoCs, it is unclear
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* if the SPI controller supports setting CPOL/CPHA.
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@ -202,12 +209,19 @@ static int mvebu_spi_set_mode(struct mvebu_spi *p, u8 mode)
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* other mode than SPI_MODE0.
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*/
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if ((mode & (SPI_CPOL|SPI_CPHA)) == SPI_MODE_0)
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return 0;
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if ((mode & (SPI_CPOL|SPI_CPHA)) != SPI_MODE_0) {
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pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
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return -EINVAL;
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}
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pr_err("%s: unsupported SPI mode %02x\n", __func__, mode);
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val = readl(p->base + SPI_IF_CONFIG);
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if (mode & SPI_LSB_FIRST)
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val |= IF_RXLSBF | IF_TXLSBF;
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else
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val &= ~(IF_RXLSBF | IF_TXLSBF);
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writel(val, p->base + SPI_IF_CONFIG);
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return -EINVAL;
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return 0;
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}
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static int mvebu_spi_setup(struct spi_device *spi)
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@ -293,6 +307,12 @@ static int mvebu_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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int ret;
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struct mvebu_spi *priv = priv_from_spi_device(spi);
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ret = mvebu_spi_set_mode(priv, spi->mode);
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if (ret) {
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dev_err(&spi->dev, "Failed to set mode (0x%x)\n", (unsigned)spi->mode);
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return ret;
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}
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ret = mvebu_spi_set_cs(priv, spi->chip_select, spi->mode, true);
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if (ret)
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return ret;
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