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arm: mvebu: introduce common lowlevel and early init 

At early stage after boot, all MVEBU SoCs are similar enough to have
a common lowlevel and barebox entry. We  also remap the internal register
base address to 0xf100000 as it gives some 512M more of contiguous address
space. As we cannot determine real memory size that early, we start with
a default memory size of 64M and probe correct size later in SoC init.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sebastian Hesselbarth 2013-05-19 20:23:46 +02:00 committed by Sascha Hauer
parent df8d29462b
commit 7286acab67
27 changed files with 316 additions and 319 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boards/globalscale-guruplug/Makefile
View File

@ -1,2 +1 @@
obj-y = globalscale-guruplug.o
lwl-y += lowlevel.o
obj-y += board.o

12
arch/arm/boards/solidrun-cubox/solidrun-cubox.c → arch/arm/boards/globalscale-guruplug/board.c
View File

@ -1,6 +1,6 @@
/*
* Copyright
* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -14,12 +14,4 @@
*
*/
#include <common.h>
#include <init.h>
#include <mach/dove.h>
static int solidrun_cubox_console_init(void)
{
return dove_add_uart(0);
}
console_initcall(solidrun_cubox_console_init);
/* empty */

26
arch/arm/boards/globalscale-guruplug/globalscale-guruplug.c
View File

@ -1,26 +0,0 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <init.h>
#include <sizes.h>
#include <mach/kirkwood.h>
static int globalscale_guruplug_console_init(void)
{
return kirkwood_add_uart0();
}
console_initcall(globalscale_guruplug_console_init);

26
arch/arm/boards/globalscale-guruplug/lowlevel.c
View File

@ -1,26 +0,0 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <sizes.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/kirkwood.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
kirkwood_barebox_entry();
}

3
arch/arm/boards/globalscale-mirabox/Makefile
View File

@ -1,2 +1 @@
obj-y = globalscale-mirabox.o
lwl-y += lowlevel.o
obj-y += board.c

13
arch/arm/boards/solidrun-cubox/lowlevel.c → arch/arm/boards/globalscale-mirabox/board.c
View File

@ -1,6 +1,6 @@
/*
* Copyright
* (C) 2013 Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -14,13 +14,4 @@
*
*/
#include <common.h>
#include <mach/dove.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
dove_barebox_entry();
}
/* empty */

26
arch/arm/boards/globalscale-mirabox/globalscale-mirabox.c
View File

@ -1,26 +0,0 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <init.h>
#include <sizes.h>
#include <mach/mvebu.h>
static int globalscale_mirabox_console_init(void)
{
return mvebu_add_uart0();
}
console_initcall(globalscale_mirabox_console_init);

3
arch/arm/boards/marvell-armada-xp-gp/Makefile
View File

@ -1,2 +1 @@
obj-y = marvell-armada-xp-gp.o
lwl-y += lowlevel.o
obj-y += board.o

17
arch/arm/boards/marvell-armada-xp-gp/board.c Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/* empty */

3
arch/arm/boards/plathome-openblocks-ax3/Makefile
View File

@ -1,2 +1 @@
obj-y = plathome-openblocks-ax3.o
lwl-y += lowlevel.o
obj-y += board.o

17
arch/arm/boards/plathome-openblocks-ax3/board.c Normal file
View File

@ -0,0 +1,17 @@
/*
* Copyright
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/* empty */

25
arch/arm/boards/plathome-openblocks-ax3/lowlevel.c
View File

@ -1,25 +0,0 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <mach/mvebu.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
mvebu_barebox_entry();
}

3
arch/arm/boards/solidrun-cubox/Makefile
View File

@ -1,2 +1 @@
obj-y = solidrun-cubox.o
lwl-y += lowlevel.o
obj-y += board.c

14
arch/arm/boards/marvell-armada-xp-gp/lowlevel.c → arch/arm/boards/solidrun-cubox/board.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2013
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -13,13 +14,4 @@
*
*/
#include <common.h>
#include <mach/mvebu.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
void __naked barebox_arm_reset_vector(void)
{
arm_cpu_lowlevel_init();
mvebu_barebox_entry();
}
/* empty */

14
arch/arm/mach-mvebu/Kconfig
View File

@ -107,4 +107,18 @@ endchoice
endif # ARCH_KIRKWOOD
#
# Common options
#
config MVEBU_CONSOLE_UART
int "UART number for console"
default 0
range 0 1 if ARCH_ARMADA_370
range 0 1 if ARCH_ARMADA_XP
range 0 3 if ARCH_DOVE
range 0 1 if ARCH_KIRKWOOD
help
Select the UART number the barebox console will sit on.
endif # ARCH_MVEBU

2
arch/arm/mach-mvebu/Makefile
View File

@ -1,3 +1,5 @@
lwl-y += lowlevel.o
obj-y += common.o
obj-$(CONFIG_ARCH_ARMADA_370) += armada-370-xp.o
obj-$(CONFIG_ARCH_ARMADA_XP) += armada-370-xp.o
obj-$(CONFIG_ARCH_DOVE) += dove.o

101
arch/arm/mach-mvebu/armada-370-xp.c
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -16,49 +17,31 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <ns16550.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <ns16550.h>
#include <asm/memory.h>
#include <asm/barebox-arm.h>
#include <mach/armada-370-xp-regs.h>
#define MVEBU_INT_REGS_BASE (0xd0000000)
#define MVEBU_UART0_BASE (MVEBU_INT_REGS_BASE + 0x12000)
#define MVEBU_SYSCTL_BASE (MVEBU_INT_REGS_BASE + 0x18200)
#define MVEBU_SDRAM_WIN_BASE (MVEBU_INT_REGS_BASE + 0x20180)
#define MVEBU_TIMER_BASE (MVEBU_INT_REGS_BASE + 0x20300)
#define MVEBU_SAR_BASE (MVEBU_INT_REGS_BASE + 0x18230)
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
#define DDR_BASE_CS_HIGH_MASK 0xf
#define DDR_BASE_CS_LOW_MASK 0xff000000
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
#define DDR_SIZE_ENABLED (1 << 0)
#define DDR_SIZE_CS_MASK 0x1c
#define DDR_SIZE_CS_SHIFT 2
#define DDR_SIZE_MASK 0xff000000
#define SAR_LOW_REG_OFF 0
#define SAR_TCLK_FREQ_BIT 20
#define SAR_HIGH_REG_OFF 0x4
#define CONSOLE_UART_BASE \
ARMADA_370_XP_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
static struct clk *tclk;
static inline void mvebu_memory_find(unsigned long *phys_base,
unsigned long *phys_size)
static inline void armada_370_xp_memory_find(unsigned long *phys_base,
unsigned long *phys_size)
{
void __iomem *sdram_win = IOMEM(MVEBU_SDRAM_WIN_BASE);
int cs;
*phys_base = ~0;
*phys_size = 0;
for (cs = 0; cs < 4; cs++) {
uint32_t base = readl(sdram_win + DDR_BASE_CS_OFF(cs));
uint32_t ctrl = readl(sdram_win + DDR_SIZE_CS_OFF(cs));
u32 base = readl(ARMADA_370_XP_SDRAM_BASE + DDR_BASE_CSn(cs));
u32 ctrl = readl(ARMADA_370_XP_SDRAM_BASE + DDR_SIZE_CSn(cs));
/* Skip non-enabled CS */
if (! (ctrl & DDR_SIZE_ENABLED))
if ((ctrl & DDR_SIZE_ENABLED) != DDR_SIZE_ENABLED)
continue;
base &= DDR_BASE_CS_LOW_MASK;
@ -68,74 +51,70 @@ static inline void mvebu_memory_find(unsigned long *phys_base,
}
}
void __naked __noreturn mvebu_barebox_entry(void)
{
unsigned long phys_base, phys_size;
mvebu_memory_find(&phys_base, &phys_size);
barebox_arm_entry(phys_base, phys_size, 0);
}
static struct NS16550_plat uart0_plat = {
static struct NS16550_plat uart_plat = {
.shift = 2,
};
int mvebu_add_uart0(void)
static int armada_370_xp_add_uart(void)
{
uart0_plat.clock = clk_get_rate(tclk);
add_ns16550_device(DEVICE_ID_DYNAMIC, MVEBU_UART0_BASE, 32,
IORESOURCE_MEM_32BIT, &uart0_plat);
uart_plat.clock = clk_get_rate(tclk);
if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
(unsigned int)CONSOLE_UART_BASE, 32,
IORESOURCE_MEM_32BIT, &uart_plat))
return -ENODEV;
return 0;
}
#if defined(CONFIG_ARCH_ARMADA_370)
static int mvebu_init_clocks(void)
static int armada_370_init_clocks(void)
{
uint32_t val;
u32 val = readl(ARMADA_370_XP_SAR_BASE + SAR_LOW);
unsigned int rate;
void __iomem *sar = IOMEM(MVEBU_SAR_BASE) + SAR_LOW_REG_OFF;
val = readl(sar);
/* On Armada 370, the TCLK frequency can be either 166 Mhz or
* 200 Mhz */
if (val & (1 << SAR_TCLK_FREQ_BIT))
rate = 200 * 1000 * 1000;
/*
* On Armada 370, the TCLK frequency can be either
* 166 Mhz or 200 Mhz
*/
if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ)
rate = 200000000;
else
rate = 166 * 1000 * 1000;
rate = 166000000;
tclk = clk_fixed("tclk", rate);
return clk_register_clkdev(tclk, NULL, "mvebu-timer");
}
#define armada_370_xp_init_clocks() armada_370_init_clocks()
#endif
#if defined(CONFIG_ARCH_ARMADA_XP)
static int mvebu_init_clocks(void)
static int armada_xp_init_clocks(void)
{
/* On Armada XP, the TCLK frequency is always 250 Mhz */
tclk = clk_fixed("tclk", 250 * 1000 * 1000);
tclk = clk_fixed("tclk", 250000000);
return clk_register_clkdev(tclk, NULL, "mvebu-timer");
}
#define armada_370_xp_init_clocks() armada_xp_init_clocks()
#endif
static int mvebu_init_soc(void)
static int armada_370_xp_init_soc(void)
{
unsigned long phys_base, phys_size;
mvebu_init_clocks();
armada_370_xp_init_clocks();
add_generic_device("mvebu-timer", DEVICE_ID_SINGLE, NULL,
MVEBU_TIMER_BASE, 0x30, IORESOURCE_MEM,
NULL);
mvebu_memory_find(&phys_base, &phys_size);
(unsigned int)ARMADA_370_XP_TIMER_BASE, 0x30,
IORESOURCE_MEM, NULL);
armada_370_xp_memory_find(&phys_base, &phys_size);
arm_add_mem_device("ram0", phys_base, phys_size);
armada_370_xp_add_uart();
return 0;
}
postcore_initcall(mvebu_init_soc);
postcore_initcall(armada_370_xp_init_soc);
void __noreturn reset_cpu(unsigned long addr)
{
writel(0x1, MVEBU_SYSCTL_BASE + 0x60);
writel(0x1, MVEBU_SYSCTL_BASE + 0x64);
writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x60);
writel(0x1, ARMADA_370_XP_SYSCTL_BASE + 0x64);
while (1)
;
}

57
arch/arm/mach-mvebu/common.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright (C) 2013
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <common.h>
#include <io.h>
#include <sizes.h>
#include <asm/barebox-arm.h>
#include <mach/common.h>
/*
* All MVEBU SoCs start with internal registers at 0xd0000000.
* To get more contiguous address space and as Linux expects them
* there, we remap them early to 0xf1000000.
*
* There is no way to determine internal registers base address
* safely later on, as the remap register itself is within the
* internal registers.
*/
#define MVEBU_BOOTUP_INT_REG_BASE 0xd0000000
#define MVEBU_BRIDGE_REG_BASE 0x20000
#define DEVICE_INTERNAL_BASE_ADDR (MVEBU_BRIDGE_REG_BASE + 0x80)
static void mvebu_remap_registers(void)
{
writel(MVEBU_REMAP_INT_REG_BASE,
IOMEM(MVEBU_BOOTUP_INT_REG_BASE) + DEVICE_INTERNAL_BASE_ADDR);
}
/*
* Determining the actual memory size is highly SoC dependent,
* but for all SoCs RAM starts at 0x00000000. Therefore, we start
* with a minimal memory setup of 64M and probe correct memory size
* later.
*/
#define MVEBU_BOOTUP_MEMORY_BASE 0x00000000
#define MVEBU_BOOTUP_MEMORY_SIZE SZ_64M
void __naked __noreturn mvebu_barebox_entry(void)
{
mvebu_remap_registers();
barebox_arm_entry(MVEBU_BOOTUP_MEMORY_BASE,
MVEBU_BOOTUP_MEMORY_SIZE, 0);
}

56
arch/arm/mach-mvebu/dove.c
View File

@ -17,38 +17,35 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <ns16550.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <ns16550.h>
#include <mach/dove-regs.h>
#include <asm/memory.h>
#include <asm/barebox-arm.h>
#include <mach/dove-regs.h>
#define CONSOLE_UART_BASE DOVE_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
static struct clk *tclk;
static inline void dove_remap_reg_base(uint32_t intbase,
uint32_t mcbase)
static inline void dove_remap_mc_regs(void)
{
void __iomem *mcboot = IOMEM(DOVE_BOOTUP_MC_REGS);
uint32_t val;
/* remap ahb slave base */
val = readl(DOVE_CPU_CTRL) & 0xffff0000;
val |= (mcbase & 0xffff0000) >> 16;
val |= (DOVE_REMAP_MC_REGS & 0xffff0000) >> 16;
writel(val, DOVE_CPU_CTRL);
/* remap axi bridge address */
val = readl(DOVE_AXI_CTRL) & 0x007fffff;
val |= mcbase & 0xff800000;
val |= DOVE_REMAP_MC_REGS & 0xff800000;
writel(val, DOVE_AXI_CTRL);
/* remap memory controller base address */
val = readl(DOVE_SDRAM_BASE + SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
val |= mcbase & 0xffff0000;
writel(val, DOVE_SDRAM_BASE + SDRAM_REGS_BASE_DECODE);
/* remap internal register */
val = intbase & 0xfff00000;
writel(val, DOVE_BRIDGE_BASE + INT_REGS_BASE_MAP);
val = readl(mcboot + SDRAM_REGS_BASE_DECODE) & 0x0000ffff;
val |= DOVE_REMAP_MC_REGS & 0xffff0000;
writel(val, mcboot + SDRAM_REGS_BASE_DECODE);
}
static inline void dove_memory_find(unsigned long *phys_base,
@ -77,32 +74,16 @@ static inline void dove_memory_find(unsigned long *phys_base,
}
}
void __naked __noreturn dove_barebox_entry(void)
{
unsigned long phys_base, phys_size;
dove_memory_find(&phys_base, &phys_size);
barebox_arm_entry(phys_base, phys_size, 0);
}
static struct NS16550_plat uart_plat[] = {
[0] = { .shift = 2, },
[1] = { .shift = 2, },
[2] = { .shift = 2, },
[3] = { .shift = 2, },
static struct NS16550_plat uart_plat = {
.shift = 2,
};
int dove_add_uart(int num)
static int dove_add_uart(void)
{
struct NS16550_plat *plat;
if (num < 0 || num > 4)
return -EINVAL;
plat = &uart_plat[num];
plat->clock = clk_get_rate(tclk);
uart_plat.clock = clk_get_rate(tclk);
if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
(unsigned int)DOVE_UARTn_BASE(num),
32, IORESOURCE_MEM_32BIT, plat))
(unsigned int)CONSOLE_UART_BASE, 32,
IORESOURCE_MEM_32BIT, &uart_plat))
return -ENODEV;
return 0;
}
@ -140,12 +121,15 @@ static int dove_init_soc(void)
{
unsigned long phys_base, phys_size;
dove_remap_mc_regs();
dove_init_clocks();
add_generic_device("orion-timer", DEVICE_ID_SINGLE, NULL,
(unsigned int)DOVE_TIMER_BASE, 0x30,
IORESOURCE_MEM, NULL);
dove_memory_find(&phys_base, &phys_size);
arm_add_mem_device("ram0", phys_base, phys_size);
dove_add_uart();
return 0;
}
postcore_initcall(dove_init_soc);

47
arch/arm/mach-mvebu/include/mach/armada-370-xp-regs.h Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright
* (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_MVEBU_ARMADA_370_XP_REGS_H
#define __MACH_MVEBU_ARMADA_370_XP_REGS_H
#include <mach/common.h>
#define ARMADA_370_XP_INT_REGS_BASE IOMEM(MVEBU_REMAP_INT_REG_BASE)
#define ARMADA_370_XP_UART_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x12000)
#define ARMADA_370_XP_UARTn_BASE(n) \
(ARMADA_370_XP_UART_BASE + ((n) * 0x100))
#define ARMADA_370_XP_SYSCTL_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x18200)
#define ARMADA_370_XP_SAR_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x18230)
#define SAR_LOW 0x00
#define SAR_TCLK_FREQ BIT(20)
#define SAR_HIGH 0x04
#define ARMADA_370_XP_SDRAM_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20000)
#define DDR_BASE_CS 0x180
#define DDR_BASE_CSn(n) (DDR_BASE_CS + ((n) * 0x8))
#define DDR_BASE_CS_HIGH_MASK 0x0000000f
#define DDR_BASE_CS_LOW_MASK 0xff000000
#define DDR_SIZE_CS 0x184
#define DDR_SIZE_CSn(n) (DDR_SIZE_CS + ((n) * 0x8))
#define DDR_SIZE_ENABLED BIT(0)
#define DDR_SIZE_CS_MASK 0x0000001c
#define DDR_SIZE_CS_SHIFT 2
#define DDR_SIZE_MASK 0xff000000
#define ARMADA_370_XP_TIMER_BASE (ARMADA_370_XP_INT_REGS_BASE + 0x20300)
#endif /* __MACH_MVEBU_DOVE_REGS_H */

16
arch/arm/boards/marvell-armada-xp-gp/marvell-armada-xp-gp.c → arch/arm/mach-mvebu/include/mach/common.h
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2013
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -13,13 +15,9 @@
*
*/
#include <common.h>
#include <init.h>
#include <mach/mvebu.h>
#ifndef __MACH_COMMON_H__
#define __MACH_COMMON_H__
static int marvell_armada_xp_gp_console_init(void)
{
return mvebu_add_uart0();
}
#define MVEBU_REMAP_INT_REG_BASE 0xf1000000
console_initcall(marvell_armada_xp_gp_console_init);
#endif

23
arch/arm/mach-mvebu/include/mach/debug_ll.h
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2013
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -18,23 +19,25 @@
#include <io.h>
#define UART_BASE 0xd0012000
#define UART_THR 0x0
#define UART_LSR 0x14
#define UART_LSR_THRE (1 << 5)
#define UART_BASE 0xf1012000
#define UARTn_BASE(n) (UART_BASE + ((n) * 0x100))
#define UART_THR 0x00
#define UART_LSR 0x14
#define LSR_THRE BIT(5)
#define EARLY_UART UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
static inline void PUTC_LL(char c)
{
/* Wait until there is space in the FIFO */
while (!(readl(UART_BASE + UART_LSR) & UART_LSR_THRE))
while (!(readl(EARLY_UART + UART_LSR) & LSR_THRE))
;
/* Send the character */
writel(c, UART_BASE + UART_THR)
;
writel(c, EARLY_UART + UART_THR);
/* Wait to make sure it hits the line, in case we die too soon. */
while (!(readl(UART_BASE + UART_LSR) & UART_LSR_THRE))
/* Wait to make sure it hits the line */
while (!(readl(EARLY_UART + UART_LSR) & LSR_THRE))
;
}
#endif

19
arch/arm/mach-mvebu/include/mach/dove-regs.h
View File

@ -17,15 +17,18 @@
#ifndef __MACH_MVEBU_DOVE_REGS_H
#define __MACH_MVEBU_DOVE_REGS_H
/* At Boot-up register base is at 0xd000000 */
#define DOVE_INT_REGS_BOOTUP 0xd0000000
#define DOVE_MC_REGS_BOOTUP 0xd0800000
/* Linux wants it remapped to 0xf1000000 */
#define DOVE_INT_REGS_REMAP 0xf1000000
#define DOVE_MC_REGS_REMAP 0xf1800000
#include <mach/common.h>
#define DOVE_INT_REGS_BASE IOMEM(DOVE_INT_REGS_BOOTUP)
#define DOVE_MC_REGS_BASE IOMEM(DOVE_MC_REGS_BOOTUP)
/*
* Even after MVEBU SoC internal register base remap. Dove MC
* registers are still at 0xd0800000. We remap it right after
* internal registers to 0xf1800000.
*/
#define DOVE_BOOTUP_MC_REGS 0xd0800000
#define DOVE_REMAP_MC_REGS 0xf1800000
#define DOVE_INT_REGS_BASE IOMEM(MVEBU_REMAP_INT_REG_BASE)
#define DOVE_MC_REGS_BASE IOMEM(DOVE_REMAP_MC_REGS)
#define DOVE_UART_BASE (DOVE_INT_REGS_BASE + 0x12000)
#define DOVE_UARTn_BASE(n) (DOVE_UART_BASE + ((n) * 0x100))

43
arch/arm/mach-mvebu/include/mach/kirkwood-regs.h
View File

@ -17,21 +17,34 @@
#ifndef __MACH_MVEBU_KIRKWOOD_REGS_H
#define __MACH_MVEBU_KIRKWOOD_REGS_H
#define KIRKWOOD_INT_REGS_BASE IOMEM(0xd0000000)
#include <mach/common.h>
#define KIRKWOOD_SDRAM_WIN_BASE (KIRKWOOD_INT_REGS_BASE + 0x1500)
#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
#define DDR_BASE_CS_HIGH_MASK 0xf
#define DDR_BASE_CS_LOW_MASK 0xff000000
#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
#define DDR_SIZE_ENABLED (1 << 0)
#define DDR_SIZE_CS_MASK 0x1c
#define DDR_SIZE_CS_SHIFT 2
#define DDR_SIZE_MASK 0xff000000
#define KIRKWOOD_SAR_BASE (KIRKWOOD_INT_REGS_BASE + 0x10030)
#define KIRKWOOD_TCLK_BIT 21
#define KIRKWOOD_UART_BASE (KIRKWOOD_INT_REGS_BASE + 0x12000)
#define KIRKWOOD_CPUCTRL_BASE (KIRKWOOD_INT_REGS_BASE + 0x20100)
#define KIRKWOOD_TIMER_BASE (KIRKWOOD_INT_REGS_BASE + 0x20300)
#define KIRKWOOD_INT_REGS_BASE IOMEM(MVEBU_REMAP_INT_REG_BASE)
#define KIRKWOOD_SDRAM_BASE (KIRKWOOD_INT_REGS_BASE + 0x00000)
#define DDR_BASE_CS 0x1500
#define DDR_BASE_CSn(n) (DDR_BASE_CS + ((n) * 0x8))
#define DDR_BASE_CS_HIGH_MASK 0x0000000f
#define DDR_BASE_CS_LOW_MASK 0xff000000
#define DDR_SIZE_CS 0x1504
#define DDR_SIZE_CSn(n) (DDR_SIZE_CS + ((n) * 0x8))
#define DDR_SIZE_ENABLED BIT(0)
#define DDR_SIZE_CS_MASK 0x1c
#define DDR_SIZE_CS_SHIFT 2
#define DDR_SIZE_MASK 0xff000000
#define KIRKWOOD_SAR_BASE (KIRKWOOD_INT_REGS_BASE + 0x10030)
#define SAR_TCLK_FREQ BIT(21)
#define KIRKWOOD_UART_BASE (KIRKWOOD_INT_REGS_BASE + 0x12000)
#define KIRKWOOD_UARTn_BASE(n) (KIRKWOOD_UART_BASE + ((n) * 0x100))
#define KIRKWOOD_BRIDGE_BASE (KIRKWOOD_INT_REGS_BASE + 0x20000)
#define BRIDGE_RSTOUT_MASK 0x108
#define SOFT_RESET_OUT_EN BIT(2)
#define BRIDGE_SYS_SOFT_RESET 0x10c
#define SOFT_RESET_EN BIT(0)
#define KIRKWOOD_TIMER_BASE (KIRKWOOD_INT_REGS_BASE + 0x20300)
#endif /* __MACH_MVEBU_KIRKWOOD_REGS_H */

16
arch/arm/boards/plathome-openblocks-ax3/plathome-openblocks-ax3.c → arch/arm/mach-mvebu/include/mach/lowlevel.h
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2013
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -13,13 +15,9 @@
*
*/
#include <common.h>
#include <init.h>
#include <mach/mvebu.h>
#ifndef __MACH_LOWLEVEL_H__
#define __MACH_LOWLEVEL_H__
static int plathome_openblocks_ax3_console_init(void)
{
return mvebu_add_uart0();
}
void mvebu_barebox_entry(void);
console_initcall(plathome_openblocks_ax3_console_init);
#endif

44
arch/arm/mach-mvebu/kirkwood.c
View File

@ -16,30 +16,30 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <ns16550.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <ns16550.h>
#include <mach/kirkwood-regs.h>
#include <asm/memory.h>
#include <asm/barebox-arm.h>
#include <mach/kirkwood-regs.h>
#define CONSOLE_UART_BASE KIRKWOOD_UARTn_BASE(CONFIG_MVEBU_CONSOLE_UART)
static struct clk *tclk;
static inline void kirkwood_memory_find(unsigned long *phys_base,
unsigned long *phys_size)
unsigned long *phys_size)
{
void __iomem *sdram_win = IOMEM(KIRKWOOD_SDRAM_WIN_BASE);
int cs;
*phys_base = ~0;
*phys_size = 0;
for (cs = 0; cs < 4; cs++) {
uint32_t base = readl(sdram_win + DDR_BASE_CS_OFF(cs));
uint32_t ctrl = readl(sdram_win + DDR_SIZE_CS_OFF(cs));
u32 base = readl(KIRKWOOD_SDRAM_BASE + DDR_BASE_CSn(cs));
u32 ctrl = readl(KIRKWOOD_SDRAM_BASE + DDR_SIZE_CSn(cs));
/* Skip non-enabled CS */
if (! (ctrl & DDR_SIZE_ENABLED))
if ((ctrl & DDR_SIZE_ENABLED) != DDR_SIZE_ENABLED)
continue;
base &= DDR_BASE_CS_LOW_MASK;
@ -49,34 +49,30 @@ static inline void kirkwood_memory_find(unsigned long *phys_base,
}
}
void __naked __noreturn kirkwood_barebox_entry(void)
{
unsigned long phys_base, phys_size;
kirkwood_memory_find(&phys_base, &phys_size);
writel('E', 0xD0012000);
barebox_arm_entry(phys_base, phys_size, 0);
}
static struct NS16550_plat uart_plat = {
.shift = 2,
};
int kirkwood_add_uart0(void)
static int kirkwood_add_uart(void)
{
uart_plat.clock = clk_get_rate(tclk);
if (!add_ns16550_device(DEVICE_ID_DYNAMIC,
(unsigned int)KIRKWOOD_UART_BASE,
32, IORESOURCE_MEM_32BIT, &uart_plat))
(unsigned int)CONSOLE_UART_BASE, 32,
IORESOURCE_MEM_32BIT, &uart_plat))
return -ENODEV;
return 0;
}
static int kirkwood_init_clocks(void)
{
uint32_t sar = readl(KIRKWOOD_SAR_BASE);
u32 val = readl(KIRKWOOD_SAR_BASE);
unsigned int rate;
if (sar & (1 << KIRKWOOD_TCLK_BIT))
/*
* On Kirkwood, the TCLK frequency can be either
* 166 Mhz or 200 Mhz
*/
if ((val & SAR_TCLK_FREQ) == SAR_TCLK_FREQ)
rate = 166666667;
else
rate = 200000000;
@ -95,16 +91,16 @@ static int kirkwood_init_soc(void)
IORESOURCE_MEM, NULL);
kirkwood_memory_find(&phys_base, &phys_size);
arm_add_mem_device("ram0", phys_base, phys_size);
kirkwood_add_uart();
return 0;
}
postcore_initcall(kirkwood_init_soc);
void __noreturn reset_cpu(unsigned long addr)
{
writel(0x4, KIRKWOOD_CPUCTRL_BASE + 0x8);
writel(0x1, KIRKWOOD_CPUCTRL_BASE + 0xC);
writel(SOFT_RESET_OUT_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_RSTOUT_MASK);
writel(SOFT_RESET_EN, KIRKWOOD_BRIDGE_BASE + BRIDGE_SYS_SOFT_RESET);
for(;;)
;
}

6
arch/arm/boards/globalscale-mirabox/lowlevel.c → arch/arm/mach-mvebu/lowlevel.c
View File

@ -1,5 +1,7 @@
/*
* Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Copyright (C) 2013
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@ -17,7 +19,7 @@
#include <sizes.h>
#include <asm/barebox-arm.h>
#include <asm/barebox-arm-head.h>
#include <mach/mvebu.h>
#include <mach/lowlevel.h>
void __naked barebox_arm_reset_vector(void)
{