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ARM: execute DMB before trying to flush cache 

The CPU write buffer needs to be coherent with the cache, otherwise
we might flush stale entries with the actual data stuck in the cache.

This is really important on newer CPU core with bigger write buffers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Lucas Stach 2017-03-01 15:26:41 +01:00 committed by Sascha Hauer
parent d92ce9b36a
commit 7497685b05
1 changed files with 1 additions and 0 deletions
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arch/arm/cpu/cache-armv7.S
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@ -68,6 +68,7 @@ ENTRY(v7_mmu_cache_flush)
ENDPROC(v7_mmu_cache_flush)
ENTRY(__v7_mmu_cache_flush_invalidate)
mcr p15, 0, r12, c7, c10, 5 @ DMB
mrc p15, 0, r12, c0, c1, 5 @ read ID_MMFR1
tst r12, #0xf << 16 @ hierarchical cache (ARMv7)
mov r12, #0