sysmo-bts
/
barebox
9
0
Fork 0
Code Releases Activity

Merge octopus:/home/git/projects/u-boot-v2

This commit is contained in:
sascha 2007-10-18 11:17:32 +02:00
parent 1b272d80f1 2e36bc0781
commit 75b605bfd2
7 changed files with 106 additions and 417 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-imx/clocksource.c
View File

@ -63,8 +63,7 @@ static int clocksource_init (void)
GPT(GPT_TCTL) = 0; /* We have no udelay by now */
GPT(GPT_TPRER) = 0;
GPT(GPT_TCTL) |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
GPT(GPT_TCTL) |= TCTL_FRR | (1<<TCTL_CLKSOURCE); /* Freerun Mode, PERCLK1 input */
GPT(GPT_TCTL) &= ~TCTL_TEN;
GPT(GPT_TCTL) |= TCTL_TEN; /* Enable timer */

27
board/phycore_imx31/phycore_imx31.c
View File

@ -29,15 +29,14 @@
#include <asm/io.h>
/*
* ?MiB NOR type flash, connected to CS line 0,
* 32MiB NOR type flash, connected to CS line 0,
* data width is <friesel>
*/
static struct device_d cfi_dev = {
.name = "cfi_flash",
.id = "nor0",
.map_base = 0x10000000, /* FIXME */
.size = 16 * 1024 * 1024, /* FIXME */
.map_base = IMX_CS0_BASE,
.size = 32 * 1024 * 1024,
};
/*
@ -47,9 +46,8 @@ static struct device_d cfi_dev = {
static struct device_d sram_dev = {
.name = "sram",
.id = "sram0",
.map_base = 0x10000000, /* FIXME */
.size = 16 * 1024 * 1024, /* FIXME */
.map_base = IMX_CS4_BASE,
.size = 16 * 1024 * 1024,
};
/*
@ -58,7 +56,6 @@ static struct device_d sram_dev = {
static struct device_d nand_dev = {
.name = "cfi_flash_nand",
.id = "nand0",
.map_base = 0x10000000, /* FIXME */
.size = 16 * 1024 * 1024, /* FIXME */
};
@ -71,18 +68,17 @@ static struct device_d nand_dev = {
static struct device_d network_dev = {
.name = "smsc9xxx",
.id = "eth0",
#if 0
.map_base = 0x10000000, /* FIXME */
.map_base = IMX_CS1_BASE,
.size = 16 * 1024 * 1024, /* FIXME */
#endif
};
/* 128MiB */
static struct device_d sdram_dev = {
.name = "ram",
.id = "ram0",
.map_base = 0x08000000, /* FIXME */
.size = 16 * 1024 * 1024, /* FIXME */
.map_base = IMX_SDRAM_CS0,
.size = 128 * 1024 * 1024,
.type = DEVICE_TYPE_DRAM,
};
@ -105,12 +101,11 @@ static int imx31_devices_init(void)
imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL);
imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL);
#if 0
register_device(&cfi_dev);
register_device(&sram_dev);
register_device(&cfi_dev);
register_device(&nand_dev);
register_device(&network_dev);
#endif
register_device(&sdram_dev);
return 0;

7
drivers/serial/serial_imx.c
View File

@ -154,14 +154,17 @@
* create default values for different platforms
*/
#ifdef CONFIG_ARCH_IMX1
# define UCR1_VAL (UCR1_UARTCLKEN)
# define UCR3_VAL 0
# define UCR4_VAL (UCR4_CTSTL_32 | UCR4_REF16)
#endif
#ifdef CONFIG_ARCH_IMX27
# define UCR1_VAL (UCR1_UARTCLKEN)
# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
# define UCR4_VAL UCR4_CTSTL_32
#endif
#ifdef CONFIG_ARCH_IMX31
# define UCR1_VAL (0)
# define UCR3_VAL (0x700 | UCR3_RXDMUXSEL)
# define UCR4_VAL UCR4_CTSTL_32
#endif
@ -186,7 +189,7 @@ static int imx_serial_init_port(struct console_device *cdev)
struct device_d *dev = cdev->dev;
ulong base = dev->map_base;
UCR1(base) = UCR1_UARTCLKEN;
UCR1(base) = UCR1_VAL;
UCR2(base) = UCR2_WS | UCR2_IRTS;
UCR3(base) = UCR3_VAL;
UCR4(base) = UCR4_VAL;
@ -199,7 +202,7 @@ static int imx_serial_init_port(struct console_device *cdev)
/* Configure FIFOs */
UFCR(base) = 0xa81;
#ifdef CONFIG_ARCH_IMX27
#if defined(CONFIG_ARCH_IMX27) || defined(CONFIG_ARCH_IMX31)
ONEMS(base) = imx_serial_reffreq(base) / 1000;
#endif

24
include/asm-arm/arch-imx/imx-regs.h
View File

@ -31,9 +31,11 @@
# ifndef __ASSEMBLY__
# define __REG(x) (*((volatile u32 *)(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# define __REG16(x) (*(volatile u16 *)(x))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# define __REG16(x) (x)
# define __REG2(x,y) ((x)+(y))
#endif
@ -98,24 +100,4 @@
#define GPIO_AOUT (1 << 13)
#define GPIO_BOUT (1 << 14)
/* General purpose timers registers */
#define GPT_TCTL 0x00
#define GPT_TPRER 0x04
#define GPT_TCMP 0x08
#define GPT_TCR 0x0c
#define GPT_TCN 0x10
#define GPT_TSTAT 0x14
/* General purpose timers bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<8) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#endif /* _IMX_REGS_H */

24
include/asm-arm/arch-imx/imx1-regs.h
View File

@ -215,5 +215,27 @@
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
#endif
/*
* Definitions for the clocksource driver
*/
/* Part 1: Registers */
# define GPT_TCTL 0x00
# define GPT_TPRER 0x04
# define GPT_TCMP 0x08
# define GPT_TCR 0x0c
# define GPT_TCN 0x10
# define GPT_TSTAT 0x14
/* Part 2: Bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<8) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (1) /* Clock source bit position */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#endif /* _IMX1_REGS_H */

24
include/asm-arm/arch-imx/imx27-regs.h
View File

@ -251,5 +251,27 @@
#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
#endif /* _IMX27_REGS_H */
/*
* Definitions for the clocksource driver
*/
/* Part 1: Registers */
# define GPT_TCTL 0x00
# define GPT_TPRER 0x04
# define GPT_TCMP 0x08
# define GPT_TCR 0x0c
# define GPT_TCN 0x10
# define GPT_TSTAT 0x14
/* Part 2: Bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<8) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (1) /* Clock source bit position */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#endif /* _IMX27_REGS_H */

414
include/asm-arm/arch-imx/imx31-regs.h
View File

@ -36,6 +36,43 @@
#define IMX_RTC_BASE 0x53FD8000
#define IMX_TIM1_BASE 0x53F90000
#define IMX_SDRAM_CS0 0x80000000
#define IMX_SDRAM_CS1 0x90000000
#define IMX_CS0_BASE 0xA0000000
#define IMX_CS1_BASE 0xA8000000
#define IMX_CS2_BASE 0xB0000000
#define IMX_CS3_BASE 0xB2000000
#define IMX_CS4_BASE 0xB4000000
#define IMX_CS5_BASE 0xB6000000
/*
* Definitions for the clocksource driver
*
* These defines are using the i.MX1/27 notation
* to reuse the clocksource code for these CPUs
* on the i.MX31
*/
/* Part 1: Registers */
#define GPT_TCTL 0x00
#define GPT_TPRER 0x04
#define GPT_TCMP 0x10
#define GPT_TCR 0x1c
#define GPT_TCN 0x24
#define GPT_TSTAT 0x08
/* Part 2: Bitfields */
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<9) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (6) /* Clock source bit position */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#if 0
#define IMX_IO_BASE 0x00200000
@ -74,384 +111,13 @@
/*
* Watchdog Registers
*/
#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */
#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */
#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */
#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */
#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */
/* important definition of some bits of WCR */
#define WCR_WDE 0x04
#if 0
/*
* SYSCTRL Registers
*/
#define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */
#define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */
#define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */
/*
* Chip Select Registers
*/
#define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */
#define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */
#define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */
#define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */
#define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */
#define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */
#define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */
#define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */
#define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */
#define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */
#define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */
#define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */
#define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */
/*
* SDRAM controller registers
*/
#define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */
#define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */
#define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */
#define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */
/*
* PLL registers
*/
#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
#define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
#define CSCR_MPLL_RESTART (1<<21)
/*
* assignements for GPIO alternate/primary functions
*
* FIXME: This list is not completed. The correct directions are
* missing on some (many) pins
*/
#define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 )
#define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
#define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
#define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
#define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
#define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
#define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
#define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
#define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
#define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
#define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
#define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
#define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
#define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
#define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
#define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
#define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
#define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
#define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
#define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
#define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 )
#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
#define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
#define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
#define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
#define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
#define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
#define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
#define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
#define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
#define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
#define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
#define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
#define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
#define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
#define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
#define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
#define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
#define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
#define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
#define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 )
#define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
#define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 )
#define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
#define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 )
#define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
#define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
#define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
#define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
#define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
#define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
#define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
#define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
#define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
#define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
#define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
#define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
#define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
#define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
#define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
#define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
#define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
#define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
#define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
#define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
#define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
#define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
#define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
#define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
#define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
#define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
#define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
#define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
#define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
#define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
#define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
#define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
#define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
#define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
#define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
#define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
#define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 )
#define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
#define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
#define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 )
#define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
#define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
#define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
#define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
#define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
#define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
#define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
#define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
#define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
#define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
#define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
#define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
#define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
#define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
#define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
#define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
#define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
#define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
#define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
#define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
#define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
#define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
#define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
#define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
#define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
#define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
#define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
#define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 )
/*
* DMA Controller
*/
#define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
#define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
#define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
#define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
#define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
#define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
#define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
#define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
#define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
#define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
#define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
#define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
#define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
#define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
#define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
#define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
#define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /*<2A>Control Registers */
#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
#define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
/* TODO: define DMA_REQ lines */
#define DCR_DRST (1<<1)
#define DCR_DEN (1<<0)
#define DBTOCR_EN (1<<15)
#define DBTOCR_CNT(x) ((x) & 0x7fff )
#define CNTR_CNT(x) ((x) & 0xffffff )
#define CCR_DMOD_LINEAR ( 0x0 << 12 )
#define CCR_DMOD_2D ( 0x1 << 12 )
#define CCR_DMOD_FIFO ( 0x2 << 12 )
#define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
#define CCR_SMOD_LINEAR ( 0x0 << 10 )
#define CCR_SMOD_2D ( 0x1 << 10 )
#define CCR_SMOD_FIFO ( 0x2 << 10 )
#define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
#define CCR_MDIR_DEC (1<<9)
#define CCR_MSEL_B (1<<8)
#define CCR_DSIZ_32 ( 0x0 << 6 )
#define CCR_DSIZ_8 ( 0x1 << 6 )
#define CCR_DSIZ_16 ( 0x2 << 6 )
#define CCR_SSIZ_32 ( 0x0 << 4 )
#define CCR_SSIZ_8 ( 0x1 << 4 )
#define CCR_SSIZ_16 ( 0x2 << 4 )
#define CCR_REN (1<<3)
#define CCR_RPT (1<<2)
#define CCR_FRC (1<<1)
#define CCR_CEN (1<<0)
#define RTOR_EN (1<<15)
#define RTOR_CLK (1<<14)
#define RTOR_PSC (1<<13)
/*
* LCD Controller
*/
#define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
#define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
#define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
#define SIZE_YMAX(y) ( (y) & 0x1ff )
#define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
#define VPW_VPW(x) ( (x) & 0x3ff )
#define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
#define CPOS_CC1 (1<<31)
#define CPOS_CC0 (1<<30)
#define CPOS_OP (1<<28)
#define CPOS_CXP(x) (((x) & 3ff) << 16)
#define CPOS_CYP(y) ((y) & 0x1ff)
#define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
#define LCWHB_BK_EN (1<<31)
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
#define LCWHB_CH(h) (((h) & 0x1f) << 16)
#define LCWHB_BD(x) ((x) & 0xff)
#define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
#define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
#define PCR_TFT (1<<31)
#define PCR_COLOR (1<<30)
#define PCR_PBSIZ_1 (0<<28)
#define PCR_PBSIZ_2 (1<<28)
#define PCR_PBSIZ_4 (2<<28)
#define PCR_PBSIZ_8 (3<<28)
#define PCR_BPIX_1 (0<<25)
#define PCR_BPIX_2 (1<<25)
#define PCR_BPIX_4 (2<<25)
#define PCR_BPIX_8 (3<<25)
#define PCR_BPIX_12 (4<<25)
#define PCR_BPIX_16 (4<<25)
#define PCR_PIXPOL (1<<24)
#define PCR_FLMPOL (1<<23)
#define PCR_LPPOL (1<<22)
#define PCR_CLKPOL (1<<21)
#define PCR_OEPOL (1<<20)
#define PCR_SCLKIDLE (1<<19)
#define PCR_END_SEL (1<<18)
#define PCR_END_BYTE_SWAP (1<<17)
#define PCR_REV_VS (1<<16)
#define PCR_ACD_SEL (1<<15)
#define PCR_ACD(x) (((x) & 0x7f) << 8)
#define PCR_SCLK_SEL (1<<7)
#define PCR_SHARP (1<<6)
#define PCR_PCD(x) ((x) & 0x3f)
#define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
#define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
#define HCR_H_WAIT_2(x) ((x) & 0xff)
#define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
#define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
#define VCR_V_WAIT_2(x) ((x) & 0xff)
#define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
#define POS_POS(x) ((x) & 1f)
#define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
#define LSCR1_GRAY1(x) (((x) & 0xf) << 4)
#define LSCR1_GRAY2(x) ((x) & 0xf)
#define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
#define PWMR_CLS(x) (((x) & 0x1ff) << 16)
#define PWMR_LDMSK (1<<15)
#define PWMR_SCR1 (1<<10)
#define PWMR_SCR0 (1<<9)
#define PWMR_CC_EN (1<<8)
#define PWMR_PW(x) ((x) & 0xff)
#define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
#define DMACR_BURST (1<<31)
#define DMACR_HM(x) (((x) & 0xf) << 16)
#define DMACR_TM(x) ((x) &0xf)
#define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
#define RMCR_LCDC_EN (1<<1)
#define RMCR_SELF_REF (1<<0)
#define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
#define LCDICR_INT_SYN (1<<2)
#define LCDICR_INT_CON (1)
#define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
#define LCDISR_UDR_ERR (1<<3)
#define LCDISR_ERR_RES (1<<2)
#define LCDISR_EOF (1<<1)
#define LCDISR_BOF (1<<0)
/*
* UART port definitions in the serial driver
*/
/*
* General purpose timers registers
*/
#define TCTL1 __REG(IMX_TIM1_BASE)
#define TPRER1 __REG(IMX_TIM1_BASE + 0x4)
#define TCMP1 __REG(IMX_TIM1_BASE + 0x8)
#define TCR1 __REG(IMX_TIM1_BASE + 0xc)
#define TCN1 __REG(IMX_TIM1_BASE + 0x10)
#define TSTAT1 __REG(IMX_TIM1_BASE + 0x14)
#define TCTL2 __REG(IMX_TIM2_BASE)
#define TPRER2 __REG(IMX_TIM2_BASE + 0x4)
#define TCMP2 __REG(IMX_TIM2_BASE + 0x8)
#define TCR2 __REG(IMX_TIM2_BASE + 0xc)
#define TCN2 __REG(IMX_TIM2_BASE + 0x10)
#define TSTAT2 __REG(IMX_TIM2_BASE + 0x14)
/*
* General purpose timers bitfields
*/
#define TCTL_SWR (1<<15) /* Software reset */
#define TCTL_FRR (1<<8) /* Freerun / restart */
#define TCTL_CAP (3<<6) /* Capture Edge */
#define TCTL_OM (1<<5) /* output mode */
#define TCTL_IRQEN (1<<4) /* interrupt enable */
#define TCTL_CLKSOURCE (7<<1) /* Clock source */
#define TCTL_TEN (1) /* Timer enable */
#define TPRER_PRES (0xff) /* Prescale */
#define TSTAT_CAPT (1<<1) /* Capture event */
#define TSTAT_COMP (1) /* Compare event */
#endif
/*
* ????????????
*/