Add Garz+Fricke Neso support
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
a398a920b6
commit
75f99628fc
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@ -77,6 +77,7 @@ board-$(CONFIG_MACH_PCM038) := pcm038
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board-$(CONFIG_MACH_PCM043) := pcm043
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board-$(CONFIG_MACH_PM9263) := pm9263
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board-$(CONFIG_MACH_SCB9328) := scb9328
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board-$(CONFIG_MACH_NESO) := guf-neso
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machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
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@ -16,6 +16,7 @@ config ARCH_TEXT_BASE
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default 0x87f00000 if MACH_PCM037
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default 0x87f00000 if MACH_PCM043
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default 0x08f80000 if MACH_SCB9328
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default 0xa7e00000 if MACH_NESO
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config BOARDINFO
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default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
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@ -30,6 +31,7 @@ config BOARDINFO
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default "Phytec phyCORE-i.MX31" if MACH_PCM037
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default "Phytec phyCORE-i.MX35" if MACH_PCM043
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default "Synertronixx scb9328" if MACH_SCB9328
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default "Garz+Fricke Neso" if MACH_NESO
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config ARCH_HAS_FEC_IMX
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bool
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@ -195,6 +197,14 @@ config MACH_PCM038
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Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
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with a Freescale i.MX27 Processor
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config MACH_NESO
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bool "Garz+Fricke Neso"
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select MACH_HAS_LOWLEVEL_INIT
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select HAVE_MMU
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help
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Say Y here if you are using the Garz+Fricke Neso board equipped
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with a Freescale i.MX27 Processor
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endchoice
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endif
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@ -0,0 +1,5 @@
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obj-y += lowlevel.o
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obj-y += board.o
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obj-y += pll_init.o
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@ -0,0 +1,401 @@
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/*
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* Copyright (C) 2010 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <environment.h>
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#include <fec.h>
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#include <notifier.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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#include <nand.h>
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#include <command.h>
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#include <spi/spi.h>
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#include <usb/isp1504.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/armlinux.h>
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#include <asm/mach-types.h>
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#include <mach/gpio.h>
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#include <mach/spi.h>
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#include <mach/imx-regs.h>
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#include <mach/iomux-mx27.h>
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#include <mach/imx-nand.h>
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#include <mach/imx-pll.h>
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#include <mach/imxfb.h>
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/* two pins are controlling the CS signals to the USB phys */
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#define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20)
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#define OTG_PHY_CS_GPIO (GPIO_PORTF + 19)
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/* two pins are controlling the display and its backlight */
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#define LCD_POWER_GPIO (GPIO_PORTF + 18)
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#define BACKLIGHT_POWER_GPIO (GPIO_PORTE + 5)
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static struct memory_platform_data ram_pdata = {
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.name = "ram0",
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.flags = DEVFS_RDWR,
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};
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static struct device_d sdram_dev = {
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.name = "mem",
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.map_base = 0xa0000000,
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.size = 128 * 1024 * 1024,
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.platform_data = &ram_pdata,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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.phy_addr = 31,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx",
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.map_base = 0x1002b000,
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.platform_data = &fec_info,
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};
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static struct imx_nand_platform_data nand_info = {
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.width = 1,
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.hw_ecc = 1,
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.flash_bbt = 1,
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};
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static struct device_d nand_dev = {
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.name = "imx_nand",
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.map_base = 0xd8000000,
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.platform_data = &nand_info,
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};
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static struct imx_fb_videomode imxfb_mode = {
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.mode = {
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.name = "CPT CLAA070LC0JCT",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = KHZ2PICOS(27000),
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.hsync_len = 1, /* DE only sync */
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.left_margin = 50,
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.right_margin = 50,
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.vsync_len = 1, /* DE only sync */
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.upper_margin = 10,
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.lower_margin = 10,
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},
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/*
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* - TFT style panel
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* - clk enabled while idle
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* - clock inverted
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* - data not inverted
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* - data enable high active
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*/
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.pcr = PCR_TFT |
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PCR_COLOR |
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PCR_PBSIZ_8 |
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PCR_BPIX_16 |
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PCR_CLKPOL |
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PCR_SCLK_SEL |
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PCR_LPPOL |
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PCR_FLMPOL,
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.bpp = 16, /* TODO 32 bit does not work: The 'green' component is lacking in this mode */
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};
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static void neso_fb_enable(int enable)
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{
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gpio_direction_output(LCD_POWER_GPIO, enable);
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gpio_direction_output(BACKLIGHT_POWER_GPIO, enable);
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}
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static struct imx_fb_platform_data neso_fb_data = {
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.mode = &imxfb_mode,
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.pwmr = 0x00000000, /* doesn't matter */
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.lscr1 = 0x00120300, /* doesn't matter */
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/* dynamic mode -> using the reset values (as recommended in the datasheet) */
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.dmacr = (0 << 31) | (4 << 16) | 96,
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.enable = neso_fb_enable,
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.framebuffer_ovl = (void *)0xa7f00000,
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};
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static struct device_d imxfb_dev = {
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.name = "imxfb",
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.map_base = 0x10021000,
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.size = 0x1000,
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.platform_data = &neso_fb_data,
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};
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#ifdef CONFIG_USB
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static struct device_d usbh2_dev = {
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.name = "ehci",
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.map_base = IMX_OTG_BASE + 0x400,
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.size = 0x200,
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};
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static void neso_usbh_init(void)
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{
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uint32_t temp;
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temp = readl(IMX_OTG_BASE + 0x600);
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temp &= ~((3 << 21) | 1);
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temp |= (1 << 5) | (1 << 16) | (1 << 19) | (1 << 20) | (1<<11);
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writel(temp, IMX_OTG_BASE + 0x600);
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temp = readl(IMX_OTG_BASE + 0x584);
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temp &= ~(3 << 30);
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temp |= 2 << 30;
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writel(temp, IMX_OTG_BASE + 0x584);
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mdelay(10);
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gpio_set_value(USBH2_PHY_CS_GPIO, 0);
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mdelay(10);
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isp1504_set_vbus_power((void *)(IMX_OTG_BASE + 0x570), 1);
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}
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#endif
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#ifdef CONFIG_MMU
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static void neso_mmu_init(void)
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{
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mmu_init();
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arm_create_section(0xa0000000, 0xa0000000, 128, PMD_SECT_DEF_CACHED);
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arm_create_section(0xb0000000, 0xa0000000, 128, PMD_SECT_DEF_UNCACHED);
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setup_dma_coherent(0x10000000);
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#if TEXT_BASE & (0x100000 - 1)
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#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
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#else
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arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED);
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#endif
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mmu_enable();
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}
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#else
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static void neso_mmu_init(void)
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{
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}
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#endif
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static int neso_devices_init(void)
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{
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int i;
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unsigned int mode[] = {
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/* UART1 */
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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/* FEC */
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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/* SSI1 connected in AC97 style */
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PC20_PF_SSI1_FS,
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PC21_PF_SSI1_RXD,
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PC22_PF_SSI1_TXD,
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PC23_PF_SSI1_CLK,
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/* LED 1 */
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(GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT),
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/* LED 2 */
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(GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT),
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/* CTOUCH reset */
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(GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT),
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/* CTOUCH IRQ */
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(GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN),
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/* RTC IRQ */
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(GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN),
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/* SD change card detection */
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(GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN),
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/* SDHC1*/
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PE18_PF_SD1_D0,
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PE19_PF_SD1_D1,
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PE20_PF_SD1_D2,
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PE21_PF_SD1_D3,
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PE22_PF_SD1_CMD,
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PE23_PF_SD1_CLK,
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/* I2C1 */
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PD17_PF_I2C_DATA,
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PD18_PF_I2C_CLK,
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/* I2C2, for CTOUCH */
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PC5_PF_I2C2_SDA,
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PC6_PF_I2C2_SCL,
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/* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */
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PE17_PF_RESET_OUT,
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/* USB host */
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(USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
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PA0_PF_USBH2_CLK,
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PA1_PF_USBH2_DIR,
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PA3_PF_USBH2_NXT,
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PA4_PF_USBH2_STP,
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PD22_AF_USBH2_DATA0,
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PD24_AF_USBH2_DATA1,
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PD23_AF_USBH2_DATA2,
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PD20_AF_USBH2_DATA3,
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PD19_AF_USBH2_DATA4,
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PD26_AF_USBH2_DATA5,
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PD21_AF_USBH2_DATA6,
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PA2_PF_USBH2_DATA7,
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/* USB OTG */
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(OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
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PE24_PF_USBOTG_CLK,
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PE2_PF_USBOTG_DIR,
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PE0_PF_USBOTG_NXT,
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PE1_PF_USBOTG_STP,
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PC9_PF_USBOTG_DATA0,
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PC11_PF_USBOTG_DATA1,
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PC10_PF_USBOTG_DATA2,
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PC13_PF_USBOTG_DATA3,
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PC12_PF_USBOTG_DATA4,
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PC7_PF_USBOTG_DATA5,
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PC8_PF_USBOTG_DATA6,
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PE25_PF_USBOTG_DATA7,
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/* Display signals */
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(LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA31_PF_OE_ACD, /* DE */
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/* Backlight PWM (Use as gpio) */
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(BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT),
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};
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/* reset the chip select lines to the USB/OTG phys to avoid any hang */
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gpio_direction_output(OTG_PHY_CS_GPIO, 1);
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gpio_direction_output(USBH2_PHY_CS_GPIO, 1);
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neso_mmu_init();
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/* initialize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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register_device(&nand_dev);
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register_device(&sdram_dev);
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register_device(&imxfb_dev);
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#ifdef CONFIG_USB
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neso_usbh_init();
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register_device(&usbh2_dev);
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#endif
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register_device(&fec_dev);
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devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
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dev_add_bb_dev("self_raw", "self0");
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devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw");
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dev_add_bb_dev("env_raw", "env0");
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armlinux_add_dram(&sdram_dev);
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armlinux_set_bootparams((void *)0xa0000100);
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armlinux_set_architecture(MACH_TYPE_NESO);
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return 0;
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}
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device_initcall(neso_devices_init);
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static struct device_d neso_serial_device = {
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.name = "imx_serial",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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};
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static int neso_console_init(void)
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{
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register_device(&neso_serial_device);
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return 0;
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}
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console_initcall(neso_console_init);
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extern void *neso_pll_init, *neso_pll_init_end;
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static int neso_pll(void)
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{
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void *vram = (void *)0xffff4c00;
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void (*pllfunc)(void) = vram;
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printf("initialising PLLs\n");
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memcpy(vram, &neso_pll_init, 0x100);
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console_flush();
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pllfunc();
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/* clock gating enable */
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GPCR = 0x00050f08;
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PCDR0 = 0x130410c3;
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PCDR1 = 0x09030911;
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/* Clocks have changed. Notify clients */
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clock_notifier_call_chain();
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return 0;
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}
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late_initcall(neso_pll);
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@ -0,0 +1,26 @@
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/*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Global defintions for the ARM i.MX27 based pcm038
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#!/bin/sh
|
||||
|
||||
machine=guf-neso
|
||||
eth0.serverip=
|
||||
user=
|
||||
|
||||
# use 'dhcp' to do dhcp in barebox and in kernel
|
||||
# use 'none' if you want to skip kernel ip autoconfiguration
|
||||
ip=dhcp
|
||||
|
||||
# or set your networking parameters here
|
||||
#eth0.ipaddr=a.b.c.d
|
||||
#eth0.netmask=a.b.c.d
|
||||
#eth0.gateway=a.b.c.d
|
||||
#eth0.serverip=a.b.c.d
|
||||
|
||||
# can be either 'net', 'nor' or 'nand'
|
||||
kernel_loc=net
|
||||
# can be either 'net', 'nor', 'nand' or 'initrd'
|
||||
rootfs_loc=net
|
||||
|
||||
# can be either 'jffs2' or 'ubifs'
|
||||
rootfs_type=ubifs
|
||||
rootfsimage=root-$machine.$rootfs_type
|
||||
|
||||
# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo
|
||||
kernelimage_type=zimage
|
||||
kernelimage=zImage-$machine
|
||||
#kernelimage_type=uimage
|
||||
#kernelimage=uImage-$machine
|
||||
#kernelimage_type=raw
|
||||
#kernelimage=Image-$machine
|
||||
#kernelimage_type=raw_lzo
|
||||
#kernelimage=Image-$machine.lzo
|
||||
|
||||
if [ -n $user ]; then
|
||||
kernelimage="$user"-"$kernelimage"
|
||||
nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine"
|
||||
rootfsimage="$user"-"$rootfsimage"
|
||||
else
|
||||
nfsroot="$eth0.serverip:/path/to/nfs/root"
|
||||
fi
|
||||
|
||||
autoboot_timeout=3
|
||||
|
||||
bootargs="console=ttymxc0,115200"
|
||||
|
||||
nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)"
|
||||
rootfs_mtdblock_nand=3
|
||||
|
||||
# set a fancy prompt (if support is compiled in)
|
||||
PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
|
||||
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
*
|
||||
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <mach/imx-pll.h>
|
||||
#include <mach/esdctl.h>
|
||||
#include <asm/cache-l2x0.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/imx-nand.h>
|
||||
#include <asm/barebox-arm.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm-generic/memory_layout.h>
|
||||
|
||||
static void __bare_init __naked insdram(void)
|
||||
{
|
||||
uint32_t r;
|
||||
|
||||
PCCR1 |= PCCR1_NFC_BAUDEN;
|
||||
|
||||
/* setup a stack to be able to call imx_nand_load_image() */
|
||||
r = STACK_BASE + STACK_SIZE - 12;
|
||||
__asm__ __volatile__("mov sp, %0" : : "r"(r));
|
||||
|
||||
imx_nand_load_image((void *)TEXT_BASE, 256 * 1024);
|
||||
|
||||
board_init_lowlevel_return();
|
||||
}
|
||||
|
||||
#define ESDCTL0_VAL (ESDCTL0_SDE | ESDCTL0_ROW13 | ESDCTL0_COL10)
|
||||
|
||||
void __bare_init __naked board_init_lowlevel(void)
|
||||
{
|
||||
uint32_t r;
|
||||
int i;
|
||||
unsigned int *trg, *src;
|
||||
|
||||
/* ahb lite ip interface */
|
||||
AIPI1_PSR0 = 0x20040304;
|
||||
AIPI1_PSR1 = 0xDFFBFCFB;
|
||||
AIPI2_PSR0 = 0x00000000;
|
||||
AIPI2_PSR1 = 0xFFFFFFFF;
|
||||
|
||||
/* Skip SDRAM initialization if we run from RAM */
|
||||
r = get_pc();
|
||||
if (r > 0xa0000000 && r < 0xb0000000)
|
||||
board_init_lowlevel_return();
|
||||
|
||||
/*
|
||||
* DDR on CSD0
|
||||
*/
|
||||
writel(0x00000008, ESDMISC); /* Enable DDR SDRAM operation */
|
||||
|
||||
DSCR(3) = 0x55555555; /* Set the driving strength */
|
||||
DSCR(5) = 0x55555555;
|
||||
DSCR(6) = 0x55555555;
|
||||
DSCR(7) = 0x00005005;
|
||||
DSCR(8) = 0x15555555;
|
||||
|
||||
writel(0x00000004, ESDMISC); /* Initial reset */
|
||||
writel(0x006ac73a, ESDCFG0);
|
||||
|
||||
writel(ESDCTL0_VAL | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); /* precharge CSD0 all banks */
|
||||
writel(0x00000000, 0xA0000F00); /* CSD0 precharge address (A10 = 1) */
|
||||
writel(ESDCTL0_VAL | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
writel(0, 0xa0000f00);
|
||||
|
||||
writel(ESDCTL0_VAL | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0);
|
||||
|
||||
writeb(0xda, 0xa0000033);
|
||||
writeb(0xff, 0xa1000000);
|
||||
writel(ESDCTL0_VAL | ESDCTL0_DSIZ_31_0 | ESDCTL0_REF4 |
|
||||
ESDCTL0_BL | ESDCTL0_SMODE_NORMAL, ESDCTL0);
|
||||
|
||||
#ifdef CONFIG_NAND_IMX_BOOT
|
||||
/* skip NAND boot if not running from NFC space */
|
||||
r = get_pc();
|
||||
if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800)
|
||||
board_init_lowlevel_return();
|
||||
|
||||
src = (unsigned int *)IMX_NFC_BASE;
|
||||
trg = (unsigned int *)TEXT_BASE;
|
||||
|
||||
/* Move ourselves out of NFC SRAM */
|
||||
for (i = 0; i < 0x800 / sizeof(int); i++)
|
||||
*trg++ = *src++;
|
||||
|
||||
/* Jump to SDRAM */
|
||||
r = (unsigned int)&insdram;
|
||||
__asm__ __volatile__("mov pc, %0" : : "r"(r));
|
||||
#else
|
||||
board_init_lowlevel_return();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#include <config.h>
|
||||
#include <mach/imx-regs.h>
|
||||
#include <mach/imx-pll.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#define writel(val, reg) \
|
||||
ldr r0, =reg; \
|
||||
ldr r1, =val; \
|
||||
str r1, [r0];
|
||||
|
||||
#define CSCR_VAL CSCR_USB_DIV(3) | \
|
||||
CSCR_SD_CNT(3) | \
|
||||
CSCR_MSHC_SEL | \
|
||||
CSCR_H264_SEL | \
|
||||
CSCR_SSI1_SEL | \
|
||||
CSCR_SSI2_SEL | \
|
||||
CSCR_MCU_SEL | \
|
||||
CSCR_ARM_SRC_MPLL | \
|
||||
CSCR_SP_SEL | \
|
||||
CSCR_ARM_DIV(0) | \
|
||||
CSCR_FPM_EN | \
|
||||
CSCR_SPEN | \
|
||||
CSCR_MPEN | \
|
||||
CSCR_AHB_DIV(1)
|
||||
|
||||
ENTRY(neso_pll_init)
|
||||
|
||||
writel(IMX_PLL_PD(0) |
|
||||
IMX_PLL_MFD(51) |
|
||||
IMX_PLL_MFI(7) |
|
||||
IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */
|
||||
|
||||
writel(IMX_PLL_PD(1) |
|
||||
IMX_PLL_MFD(12) |
|
||||
IMX_PLL_MFI(9) |
|
||||
IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */
|
||||
|
||||
writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
|
||||
|
||||
ldr r2, =16000
|
||||
1:
|
||||
subs r2, r2, #1
|
||||
nop
|
||||
bcs 1b
|
||||
|
||||
mov pc, lr
|
||||
ENDPROC(neso_pll_init)
|
||||
|
||||
Loading…
Reference in New Issue