i.MX: clk: Add IMX_PLLV3_SYS_VF610 subtype
Add IMX_PLLV3_SYS_VF610 subtype to pllv3 code to be able to control and re-clock PLL1 and PLL2 on Vybrid SoC. This commit also introduces imx_clk_pllv3_locked which allows the user to create PLLv3 and specify how it should be polled for "locked" status (used in .set_rate callback) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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390f49096e
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@ -26,6 +26,8 @@
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#define PLL_NUM_OFFSET 0x10
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#define PLL_DENOM_OFFSET 0x20
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#define SYS_VF610_PLL_OFFSET 0x10
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#define BM_PLL_POWER (0x1 << 12)
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#define BM_PLL_ENABLE (0x1 << 13)
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#define BM_PLL_BYPASS (0x1 << 16)
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@ -38,6 +40,8 @@ struct clk_pllv3 {
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u32 div_mask;
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u32 div_shift;
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const char *parent;
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void __iomem *lock_reg;
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u32 lock_mask;
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};
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#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk)
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@ -279,6 +283,88 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
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.disable = clk_pllv3_disable,
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};
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static unsigned long clk_pllv3_sys_vf610_recalc_rate(struct clk *clk,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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u32 mfn = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
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u32 mfd = readl(pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
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u32 div = (readl(pll->base) & pll->div_mask) ? 22 : 20;
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return (parent_rate * div) + ((parent_rate / mfd) * mfn);
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}
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static long clk_pllv3_sys_vf610_round_rate(struct clk *clk, unsigned long rate,
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unsigned long *prate)
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{
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unsigned long parent_rate = *prate;
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unsigned long min_rate = parent_rate * 20;
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unsigned long max_rate = 528000000;
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u32 mfn, mfd = 1000000;
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u64 temp64;
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if (rate >= max_rate)
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return max_rate;
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else if (rate < min_rate)
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rate = min_rate;
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temp64 = (u64) (rate - 20 * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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return parent_rate * 20 + parent_rate / mfd * mfn;
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}
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static int clk_pllv3_sys_vf610_set_rate(struct clk *clk, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pllv3 *pll = to_clk_pllv3(clk);
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unsigned long min_rate = parent_rate * 20;
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unsigned long max_rate = 528000000;
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u32 val;
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u32 mfn, mfd = 1000000;
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u64 temp64;
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if (rate < min_rate || rate > max_rate)
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return -EINVAL;
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val = readl(pll->base);
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if (rate == max_rate) {
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writel(0, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
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val |= pll->div_mask;
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writel(val, pll->base);
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return 0;
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} else {
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val &= ~pll->div_mask;
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}
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temp64 = (u64) (rate - 20 * parent_rate);
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temp64 *= mfd;
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do_div(temp64, parent_rate);
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mfn = temp64;
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writel(val, pll->base);
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writel(mfn, pll->base + SYS_VF610_PLL_OFFSET + PLL_NUM_OFFSET);
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writel(mfd, pll->base + SYS_VF610_PLL_OFFSET + PLL_DENOM_OFFSET);
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while (!(readl(pll->lock_reg) & pll->lock_mask))
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;
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return 0;
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}
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static const struct clk_ops clk_pllv3_sys_vf610_ops = {
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.enable = clk_pllv3_enable,
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.disable = clk_pllv3_disable,
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.recalc_rate = clk_pllv3_sys_vf610_recalc_rate,
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.round_rate = clk_pllv3_sys_vf610_round_rate,
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.set_rate = clk_pllv3_sys_vf610_set_rate,
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};
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struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent, void __iomem *base,
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u32 div_mask)
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@ -290,6 +376,9 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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pll = xzalloc(sizeof(*pll));
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switch (type) {
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case IMX_PLLV3_SYS_VF610:
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ops = &clk_pllv3_sys_vf610_ops;
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break;
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case IMX_PLLV3_SYS:
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ops = &clk_pllv3_sys_ops;
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break;
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@ -327,3 +416,22 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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return &pll->clk;
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}
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struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
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const char *parent, void __iomem *base,
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u32 div_mask, void __iomem *lock_reg, u32 lock_mask)
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{
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struct clk *clk;
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struct clk_pllv3 *pll;
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clk = imx_clk_pllv3(type, name, parent, base, div_mask);
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if (IS_ERR(clk))
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return clk;
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pll = to_clk_pllv3(clk);
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pll->lock_reg = lock_reg;
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pll->lock_mask = lock_mask;
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return clk;
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}
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@ -78,6 +78,7 @@ struct clk *imx_clk_pllv2(const char *name, const char *parent,
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enum imx_pllv3_type {
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IMX_PLLV3_GENERIC,
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IMX_PLLV3_SYS,
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IMX_PLLV3_SYS_VF610,
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IMX_PLLV3_USB,
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IMX_PLLV3_USB_VF610,
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IMX_PLLV3_AV,
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@ -89,6 +90,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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const char *parent, void __iomem *base,
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u32 div_mask);
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struct clk *imx_clk_pllv3_locked(enum imx_pllv3_type type, const char *name,
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const char *parent, void __iomem *base,
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u32 div_mask, void __iomem *lock_reg, u32 lock_mask);
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struct clk *imx_clk_pfd(const char *name, const char *parent,
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void __iomem *reg, u8 idx);
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