[i.MX]: Basic board support for the Freescale i.MX27 eval board
This commit is contained in:
Sascha Hauer
parent
d5caf5ec5b
commit
7b4e9c4a82
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@ -10,6 +10,7 @@ ARM type:
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- @subpage pcm037
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- @subpage pcm038
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- @subpage imx27ads
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- @subpage scb9328
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- @subpage netx
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@ -8,6 +8,7 @@ config ARCH_TEXT_BASE
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default 0x81f00000 if MACH_NXDB500
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default 0x21e00000 if MACH_ECO920
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default 0xa0000000 if MACH_PCM038
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default 0xa0000000 if MACH_IMX27ADS
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default 0x87f00000 if MACH_PCM037
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#
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#
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@ -21,6 +22,9 @@ config BOARDINFO
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config BOARDINFO
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default "Phytec phyCORE-i.MX27" if MACH_PCM038
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config BOARDINFO
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default "Freescale i.MX27 ADS" if MACH_IMX27ADS
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config BOARDINFO
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default "Phytec phyCORE-i.MX31" if MACH_PCM037
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@ -98,6 +102,14 @@ config MACH_PCM038
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Say Y here if you are using Phytec's phyCORE-i.MX27 (pcm038) equipped
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with a Freescale i.MX27 Processor
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config MACH_IMX27ADS
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bool "Freescale i.MX27ADS"
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select HAS_CFI
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select ARCH_IMX27
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help
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Say Y here if you are using the Freescale i.MX27ads board equipped
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with a Freescale i.MX27 Processor
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config MACH_ECO920
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bool "eco920"
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select HAS_AT91_ETHER
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@ -10,6 +10,7 @@ board-$(CONFIG_MACH_MX1ADS) := mx1ads
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board-$(CONFIG_MACH_ECO920) := eco920
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board-$(CONFIG_MACH_SCB9328) := scb9328
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board-$(CONFIG_MACH_PCM038) := pcm038
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board-$(CONFIG_MACH_IMX27ADS) := imx27ads
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board-$(CONFIG_MACH_NXDB500) := netx
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board-$(CONFIG_MACH_PCM037) := pcm037
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# FIXME "cpu-y" never used on ARM!
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@ -0,0 +1,3 @@
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obj-y += lowlevel_init.o
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obj-y += imx27ads.o
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@ -0,0 +1,36 @@
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#!/bin/sh
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if [ -z "$part" -o -z "$image" ]; then
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echo "define \$part and \$image"
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exit 1
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fi
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if [ \! -e "$part" ]; then
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echo "Partition $part does not exist"
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exit 1
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fi
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if [ $# = 1 ]; then
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image=$1
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fi
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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ping $eth0.serverip
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if [ $? -ne 0 ] ; then
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echo "update aborted"
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exit 1
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fi
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unprotect $part
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echo
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echo "erasing partition $part"
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erase $part
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echo
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echo "flashing $image to $part"
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echo
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tftp $image $part
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@ -0,0 +1,38 @@
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#!/bin/sh
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. /env/config
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if [ x$1 = xflash ]; then
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root=flash
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kernel=flash
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fi
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if [ x$1 = xnet ]; then
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root=net
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kernel=net
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fi
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if [ x$ip = xdhcp ]; then
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bootargs="$bootargs ip=dhcp"
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else
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bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
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fi
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if [ x$root = xflash ]; then
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bootargs="$bootargs root=$rootpart rootfstype=jffs2"
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else
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bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp"
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fi
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bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts"
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if [ $kernel = net ]; then
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if [ x$ip = xdhcp ]; then
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dhcp
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fi
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tftp $uimage uImage
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bootm uImage
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else
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bootm /dev/nor0.kernel
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fi
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@ -0,0 +1,20 @@
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#!/bin/sh
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PATH=/env/bin
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export PATH
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. /env/config
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addpart /dev/nor0 $mtdparts
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echo
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echo -n "Hit any key to stop autoboot: "
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timeout -a $autoboot_timeout
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if [ $? != 0 ]; then
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echo
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echo "type update_kernel [<imagename>] to update kernel into flash"
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echo "type udate_root [<imagename>] to update rootfs into flash"
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echo
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exit
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fi
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boot
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@ -0,0 +1,8 @@
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#!/bin/sh
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. /env/config
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image=$uimage
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part=/dev/nor0.kernel
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. /env/bin/_update $1
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@ -0,0 +1,8 @@
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#!/bin/sh
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. /env/config
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image=$jffs2
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part=/dev/nor0.root
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. /env/bin/_update $1
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@ -0,0 +1,26 @@
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#!/bin/sh
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# can be either 'net' or 'flash'
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kernel=net
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root=net
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# use 'dhcp' todo dhcp in uboot and in kernel
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ip=dhcp
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eth0.ipaddr=192.168.23.164
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eth0.netmask=255.255.255.0
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eth0.gateway=192.168.23.2
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eth0.serverip=192.168.23.2
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eth0.ethaddr=00:50:c2:72:a7:4a
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uimage=uImage-pcm038
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jffs2=root-pcm038.jffs2
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autoboot_timeout=3
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nfsroot="/tmp/imx27ads"
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bootargs="console=ttymxc0,115200"
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mtdparts="128k(uboot)ro,128k(ubootenv),1536k(kernel),-(root)"
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rootpart="/dev/mtdblock3"
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@ -0,0 +1,135 @@
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/*
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* Copyright (C) 2007 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <net.h>
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#include <cfi_flash.h>
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#include <init.h>
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#include <environment.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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#include <fec.h>
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#include <asm/arch/gpio.h>
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#include <partition.h>
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#include <fs.h>
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#include <fcntl.h>
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static struct device_d cfi_dev = {
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.name = "cfi_flash",
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.id = "nor0",
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.map_base = 0xC0000000,
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.size = 32 * 1024 * 1024,
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};
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static struct device_d sdram_dev = {
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.name = "ram",
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.id = "ram0",
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.map_base = 0xa0000000,
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.size = 128 * 1024 * 1024,
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.type = DEVICE_TYPE_DRAM,
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};
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static struct fec_platform_data fec_info = {
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.xcv_type = MII100,
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};
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static struct device_d fec_dev = {
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.name = "fec_imx27",
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.id = "eth0",
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.map_base = 0x1002b000,
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.platform_data = &fec_info,
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.type = DEVICE_TYPE_ETHER,
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};
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static void fec_cpld_init(void)
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{
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/* Select FEC data through data path */
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writew(0x0020, IMX_CS4_BASE + 0x10);
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/* Enable CPLD FEC data path */
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writew(0x0010, IMX_CS4_BASE + 0x14);
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}
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static int pcm038_devices_init(void)
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{
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int i;
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unsigned int mode[] = {
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC | GPIO_PUEN,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_CLR,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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};
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/* initizalize gpios */
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for (i = 0; i < ARRAY_SIZE(mode); i++)
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imx_gpio_mode(mode[i]);
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fec_cpld_init();
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register_device(&cfi_dev);
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register_device(&sdram_dev);
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register_device(&fec_dev);
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dev_add_partition(&cfi_dev, 0x00000, 0x20000, PARTITION_FIXED, "self");
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dev_add_partition(&cfi_dev, 0x20000, 0x20000, PARTITION_FIXED, "env");
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dev_protect(&cfi_dev, 0x20000, 0, 1);
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return 0;
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}
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device_initcall(pcm038_devices_init);
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static struct device_d pcm038_serial_device = {
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.name = "imx_serial",
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.id = "cs0",
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.map_base = IMX_UART1_BASE,
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.size = 4096,
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.type = DEVICE_TYPE_CONSOLE,
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};
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static int pcm038_console_init(void)
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{
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register_device(&pcm038_serial_device);
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return 0;
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}
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console_initcall(pcm038_console_init);
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@ -0,0 +1,5 @@
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/** @page imx27ads Freescale i.MX27ads
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This is the Freescale evaluation board for the i.MX27 Processor
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*/
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@ -0,0 +1,182 @@
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/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#define writel(val, reg) \
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ldr r0, =reg; \
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ldr r1, =val; \
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str r1, [r0];
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#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
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.macro sdram_init_sha
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/*
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* DDR on CSD0
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*/
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writel(0x00000008, 0xD8001010)
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writel(0x55555555, 0x10027828)
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writel(0x55555555, 0x10027830)
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writel(0x55555555, 0x10027834)
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writel(0x00005005, 0x10027838)
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writel(0x15555555, 0x1002783C)
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2100000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xA2200000, 0xD8001000)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0x00000000, 0xA0000F00)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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.endm
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.macro sdram_init_mx27_manual
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/*
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* sdram init sequence, as defined in 18.5.4 of the i.MX27 reference manual
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*/
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1:
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ldr r2, =ESD_ESDCTL0 /* base address of registers */
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ldr r3, =PRE_ALL_CMD /* SMODE=001 */
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str r3,(r2,#0x0) /* put CSD0 in precharge command mode */
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ldr r4, =SDRAM_CSD0 /* CSD0 precharge address (A10=1) */
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str r1,(r4,#0x0) /* precharge CSD0 all banks */
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ldr r3, =AUTO_REF_CMD /* SMODE=010 */
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str r3,(r2,#0x0) /* put array 0 in auto-refresh mode */
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ldr r4, =SDRAM_CSD0_BASE /* CSD0 base address */
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ldr r6,=0x7 /* load loop counter */
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1: ldr r5,(r4,#0x0) /* run auto-refresh cycle to array 0 */
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subs r6,r6,#1 /* decrease counter value */
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bne 1b
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ldr r3, =SET_MODE_REG_CMD /* SMODE=011 */
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str r3,(r2,#0x0) /* setup CSD0 for mode register write */
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ldr r3, =MODE_REG_VAL0 /* array 0 mode register value */
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ldrb r5,(r3,#0x0) /* New mode register value on address bus */
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ldr r3, =NORMAL_MODE /* SMODE=000 */
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str r3,(r2,#0x0) /* setup CSD0 for normal operation */
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ESD_ESDCTL0 .long 0xD8001000 // system/external device dependent data
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SDRAM_CSD0 .long 0x00000000 // system/external device dependent data
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SDRAM_CSD0_BASE .long 0x00000000 // system/external device dependent data
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PRE_ALL_CMD .long 0x00000000 // system/external device dependent data (SMODE=001)
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AUTO_REF_CMD .long 0x00000000 // system/external device dependent data (SMODE=010)
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SET_MODE_REG_CMD .long 0x00000000 // system/external device dependent data (SMODE=011)
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MODE_REG_VAL0 .long 0x00000000 // system/external device dependent data
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NORMAL_MODE .long 0x00000000 // system/external device dependent data (SMODE=000)
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.endm
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.macro sdram_init_uboot
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/* configure 16 bit nor flash on cs0 */
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writel(0x0000CC03, 0xd8002000)
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writel(0xa0330D01, 0xd8002004)
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writel(0x00220800, 0xd8002008)
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/* ddr on csd0 - initial reset */
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writel(0x00000008, 0xD8001010)
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/* configure ddr on csd0 - wait 5000 cycles */
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writel(0x00000004, 0xD8001010)
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writel(0x006ac73a, 0xD8001004)
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writel(0x92100000, 0xD8001000)
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writel(0x12344321, 0xA0000f00)
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writel(0xa2100000, 0xD8001000)
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writel(0x12344321, 0xA0000000)
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writel(0x12344321, 0xA0000000)
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writel(0xb2100000, 0xD8001000)
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ldr r0, =0xA0000033
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mov r1, #0xda
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strb r1, [r0]
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ldr r0, =0xA1000000
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mov r1, #0xff
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strb r1, [r0]
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writel(0x82226080, 0xD8001000)
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writel(0xDEADBEEF, 0xA0000000)
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writel(0x0000000c, 0xD8001010)
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.endm
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.globl board_init_lowlevel
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board_init_lowlevel:
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mov r10, lr
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/* ahb lite ip interface */
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writel(0x20040304, AIPI1_PSR0)
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writel(0xDFFBFCFB, AIPI1_PSR1)
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writel(0x00000000, AIPI2_PSR0)
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writel(0xFFFFFFFF, AIPI2_PSR1)
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/* disable mpll/spll */
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ldr r0, =CSCR
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ldr r1, [r0]
|
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bic r1, r1, #0x03
|
||||
str r1, [r0]
|
||||
|
||||
/*
|
||||
* pll clock initialization - see section 3.4.3 of the i.MX27 manual
|
||||
*
|
||||
* FIXME: Using the 399*2 MHz values from table 3-8 doens't work
|
||||
* with 1.2 V core voltage! Find out if this is
|
||||
* documented somewhere.
|
||||
*/
|
||||
writel(0x00191403, MPCTL0) /* MPLL = 199.5*2 MHz */
|
||||
writel(0x040C2403, SPCTL0) /* SPLL = FIXME (needs review) */
|
||||
|
||||
/*
|
||||
* ARM clock = (399 MHz / 2) / (ARM divider = 1) = 200 MHz
|
||||
* AHB clock = (399 MHz / 3) / (AHB divider = 2) = 66.5 MHz
|
||||
* System clock (HCLK) = 133 MHz
|
||||
*/
|
||||
writel(0x33F30307 | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR)
|
||||
|
||||
/* add some delay here */
|
||||
mov r1, #0x1000
|
||||
1: subs r1, r1, #0x1
|
||||
bne 1b
|
||||
|
||||
/* clock gating enable */
|
||||
writel(0x00050f08, GPCR)
|
||||
|
||||
/* peripheral clock divider */
|
||||
writel(0x23C8F403, PCDR0) /* FIXME */
|
||||
writel(0x09030913, PCDR1) /* PERDIV1=08 @133 MHz */
|
||||
/* PERDIV1=04 @266 MHz */
|
||||
|
||||
/* configure 16 bit nor flash on cs0 */
|
||||
writel(0x0000CC03, CS0U)
|
||||
writel(0xa0330D01, CS0L)
|
||||
writel(0x00220800, CS0A)
|
||||
|
||||
/* configure cpld on cs4 */
|
||||
writel(0x0000DCF6, CS4U)
|
||||
writel(0x444A4541, CS4L)
|
||||
writel(0x44443302, CS4A)
|
||||
|
||||
/* skip sdram initialization if we run from ram */
|
||||
cmp pc, #0xa0000000
|
||||
bls 1f
|
||||
cmp pc, #0xc0000000
|
||||
bhi 1f
|
||||
|
||||
mov pc,r10
|
||||
1:
|
||||
sdram_init_sha
|
||||
|
||||
mov pc,r10
|
||||
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/**
|
||||
* @file
|
||||
* @brief Global defintions for the ARM i.MX27 based pcm038
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* FIXME: ugly....should be simply part of the BSP file */
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#define CONFIG_ARCH_NUMBER MACH_TYPE_MX27ADS
|
||||
#define CONFIG_BOOT_PARAMS 0xa0000100
|
||||
#define CFG_MALLOC_LEN (4096 << 10)
|
||||
#define CONFIG_STACKSIZE ( 120 << 10) /* stack size */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue