CLK: clk-mux: Respect CLK_MUX_HIWORD_MASK flag
It is required for Rockchip SoCs where clock settings registers have write-enable mask in high word. Signed-off-by: Andrey Panov <rockford@yandex.ru> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -45,6 +45,9 @@ static int clk_mux_set_parent(struct clk *clk, u8 idx)
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val = readl(m->reg);
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val &= ~(((1 << m->width) - 1) << m->shift);
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val |= idx << m->shift;
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if (clk->flags & CLK_MUX_HIWORD_MASK)
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val |= ((1 << m->width) - 1) << (m->shift + 16);
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writel(val, m->reg);
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return 0;
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@ -248,6 +248,8 @@ struct clk_divider {
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int table_size;
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};
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#define CLK_MUX_HIWORD_MASK (1 << 2)
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extern struct clk_ops clk_divider_ops;
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struct clk *clk_divider(const char *name, const char *parent,
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