mci s3c: allocate host struct dynamically
Yes, it does make sense. First there will always be the next hardware which has multiple controllers. Also, we shouldn't give bad examples to others. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -153,18 +153,13 @@
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#define SDIDATA 0x40
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struct s3c_mci_host {
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struct mci_host host;
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void __iomem *base;
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int bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */
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unsigned clock; /* current clock in Hz */
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unsigned data_size; /* data transfer in bytes */
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};
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/*
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* There is only one host MCI hardware instance available.
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* It makes no sense to dynamically allocate this data
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*/
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static struct s3c_mci_host host_data;
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/**
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* Finish a request
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* @param hw_dev Host interface instance
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@ -743,20 +738,16 @@ static void s3c_info(struct device_d *hw_dev)
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}
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#endif
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/*
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* There is only one host MCI hardware instance available.
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* It makes no sense to dynamically allocate this data
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*/
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static struct mci_host mci_pdata = {
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.send_cmd = mci_request,
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.set_ios = mci_set_ios,
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.init = mci_reset,
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};
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static int s3c_mci_probe(struct device_d *hw_dev)
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{
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struct s3c_mci_host *s3c_host;
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struct s3c_mci_platform_data *pd = hw_dev->platform_data;
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s3c_host = xzalloc(sizeof(*s3c_host));
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s3c_host->host.send_cmd = mci_request;
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s3c_host->host.set_ios = mci_set_ios;
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s3c_host->host.init = mci_reset;
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/* TODO replace by the global func: enable the SDI unit clock */
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writel(readl(S3C_CLOCK_POWER_BASE + 0x0c) | 0x200,
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S3C_CLOCK_POWER_BASE + 0x0c);
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@ -766,23 +757,23 @@ static int s3c_mci_probe(struct device_d *hw_dev)
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return -EINVAL;
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}
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hw_dev->priv = &host_data;
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host_data.base = dev_request_mem_region(hw_dev, 0);
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mci_pdata.hw_dev = hw_dev;
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hw_dev->priv = s3c_host;
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s3c_host->base = dev_request_mem_region(hw_dev, 0);
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s3c_host->host.hw_dev = hw_dev;
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/* feed forward the platform specific values */
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mci_pdata.voltages = pd->voltages;
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mci_pdata.host_caps = pd->caps;
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mci_pdata.f_min = pd->f_min == 0 ? s3c_get_pclk() / 256 : pd->f_min;
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mci_pdata.f_max = pd->f_max == 0 ? s3c_get_pclk() / 2 : pd->f_max;
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s3c_host->host.voltages = pd->voltages;
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s3c_host->host.host_caps = pd->caps;
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s3c_host->host.f_min = pd->f_min == 0 ? s3c_get_pclk() / 256 : pd->f_min;
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s3c_host->host.f_max = pd->f_max == 0 ? s3c_get_pclk() / 2 : pd->f_max;
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/*
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* Start the clock to let the engine and the card finishes its startup
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*/
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host_data.clock = s3c_setup_clock_speed(hw_dev, mci_pdata.f_min);
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writel(SDICON_FIFORESET | SDICON_MMCCLOCK, host_data.base + SDICON);
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s3c_host->clock = s3c_setup_clock_speed(hw_dev, pd->f_min);
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writel(SDICON_FIFORESET | SDICON_MMCCLOCK, s3c_host->base + SDICON);
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return mci_register(&mci_pdata);
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return mci_register(&s3c_host->host);
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}
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static struct driver_d s3c_mci_driver = {
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