net: add ar231x-eth support
This driver should work with some Atheros WiSoCs: - ar2312, ar2313 - ar2315, ar2316 ... Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Oleksij Rempel
Sascha Hauer
parent
59fe549733
commit
7d27f0db93
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@ -27,6 +27,13 @@ menu "Network drivers"
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source "drivers/net/phy/Kconfig"
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config DRIVER_NET_AR231X
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bool "AR231X Ethernet support"
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depends on MACH_MIPS_AR231X
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select PHYLIB
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help
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Support for the AR231x/531x ethernet controller
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config DRIVER_NET_CALXEDA_XGMAC
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bool "Calxeda xgmac"
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@ -1,3 +1,4 @@
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obj-$(CONFIG_DRIVER_NET_AR231X) += ar231x.o
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obj-$(CONFIG_DRIVER_NET_CALXEDA_XGMAC) += xgmac.o
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obj-$(CONFIG_DRIVER_NET_CS8900) += cs8900.o
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obj-$(CONFIG_DRIVER_NET_CPSW) += cpsw.o
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@ -0,0 +1,437 @@
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/*
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* ar231x.c: driver for the Atheros AR231x Ethernet device.
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* This device is build in to SoC on ar231x series.
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* All known of them are big endian.
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*
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* Based on Linux driver:
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* Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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* Ported to Barebox:
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* Copyright (C) 2013 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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/*
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* Known issues:
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* - broadcast packets are not filtered by hardware. On noisy network with
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* lots of bcast packages rx_buffer can be completely filled after. Currently
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* we clear rx_buffer transmit some package.
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*/
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#include <common.h>
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#include <net.h>
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#include <init.h>
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#include <io.h>
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#include "ar231x.h"
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static inline void dma_writel(struct ar231x_eth_priv *priv,
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u32 val, int reg)
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{
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__raw_writel(val, priv->dma_regs + reg);
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}
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static inline u32 dma_readl(struct ar231x_eth_priv *priv, int reg)
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{
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return __raw_readl(priv->dma_regs + reg);
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}
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static inline void eth_writel(struct ar231x_eth_priv *priv,
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u32 val, int reg)
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{
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__raw_writel(val, priv->eth_regs + reg);
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}
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static inline u32 eth_readl(struct ar231x_eth_priv *priv, int reg)
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{
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return __raw_readl(priv->eth_regs + reg);
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}
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static inline void phy_writel(struct ar231x_eth_priv *priv,
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u32 val, int reg)
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{
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__raw_writel(val, priv->phy_regs + reg);
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}
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static inline u32 phy_readl(struct ar231x_eth_priv *priv, int reg)
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{
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return __raw_readl(priv->phy_regs + reg);
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}
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static void ar231x_reset_bit_(struct ar231x_eth_priv *priv,
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u32 val, enum reset_state state)
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{
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if (priv->reset_bit)
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(*priv->reset_bit)(val, state);
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}
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static int ar231x_set_ethaddr(struct eth_device *edev, unsigned char *addr);
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static void ar231x_reset_regs(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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struct ar231x_eth_platform_data *cfg = priv->cfg;
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u32 flags;
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ar231x_reset_bit_(priv, cfg->reset_mac, SET);
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mdelay(10);
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ar231x_reset_bit_(priv, cfg->reset_mac, REMOVE);
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mdelay(10);
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ar231x_reset_bit_(priv, cfg->reset_phy, SET);
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mdelay(10);
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ar231x_reset_bit_(priv, cfg->reset_phy, REMOVE);
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mdelay(10);
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dma_writel(priv, DMA_BUS_MODE_SWR, AR231X_DMA_BUS_MODE);
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mdelay(10);
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dma_writel(priv, ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE),
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AR231X_DMA_BUS_MODE);
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/* FIXME: priv->{t,r}x_ring are virtual addresses,
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* use virt-to-phys convertion */
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dma_writel(priv, (u32)priv->tx_ring, AR231X_DMA_TX_RING);
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dma_writel(priv, (u32)priv->rx_ring, AR231X_DMA_RX_RING);
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dma_writel(priv, (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF),
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AR231X_DMA_CONTROL);
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eth_writel(priv, FLOW_CONTROL_FCE, AR231X_ETH_FLOW_CONTROL);
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/* TODO: not sure if we need it here. */
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eth_writel(priv, 0x8100, AR231X_ETH_VLAN_TAG);
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/* Enable Ethernet Interface */
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flags = (MAC_CONTROL_TE | /* transmit enable */
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/* FIXME: MAC_CONTROL_PM - pass mcast.
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* Seems like it makes no difference on some WiSoCs,
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* for example ar2313.
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* It should be tested on ar231[5,6,7] */
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MAC_CONTROL_PM |
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MAC_CONTROL_F | /* full duplex */
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MAC_CONTROL_HBD); /* heart beat disabled */
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eth_writel(priv, flags, AR231X_ETH_MAC_CONTROL);
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}
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static void ar231x_flash_rxdsc(struct ar231x_descr *rxdsc)
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{
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rxdsc->status = DMA_RX_OWN;
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rxdsc->devcs = ((AR2313_RX_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
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DMA_RX1_CHAINED);
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}
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static void ar231x_allocate_dma_descriptors(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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u16 ar231x_descr_size = sizeof(struct ar231x_descr);
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u16 i;
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priv->tx_ring = xmalloc(ar231x_descr_size);
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dev_dbg(&edev->dev, "allocate tx_ring @ %p\n", priv->tx_ring);
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priv->rx_ring = xmalloc(ar231x_descr_size * AR2313_RXDSC_ENTRIES);
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dev_dbg(&edev->dev, "allocate rx_ring @ %p\n", priv->rx_ring);
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priv->rx_buffer = xmalloc(AR2313_RX_BUFSIZE * AR2313_RXDSC_ENTRIES);
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dev_dbg(&edev->dev, "allocate rx_buffer @ %p\n", priv->rx_buffer);
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/* Initialize the rx Descriptors */
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for (i = 0; i < AR2313_RXDSC_ENTRIES; i++) {
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struct ar231x_descr *rxdsc = &priv->rx_ring[i];
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ar231x_flash_rxdsc(rxdsc);
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rxdsc->buffer_ptr =
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(u32)(priv->rx_buffer + AR2313_RX_BUFSIZE * i);
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rxdsc->next_dsc_ptr = (u32)&priv->rx_ring[DSC_NEXT(i)];
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}
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/* set initial position of ring descriptor */
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priv->next_rxdsc = &priv->rx_ring[0];
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}
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static void ar231x_adjust_link(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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u32 mc;
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if (edev->phydev->duplex != priv->oldduplex) {
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mc = eth_readl(priv, AR231X_ETH_MAC_CONTROL);
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mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
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if (edev->phydev->duplex)
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mc |= MAC_CONTROL_F;
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else
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mc |= MAC_CONTROL_DRO;
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eth_writel(priv, mc, AR231X_ETH_MAC_CONTROL);
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priv->oldduplex = edev->phydev->duplex;
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}
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}
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static int ar231x_eth_init(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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ar231x_allocate_dma_descriptors(edev);
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ar231x_reset_regs(edev);
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ar231x_set_ethaddr(edev, priv->mac);
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return 0;
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}
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static int ar231x_eth_open(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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u32 tmp;
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/* Enable RX. Now the rx_buffer will be filled.
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* If it is full we may lose first transmission. In this case
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* barebox should retry it.
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* Or TODO: - force HW to filter some how broadcasts
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* - disable RX if we do not need it. */
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tmp = eth_readl(priv, AR231X_ETH_MAC_CONTROL);
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eth_writel(priv, (tmp | MAC_CONTROL_RE), AR231X_ETH_MAC_CONTROL);
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return phy_device_connect(edev, &priv->miibus, (int)priv->phy_regs,
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ar231x_adjust_link, 0, PHY_INTERFACE_MODE_MII);
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}
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static int ar231x_eth_recv(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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while (1) {
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struct ar231x_descr *rxdsc = priv->next_rxdsc;
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u32 status = rxdsc->status;
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/* owned by DMA? */
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if (status & DMA_RX_OWN)
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break;
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/* Pick only packets what we can handle:
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* - only complete packet per buffer
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* (First and Last at same time)
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* - drop multicast */
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if (!priv->kill_rx_ring &&
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((status & DMA_RX_MASK) == DMA_RX_FSLS)) {
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u16 length =
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((status >> DMA_RX_LEN_SHIFT) & 0x3fff)
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- CRC_LEN;
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net_receive((void *)rxdsc->buffer_ptr, length);
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}
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/* Clean descriptor. now it is owned by DMA. */
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priv->next_rxdsc = (struct ar231x_descr *)rxdsc->next_dsc_ptr;
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ar231x_flash_rxdsc(rxdsc);
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}
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priv->kill_rx_ring = 0;
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return 0;
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}
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static int ar231x_eth_send(struct eth_device *edev, void *packet,
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int length)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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struct ar231x_descr *txdsc = priv->tx_ring;
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u32 rx_missed;
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/* We do not do async work.
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* If rx_ring is full, there is nothing we can use. */
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rx_missed = dma_readl(priv, AR231X_DMA_RX_MISSED);
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if (rx_missed) {
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priv->kill_rx_ring = 1;
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ar231x_eth_recv(edev);
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}
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/* Setup the transmit descriptor. */
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txdsc->devcs = ((length << DMA_TX1_BSIZE_SHIFT) | DMA_TX1_DEFAULT);
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txdsc->buffer_ptr = (uint)packet;
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txdsc->status = DMA_TX_OWN;
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/* Trigger transmission */
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dma_writel(priv, 0, AR231X_DMA_TX_POLL);
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/* Take enough time to transmit packet. 100 is not enough. */
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wait_on_timeout(2000 * MSECOND,
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!(txdsc->status & DMA_TX_OWN));
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/* We can't do match here. If it is still in progress,
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* then engine is probably stalled or we wait not enough. */
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if (txdsc->status & DMA_TX_OWN)
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dev_err(&edev->dev, "Frame is still in progress.\n");
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if (txdsc->status & DMA_TX_ERROR)
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dev_err(&edev->dev, "Frame was aborted by engine\n");
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/* Ready or not. Stop it. */
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txdsc->status = 0;
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return 0;
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}
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static void ar231x_eth_halt(struct eth_device *edev)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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u32 tmp;
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/* kill the MAC: disable RX and TX */
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tmp = eth_readl(priv, AR231X_ETH_MAC_CONTROL);
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eth_writel(priv, tmp & ~(MAC_CONTROL_RE | MAC_CONTROL_TE),
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AR231X_ETH_MAC_CONTROL);
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/* stop DMA */
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dma_writel(priv, 0, AR231X_DMA_CONTROL);
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dma_writel(priv, DMA_BUS_MODE_SWR, AR231X_DMA_BUS_MODE);
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/* place PHY and MAC in reset */
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ar231x_reset_bit_(priv, (priv->cfg->reset_mac | priv->cfg->reset_phy), SET);
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}
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static int ar231x_get_ethaddr(struct eth_device *edev, unsigned char *addr)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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/* MAC address is stored on flash, in some kind of atheros config
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* area. Platform code should read it and pass to the driver. */
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memcpy(addr, priv->mac, 6);
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return 0;
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}
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/**
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* These device do not have build in MAC address.
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* It is located on atheros-config field on flash.
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*/
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static int ar231x_set_ethaddr(struct eth_device *edev, unsigned char *addr)
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{
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struct ar231x_eth_priv *priv = edev->priv;
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eth_writel(priv,
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(addr[5] << 8) | (addr[4]),
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AR231X_ETH_MAC_ADDR1);
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eth_writel(priv,
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(addr[3] << 24) | (addr[2] << 16) |
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(addr[1] << 8) | addr[0],
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AR231X_ETH_MAC_ADDR2);
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mdelay(10);
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return 0;
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}
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#define MII_ADDR(phy, reg) \
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((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
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static int ar231x_miibus_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct ar231x_eth_priv *priv = bus->priv;
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uint64_t time_start;
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phy_writel(priv, MII_ADDR(phy_id, regnum), AR231X_ETH_MII_ADDR);
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time_start = get_time_ns();
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while (phy_readl(priv, AR231X_ETH_MII_ADDR) & MII_ADDR_BUSY) {
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if (is_timeout(time_start, SECOND)) {
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dev_err(&bus->dev, "miibus read timeout\n");
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return -ETIMEDOUT;
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}
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}
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return phy_readl(priv, AR231X_ETH_MII_DATA) >> MII_DATA_SHIFT;
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}
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static int ar231x_miibus_write(struct mii_bus *bus, int phy_id,
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int regnum, u16 val)
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{
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struct ar231x_eth_priv *priv = bus->priv;
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uint64_t time_start = get_time_ns();
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while (phy_readl(priv, AR231X_ETH_MII_ADDR) & MII_ADDR_BUSY) {
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if (is_timeout(time_start, SECOND)) {
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dev_err(&bus->dev, "miibus write timeout\n");
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return -ETIMEDOUT;
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}
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}
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phy_writel(priv, val << MII_DATA_SHIFT, AR231X_ETH_MII_DATA);
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phy_writel(priv, MII_ADDR(phy_id, regnum) | MII_ADDR_WRITE,
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AR231X_ETH_MII_ADDR);
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return 0;
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}
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static int ar231x_mdiibus_reset(struct mii_bus *bus)
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{
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struct ar231x_eth_priv *priv = bus->priv;
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ar231x_reset_regs(&priv->edev);
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return 0;
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}
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static int ar231x_eth_probe(struct device_d *dev)
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{
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struct ar231x_eth_priv *priv;
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struct eth_device *edev;
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struct mii_bus *miibus;
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struct ar231x_eth_platform_data *pdata;
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if (!dev->platform_data) {
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dev_err(dev, "no platform data\n");
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return -ENODEV;
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}
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pdata = dev->platform_data;
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priv = xzalloc(sizeof(struct ar231x_eth_priv));
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edev = &priv->edev;
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miibus = &priv->miibus;
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edev->priv = priv;
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/* link all platform depended regs */
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priv->mac = pdata->mac;
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priv->reset_bit = pdata->reset_bit;
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priv->eth_regs = dev_request_mem_region(dev, 0);
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if (priv->eth_regs == NULL) {
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dev_err(dev, "No eth_regs!!\n");
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return -ENODEV;
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}
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/* we have 0x100000 for eth, part of it are dma regs.
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* So they are already requested */
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priv->dma_regs = (void *)(priv->eth_regs + 0x1000);
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priv->phy_regs = dev_request_mem_region(dev, 1);
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if (priv->phy_regs == NULL) {
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dev_err(dev, "No phy_regs!!\n");
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return -ENODEV;
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}
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priv->cfg = pdata;
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edev->init = ar231x_eth_init;
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edev->open = ar231x_eth_open;
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edev->send = ar231x_eth_send;
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edev->recv = ar231x_eth_recv;
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edev->halt = ar231x_eth_halt;
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edev->get_ethaddr = ar231x_get_ethaddr;
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edev->set_ethaddr = ar231x_set_ethaddr;
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priv->miibus.read = ar231x_miibus_read;
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priv->miibus.write = ar231x_miibus_write;
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priv->miibus.reset = ar231x_mdiibus_reset;
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priv->miibus.priv = priv;
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priv->miibus.parent = dev;
|
||||
|
||||
mdiobus_register(miibus);
|
||||
eth_register(edev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ar231x_eth_remove(struct device_d *dev)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static struct driver_d ar231x_eth_driver = {
|
||||
.name = "ar231x_eth",
|
||||
.probe = ar231x_eth_probe,
|
||||
.remove = ar231x_eth_remove,
|
||||
};
|
||||
|
||||
static int ar231x_eth_driver_init(void)
|
||||
{
|
||||
return platform_driver_register(&ar231x_eth_driver);
|
||||
}
|
||||
device_initcall(ar231x_eth_driver_init);
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
|
||||
* Based on Linux driver:
|
||||
* Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
|
||||
* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
||||
* Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
|
||||
* Ported to Barebox:
|
||||
* Copyright (C) 2013 Oleksij Rempel <linux@rempel-privat.de>
|
||||
*
|
||||
* Thanks to Atheros for providing hardware and documentation
|
||||
* enabling me to write this driver.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef _AR2313_2_H_
|
||||
#define _AR2313_2_H_
|
||||
|
||||
#include <net.h>
|
||||
#include <mach/ar231x_platform.h>
|
||||
|
||||
/* Allocate 64 RX buffers. This will reduce packet loss, until we will start
|
||||
* processing them. It is important in noisy network with lots of broadcasts. */
|
||||
#define AR2313_RXDSC_ENTRIES 64
|
||||
#define DSC_NEXT(idx) (((idx) + 1) & (AR2313_RXDSC_ENTRIES - 1))
|
||||
|
||||
/* Use system default buffers size. At the moment of writing it was 1518 */
|
||||
#define AR2313_RX_BUFSIZE PKTSIZE
|
||||
#define CRC_LEN 4
|
||||
|
||||
/**
|
||||
* DMA controller
|
||||
*/
|
||||
#define AR231X_DMA_BUS_MODE 0x00 /* (CSR0) */
|
||||
#define AR231X_DMA_TX_POLL 0x04 /* (CSR1) */
|
||||
#define AR231X_DMA_RX_POLL 0x08 /* (CSR2) */
|
||||
#define AR231X_DMA_RX_RING 0x0c /* (CSR3) */
|
||||
#define AR231X_DMA_TX_RING 0x10 /* (CSR4) */
|
||||
#define AR231X_DMA_STATUS 0x14 /* (CSR5) */
|
||||
#define AR231X_DMA_CONTROL 0x18 /* (CSR6) */
|
||||
#define AR231X_DMA_INTR_ENA 0x1c /* (CSR7) */
|
||||
#define AR231X_DMA_RX_MISSED 0x20 /* (CSR8) */
|
||||
/* reserverd 0x24-0x4c (CSR9-19) */
|
||||
#define AR231X_DMA_CUR_TX_BUF_ADDR 0x50 /* (CSR20) */
|
||||
#define AR231X_DMA_CUR_RX_BUF_ADDR 0x54 /* (CSR21) */
|
||||
|
||||
/**
|
||||
* Ethernet controller
|
||||
*/
|
||||
#define AR231X_ETH_MAC_CONTROL 0x00
|
||||
#define AR231X_ETH_MAC_ADDR1 0x04
|
||||
#define AR231X_ETH_MAC_ADDR2 0x08
|
||||
#define AR231X_ETH_MCAST_TABLE1 0x0c
|
||||
#define AR231X_ETH_MCAST_TABLE2 0x10
|
||||
#define AR231X_ETH_MII_ADDR 0x14
|
||||
#define AR231X_ETH_MII_DATA 0x18
|
||||
#define AR231X_ETH_FLOW_CONTROL 0x1c
|
||||
#define AR231X_ETH_VLAN_TAG 0x20
|
||||
/* pad 0x24 - 0x3c */
|
||||
/* ucast_table 0x40-0x5c */
|
||||
|
||||
/**
|
||||
* RX descriptor status bits. ar231x_descr.status
|
||||
*/
|
||||
#define DMA_RX_ERR_CRC BIT(1)
|
||||
#define DMA_RX_ERR_DRIB BIT(2)
|
||||
#define DMA_RX_ERR_MII BIT(3)
|
||||
#define DMA_RX_EV2 BIT(5)
|
||||
#define DMA_RX_ERR_COL BIT(6)
|
||||
#define DMA_RX_LONG BIT(7)
|
||||
#define DMA_RX_LS BIT(8) /* last descriptor */
|
||||
#define DMA_RX_FS BIT(9) /* first descriptor */
|
||||
#define DMA_RX_MF BIT(10) /* multicast frame */
|
||||
#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
|
||||
#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
|
||||
#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
|
||||
#define DMA_RX_ERROR BIT(15) /* error summary */
|
||||
#define DMA_RX_LEN_MASK 0x3fff0000
|
||||
#define DMA_RX_LEN_SHIFT 16
|
||||
#define DMA_RX_FILT BIT(30)
|
||||
#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
|
||||
#define DMA_RX_FSLS (DMA_RX_LS | DMA_RX_FS)
|
||||
#define DMA_RX_MASK (DMA_RX_FSLS | DMA_RX_MF | DMA_RX_ERROR)
|
||||
|
||||
/**
|
||||
* RX descriptor configuration bits. ar231x_descr.devcs
|
||||
*/
|
||||
#define DMA_RX1_BSIZE_MASK 0x000007ff
|
||||
#define DMA_RX1_BSIZE_SHIFT 0
|
||||
#define DMA_RX1_CHAINED BIT(24)
|
||||
#define DMA_RX1_RER BIT(25)
|
||||
|
||||
/**
|
||||
* TX descriptor status fields. ar231x_descr.status
|
||||
*/
|
||||
#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
|
||||
#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
|
||||
#define DMA_TX_COL_MASK 0x78
|
||||
#define DMA_TX_COL_SHIFT 3
|
||||
#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
|
||||
#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
|
||||
#define DMA_TX_ERR_LATE BIT(9) /* late collision */
|
||||
#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
|
||||
#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
|
||||
#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
|
||||
#define DMA_TX_ERROR BIT(15) /* frame aborted */
|
||||
#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
|
||||
|
||||
/**
|
||||
* TX descriptor configuration bits. ar231x_descr.devcs
|
||||
*/
|
||||
#define DMA_TX1_BSIZE_MASK 0x000007ff
|
||||
#define DMA_TX1_BSIZE_SHIFT 0
|
||||
#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
|
||||
#define DMA_TX1_TER BIT(25) /* transmit end of ring */
|
||||
#define DMA_TX1_FS BIT(29) /* first segment */
|
||||
#define DMA_TX1_LS BIT(30) /* last segment */
|
||||
#define DMA_TX1_IC BIT(31) /* interrupt on completion */
|
||||
#define DMA_TX1_DEFAULT (DMA_TX1_FS | DMA_TX1_LS | DMA_TX1_TER)
|
||||
|
||||
#define MAC_CONTROL_RE BIT(2) /* receive enable */
|
||||
#define MAC_CONTROL_TE BIT(3) /* transmit enable */
|
||||
#define MAC_CONTROL_DC BIT(5) /* Deferral check */
|
||||
#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
|
||||
#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
|
||||
#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
|
||||
#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
|
||||
#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
|
||||
#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
|
||||
#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
|
||||
#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
|
||||
#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
|
||||
#define MAC_CONTROL_PR BIT(18) /* promiscuous mode
|
||||
* (valid frames only) */
|
||||
#define MAC_CONTROL_PM BIT(19) /* pass multicast */
|
||||
#define MAC_CONTROL_F BIT(20) /* full-duplex */
|
||||
#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
|
||||
#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
|
||||
#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
|
||||
#define MAC_CONTROL_RA BIT(31) /* receive all
|
||||
* (valid and invalid frames) */
|
||||
|
||||
#define MII_ADDR_BUSY BIT(0)
|
||||
#define MII_ADDR_WRITE BIT(1)
|
||||
#define MII_ADDR_REG_SHIFT 6
|
||||
#define MII_ADDR_PHY_SHIFT 11
|
||||
#define MII_DATA_SHIFT 0
|
||||
|
||||
#define FLOW_CONTROL_FCE BIT(1)
|
||||
|
||||
#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
|
||||
#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
|
||||
#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
|
||||
#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
|
||||
|
||||
#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
|
||||
#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
|
||||
#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
|
||||
#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
|
||||
#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
|
||||
#define DMA_STATUS_RI BIT(6) /* receive interrupt */
|
||||
#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
|
||||
#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
|
||||
#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
|
||||
#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
|
||||
#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
|
||||
#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
|
||||
#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
|
||||
#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
|
||||
#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
|
||||
#define DMA_STATUS_EB_SHIFT 23 /* error bits */
|
||||
|
||||
#define DMA_CONTROL_SR BIT(1) /* start receive */
|
||||
#define DMA_CONTROL_ST BIT(13) /* start transmit */
|
||||
#define DMA_CONTROL_SF BIT(21) /* store and forward */
|
||||
|
||||
|
||||
struct ar231x_descr {
|
||||
u32 status; /* OWN, Device control and status. */
|
||||
u32 devcs; /* Packet control bitmap + Length. */
|
||||
u32 buffer_ptr; /* Pointer to packet buffer. */
|
||||
u32 next_dsc_ptr; /* Pointer to next descriptor in chain. */
|
||||
};
|
||||
|
||||
/**
|
||||
* Struct private for the Sibyte.
|
||||
*
|
||||
* Elements are grouped so variables used by the tx handling goes
|
||||
* together, and will go into the same cache lines etc. in order to
|
||||
* avoid cache line contention between the rx and tx handling on SMP.
|
||||
*
|
||||
* Frequently accessed variables are put at the beginning of the
|
||||
* struct to help the compiler generate better/shorter code.
|
||||
*/
|
||||
struct ar231x_eth_priv {
|
||||
struct ar231x_eth_platform_data *cfg;
|
||||
u8 *mac;
|
||||
void __iomem *phy_regs;
|
||||
void __iomem *eth_regs;
|
||||
void __iomem *dma_regs;
|
||||
void __iomem *reset_regs;
|
||||
|
||||
struct eth_device edev;
|
||||
struct mii_bus miibus;
|
||||
|
||||
struct ar231x_descr *tx_ring;
|
||||
struct ar231x_descr *rx_ring;
|
||||
struct ar231x_descr *next_rxdsc;
|
||||
u8 kill_rx_ring;
|
||||
void *rx_buffer;
|
||||
|
||||
int oldduplex;
|
||||
void (*reset_bit)(u32 val, enum reset_state state);
|
||||
};
|
||||
|
||||
#endif /* _AR2313_H_ */
|
||||
Loading…
Reference in New Issue