video: i.MX IPUv3: Set ldb clocks correctly
The clocks for the LVDS display bridge have a fixed /3.5 and a configurable /1,/2 divider in their path. The configurable divider has to be explicitly configured for single/dual channel support, so we can't rely on clock rate parent propagation here. Clear the CLK_SET_RATE_PARENT flag for the configurable divider and configure the clock explicitly in the ldb driver. Tested on a custom i.MX6 board, currently untested on i.MX53. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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4 changed files with 31 additions and 7 deletions
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@ -332,7 +332,7 @@ static struct driver_d imx51_ccm_driver = {
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static void mx53_clocks_ipu_init(void __iomem *regs)
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{
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clks[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
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clks[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_np("ldb_di1_div", "ldb_di1_div_3_5", regs + CCM_CSCMR2, 11, 1);
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clks[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_p("ldb_di1_sel", regs + CCM_CSCMR2, 9, 1,
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mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel));
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clks[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", regs + CCM_CDCDR, 16, 3);
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@ -300,9 +300,9 @@ static void imx6_add_video_clks(void __iomem *anab, void __iomem *cb)
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clks[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", cb + 0x3c, 11, 3);
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clks[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", cb + 0x3c, 16, 3);
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clks[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
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clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
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clks[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_np("ldb_di0_podf", "ldb_di0_div_3_5", cb + 0x20, 10, 1);
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clks[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
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clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
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clks[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_np("ldb_di1_podf", "ldb_di1_div_3_5", cb + 0x20, 11, 1);
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clks[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", cb + 0x34, 3, 3);
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clks[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", cb + 0x34, 12, 3);
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clks[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", cb + 0x38, 3, 3);
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@ -10,6 +10,12 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
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return clk_divider(name, parent, reg, shift, width, CLK_SET_RATE_PARENT);
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}
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static inline struct clk *imx_clk_divider_np(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 width)
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{
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return clk_divider(name, parent, reg, shift, width, 0);
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}
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static inline struct clk *imx_clk_divider_table(const char *name,
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const char *parent, void __iomem *reg, u8 shift, u8 width,
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const struct clk_div_table *table)
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@ -68,7 +68,7 @@ struct imx_ldb_channel {
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struct imx_ldb_data {
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void __iomem *base;
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int (*prepare)(struct imx_ldb_channel *imx_ldb_ch, int di);
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int (*prepare)(struct imx_ldb_channel *imx_ldb_ch, int di, unsigned long clkrate);
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unsigned ipu_mask;
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int have_mux;
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};
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@ -114,7 +114,7 @@ static int imx_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, struct fb_videomo
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{
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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ldb->soc_data->prepare(imx_ldb_ch, di);
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ldb->soc_data->prepare(imx_ldb_ch, di, PICOS2KHZ(mode->pixclock) * 1000UL);
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/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
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if (imx_ldb_ch == &ldb->channel[0]) {
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@ -146,7 +146,8 @@ static int imx_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, struct fb_videomo
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return 0;
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}
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static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di,
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unsigned long pixclk)
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{
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struct clk *diclk, *ldbclk;
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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@ -155,6 +156,7 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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void __iomem *gpr3 = (void *)MX6_IOMUXC_BASE_ADDR + 0xc;
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uint32_t val;
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int shift;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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ipuno = ((di >> 1) & 1) + 1;
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dino = di & 0x1;
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@ -181,6 +183,11 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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return ret;
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}
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if (!dual)
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pixclk *= 2;
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clk_set_rate(clk_get_parent(ldbclk), pixclk);
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val = readl(gpr3);
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shift = (imx_ldb_ch->chno == 0) ? 6 : 8;
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val &= ~(3 << shift);
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@ -190,12 +197,14 @@ static int imx6q_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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return 0;
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}
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static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di,
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unsigned long pixclk)
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{
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struct clk *diclk, *ldbclk;
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int ret, dino;
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char *clkname;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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dino = di & 0x1;
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@ -221,6 +230,11 @@ static int imx53_ldb_prepare(struct imx_ldb_channel *imx_ldb_ch, int di)
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return ret;
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}
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if (!dual)
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pixclk *= 2;
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clk_set_rate(clk_get_parent(ldbclk), pixclk);
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return 0;
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}
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@ -299,6 +313,10 @@ static int imx_ldb_probe(struct device_d *dev)
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imx_ldb->base = devtype->base;
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imx_ldb->soc_data = devtype;
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dual = of_property_read_bool(np, "fsl,dual-channel");
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if (dual)
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imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
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for_each_child_of_node(np, child) {
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struct imx_ldb_channel *channel;
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struct device_node *port;
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