ARM: i.MX6: Add PCI clocks
Needed for pcie support. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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@ -196,6 +196,26 @@ static const char *ipu2_di1_sels[] = {
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"ldb_di1_podf",
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};
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static const char *lvds_sels[] = {
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"dummy",
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"dummy",
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"dummy",
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"dummy",
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"dummy",
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"dummy",
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"pll4_audio",
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"pll5_video",
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"pll8_mlb",
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"enet_ref",
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"pcie_ref_125m",
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"sata_ref_100m",
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};
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static const char *pcie_axi_sels[] = {
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"axi",
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"ahb",
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};
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static struct clk_div_table clk_enet_ref_table[] = {
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{ .val = 0, .div = 20, },
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{ .val = 1, .div = 10, },
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@ -306,6 +326,12 @@ static int imx6_ccm_probe(struct device_d *dev)
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clks[IMX6QDL_CLK_ENET_REF] = imx_clk_divider_table("enet_ref", "pll6_enet", base + 0xe0, 0, 2, clk_enet_ref_table);
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clks[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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clks[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
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clks[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
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clks[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
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/* name parent_name reg idx */
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clks[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
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clks[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
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@ -341,6 +367,7 @@ static int imx6_ccm_probe(struct device_d *dev)
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clks[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_sels, ARRAY_SIZE(eim_sels));
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clks[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
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clks[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
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clks[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
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/* name reg shift width busy: reg, shift parent_names num_parents */
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clks[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
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@ -433,6 +460,8 @@ static int imx6_ccm_probe(struct device_d *dev)
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clk_enable(clks[IMX6QDL_CLK_SATA_REF_100M]);
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clk_enable(clks[IMX6QDL_CLK_ENFC_PODF]);
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clk_set_parent(clks[IMX6QDL_CLK_LVDS1_SEL], clks[IMX6QDL_CLK_SATA_REF_100M]);
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return 0;
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}
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