ppc: Freescale P1010 headers
Add a minimal Integrated Flash Controller header file and new definitions to support the P1010 SOC. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
7e1e8aac7b
commit
7e2d924723
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@ -0,0 +1,267 @@
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/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_IFC_H
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#define __FSL_IFC_H
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#include <config.h>
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#include <common.h>
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/* Big-Endian */
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#define ifc_in32(a) in_be32(a)
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#define ifc_out32(a, v) out_be32(a, v)
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#define ifc_in16(a) in_be16(a)
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/*
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* CSPR - Chip Select Property Register
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*/
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#define CSPR_BA 0xFFFF0000
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#define CSPR_BA_SHIFT 16
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#define CSPR_PORT_SIZE 0x00000180
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#define CSPR_PORT_SIZE_SHIFT 7
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#define CSPR_PORT_SIZE_8 0x00000080
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#define CSPR_PORT_SIZE_16 0x00000100
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#define CSPR_PORT_SIZE_32 0x00000180
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/* Write Protect */
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#define CSPR_WP 0x00000040
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#define CSPR_WP_SHIFT 6
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#define CSPR_MSEL 0x00000006
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#define CSPR_MSEL_SHIFT 1
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#define CSPR_MSEL_NOR 0x00000000
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#define CSPR_MSEL_NAND 0x00000002
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#define CSPR_MSEL_GPCM 0x00000004
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#define CSPR_V 0x00000001
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#define CSPR_V_SHIFT 0
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/* Convert an address into the right format for the CSPR Registers */
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#define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
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/*
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* Address Mask Register
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*/
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#define IFC_AMASK_MASK 0xFFFF0000
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#define IFC_AMASK_SHIFT 16
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#define IFC_AMASK(n) (IFC_AMASK_MASK << \
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(__ilog2(n) - IFC_AMASK_SHIFT))
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/*
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* Chip Select Option Register IFC_NAND Machine
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*/
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#define CSOR_NAND_ECC_ENC_EN 0x80000000
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#define CSOR_NAND_ECC_MODE_MASK 0x30000000
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/* 4 bit correction per 520 Byte sector */
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#define CSOR_NAND_ECC_MODE_4 0x00000000
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/* 8 bit correction per 528 Byte sector */
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#define CSOR_NAND_ECC_MODE_8 0x10000000
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#define CSOR_NAND_ECC_DEC_EN 0x04000000
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/* Row Address Length */
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#define CSOR_NAND_RAL_MASK 0x01800000
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#define CSOR_NAND_RAL_SHIFT 20
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#define CSOR_NAND_RAL_1 0x00000000
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#define CSOR_NAND_RAL_2 0x00800000
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#define CSOR_NAND_RAL_3 0x01000000
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#define CSOR_NAND_RAL_4 0x01800000
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/* Page Size 512b, 2k, 4k */
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#define CSOR_NAND_PGS_MASK 0x00180000
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#define CSOR_NAND_PGS_SHIFT 16
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#define CSOR_NAND_PGS_512 0x00000000
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#define CSOR_NAND_PGS_2K 0x00080000
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#define CSOR_NAND_PGS_4K 0x00100000
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#define CSOR_NAND_PGS_8K 0x00180000
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/* Spare region Size */
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#define CSOR_NAND_SPRZ_MASK 0x0000E000
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#define CSOR_NAND_SPRZ_SHIFT 13
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#define CSOR_NAND_SPRZ_16 0x00000000
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#define CSOR_NAND_SPRZ_64 0x00002000
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#define CSOR_NAND_SPRZ_128 0x00004000
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#define CSOR_NAND_SPRZ_210 0x00006000
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#define CSOR_NAND_SPRZ_218 0x00008000
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#define CSOR_NAND_SPRZ_224 0x0000A000
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#define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
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/* Pages Per Block */
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#define CSOR_NAND_PB_MASK 0x00000700
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#define CSOR_NAND_PB_SHIFT 8
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#define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
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/* Time for Read Enable High to Output High Impedance */
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#define CSOR_NAND_TRHZ_MASK 0x0000001C
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#define CSOR_NAND_TRHZ_SHIFT 2
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#define CSOR_NAND_TRHZ_20 0x00000000
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#define CSOR_NAND_TRHZ_40 0x00000004
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#define CSOR_NAND_TRHZ_60 0x00000008
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#define CSOR_NAND_TRHZ_80 0x0000000C
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#define CSOR_NAND_TRHZ_100 0x00000010
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/* Buffer control disable */
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#define CSOR_NAND_BCTLD 0x00000001
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/*
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* Chip Select Option Register - NOR Flash Mode
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*/
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/* Enable Address shift Mode */
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#define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
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/* Page Read Enable from NOR device */
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#define CSOR_NOR_PGRD_EN 0x10000000
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/* AVD Toggle Enable during Burst Program */
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#define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
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/* Address Data Multiplexing Shift */
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#define CSOR_NOR_ADM_MASK 0x0003E000
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#define CSOR_NOR_ADM_SHIFT_SHIFT 13
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#define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
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/* Type of the NOR device hooked */
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#define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
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#define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
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/* Time for Read Enable High to Output High Impedance */
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#define CSOR_NOR_TRHZ_MASK 0x0000001C
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#define CSOR_NOR_TRHZ_SHIFT 2
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#define CSOR_NOR_TRHZ_20 0x00000000
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#define CSOR_NOR_TRHZ_40 0x00000004
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#define CSOR_NOR_TRHZ_60 0x00000008
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#define CSOR_NOR_TRHZ_80 0x0000000C
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#define CSOR_NOR_TRHZ_100 0x00000010
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/* Buffer control disable */
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#define CSOR_NOR_BCTLD 0x00000001
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/*
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* Flash Timing Registers (FTIM0 - FTIM2_CSn)
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*/
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/*
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* FTIM0 - NOR Flash Mode
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*/
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#define FTIM0_NOR 0xF03F3F3F
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#define FTIM0_NOR_TACSE_SHIFT 28
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#define FTIM0_NOR_TACSE(n) ((n) << FTIM0_NOR_TACSE_SHIFT)
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#define FTIM0_NOR_TEADC_SHIFT 16
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#define FTIM0_NOR_TEADC(n) ((n) << FTIM0_NOR_TEADC_SHIFT)
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#define FTIM0_NOR_TAVDS_SHIFT 8
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#define FTIM0_NOR_TAVDS(n) ((n) << FTIM0_NOR_TAVDS_SHIFT)
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#define FTIM0_NOR_TEAHC_SHIFT 0
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#define FTIM0_NOR_TEAHC(n) ((n) << FTIM0_NOR_TEAHC_SHIFT)
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/*
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* FTIM1 - NOR Flash Mode
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*/
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#define FTIM1_NOR 0xFF003F3F
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#define FTIM1_NOR_TACO_SHIFT 24
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#define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT)
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#define FTIM1_NOR_TRAD_NOR_SHIFT 8
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#define FTIM1_NOR_TRAD_NOR(n) ((n) << FTIM1_NOR_TRAD_NOR_SHIFT)
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#define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
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#define FTIM1_NOR_TSEQRAD_NOR(n) ((n) << FTIM1_NOR_TSEQRAD_NOR_SHIFT)
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/*
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* FTIM2 - NOR Flash Mode
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*/
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#define FTIM2_NOR 0x0F3CFCFF
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#define FTIM2_NOR_TCS_SHIFT 24
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#define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT)
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#define FTIM2_NOR_TCH_SHIFT 18
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#define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT)
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#define FTIM2_NOR_TWPH_SHIFT 10
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#define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT)
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#define FTIM2_NOR_TWP_SHIFT 0
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#define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT)
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/*
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* FTIM0 - Normal GPCM Mode
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*/
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#define FTIM0_GPCM 0xF03F3F3F
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#define FTIM0_GPCM_TACSE_SHIFT 28
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#define FTIM0_GPCM_TACSE(n) ((n) << FTIM0_GPCM_TACSE_SHIFT)
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#define FTIM0_GPCM_TEADC_SHIFT 16
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#define FTIM0_GPCM_TEADC(n) ((n) << FTIM0_GPCM_TEADC_SHIFT)
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#define FTIM0_GPCM_TAVDS_SHIFT 8
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#define FTIM0_GPCM_TAVDS(n) ((n) << FTIM0_GPCM_TAVDS_SHIFT)
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#define FTIM0_GPCM_TEAHC_SHIFT 0
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#define FTIM0_GPCM_TEAHC(n) ((n) << FTIM0_GPCM_TEAHC_SHIFT)
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/*
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* FTIM1 - Normal GPCM Mode
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*/
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#define FTIM1_GPCM 0xFF003F00
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#define FTIM1_GPCM_TACO_SHIFT 24
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#define FTIM1_GPCM_TACO(n) ((n) << FTIM1_GPCM_TACO_SHIFT)
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#define FTIM1_GPCM_TRAD_SHIFT 8
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#define FTIM1_GPCM_TRAD(n) ((n) << FTIM1_GPCM_TRAD_SHIFT)
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/*
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* FTIM2 - Normal GPCM Mode
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*/
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#define FTIM2_GPCM 0x0F3C00FF
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#define FTIM2_GPCM_TCS_SHIFT 24
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#define FTIM2_GPCM_TCS(n) ((n) << FTIM2_GPCM_TCS_SHIFT)
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#define FTIM2_GPCM_TCH_SHIFT 18
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#define FTIM2_GPCM_TCH(n) ((n) << FTIM2_GPCM_TCH_SHIFT)
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#define FTIM2_GPCM_TWP_SHIFT 0
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#define FTIM2_GPCM_TWP(n) ((n) << FTIM2_GPCM_TWP_SHIFT)
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/*
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* General Control Register (GCR)
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*/
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#define IFC_GCR_MASK 0x8000F800
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/* reset all IFC hardware */
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#define IFC_GCR_SOFT_RST_ALL 0x80000000
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/* Turnaroud Time of external buffer */
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#define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
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#define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
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/*
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* Clock Control Register (CCR)
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*/
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#define IFC_CCR_MASK 0x0F0F8800
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/* Clock division ratio */
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#define IFC_CCR_CLK_DIV_MASK 0x0F000000
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#define IFC_CCR_CLK_DIV_SHIFT 24
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#define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
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/* IFC Clock Delay */
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#define IFC_CCR_CLK_DLY_MASK 0x000F0000
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#define IFC_CCR_CLK_DLY_SHIFT 16
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#define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
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#ifndef __ASSEMBLY__
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#include <asm/io.h>
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#define IFC_BASE_ADDR ((void __iomem *)IFC_ADDR)
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#define FSL_IFC_CSPRX(i) (0x10 + ((i) * 0xc))
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#define FSL_IFC_CSORX(i) (0x130 + ((i) * 0xc))
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#define FSL_IFC_AMASKX(i) (0xa0 + ((i) * 0xc))
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#define FSL_IFC_CSX_FTIMY(i, j) ((0x1c0 + ((i) * 0x30)) + ((j) * 4))
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#define get_ifc_cspr(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSPRX(i)))
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#define get_ifc_csor(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSORX(i))
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#define get_ifc_amask(i) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_AMASKX(i)))
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#define get_ifc_ftim(i, j) (ifc_in32(IFC_BASE_ADDR + FSL_IFC_CSX_FTIMY(i, j)))
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#define set_ifc_cspr(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSPRX(i), v))
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#define set_ifc_csor(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSORX(i), v))
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#define set_ifc_amask(i, v) (ifc_out32(IFC_BASE_ADDR + FSL_IFC_AMASKX(i), v))
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#define set_ifc_ftim(i, j, v) \
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(ifc_out32(IFC_BASE_ADDR + FSL_IFC_CSX_FTIMY(i, j), v))
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#define FSL_IFC_GCR_OFFSET 0x40c
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#define FSL_IFC_CCR_OFFSET 0x44c
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enum ifc_chip_sel {
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IFC_CS0,
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IFC_CS1,
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IFC_CS2,
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IFC_CS3,
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IFC_CS4,
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IFC_CS5,
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IFC_CS6,
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IFC_CS7,
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};
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enum ifc_ftims {
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IFC_FTIM0,
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IFC_FTIM1,
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IFC_FTIM2,
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IFC_FTIM3,
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};
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#ifdef CONFIG_FSL_ERRATUM_IFC_A002769
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#undef CSPR_MSEL_NOR
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#define CSPR_MSEL_NOR CSPR_MSEL_GPCM
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __FSL_IFC_H */
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@ -69,6 +69,7 @@ enum law_trgt_if {
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#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
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#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
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#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
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#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
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#if defined(CONFIG_P2020)
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@ -851,7 +851,7 @@
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#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
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/* Some parts define SVR[0:23] as the SOC version */
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit */
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#define IS_E_PROCESSOR(svr) ((svr) & 0x80000)
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/*
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#define SVR_8641 0x8090
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#define SVR_8544 0x803401
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#define SVR_8544_E 0x803C01
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#define SVR_P1010 0x80F100
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#define SVR_P1022 0x80E600
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#define SVR_P2020 0x80E200
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#define SVR_P2020_E 0x80EA00
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#define FSL_TSECV2
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#define FSL_ERRATUM_A005125
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#elif defined(CONFIG_P1010)
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#define MAX_CPUS 1
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#define FSL_NUM_LAWS 12
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#define FSL_NUM_TSEC 3
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#define FSL_SEC_COMPAT 4
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#define FSL_ERRATUM_A005125
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#define PPC_E500_DEBUG_TLB 2
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#define FSL_TSECV2
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#else
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#error Processor type not defined for this platform
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#endif
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#include <asm/types.h>
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#include <asm/fsl_lbc.h>
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#include <asm/fsl_ifc.h>
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#include <asm/config.h>
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#define MPC85xx_LOCAL_OFFSET 0x0000
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#define MPC85xx_PCI1_OFFSET 0x8000
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#define MPC85xx_GPIO_OFFSET 0xf000
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#define MPC85xx_IFC_OFFSET 0x1e000
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#define MPC85xx_L2_OFFSET 0x20000
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#ifdef FSL_TSECV2
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#define TSEC1_OFFSET 0xB0000
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#define MPC85xx_GUTS_ADDR (CFG_IMMR + MPC85xx_GUTS_OFFSET)
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#define MPC85xx_DDR_ADDR (CFG_IMMR + MPC85xx_DDR_OFFSET)
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#define LBC_ADDR (CFG_IMMR + MPC85xx_LBC_OFFSET)
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#define IFC_ADDR (CFG_IMMR + MPC85xx_IFC_OFFSET)
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#define MPC85xx_GPIO_ADDR (CFG_IMMR + MPC85xx_GPIO_OFFSET)
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#define MPC85xx_L2_ADDR (CFG_IMMR + MPC85xx_L2_OFFSET)
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#define MPC8xxx_PIC_ADDR (CFG_IMMR + MPC85xx_PIC_OFFSET)
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/*
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* L2 Cache Register Offsets
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*/
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#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */
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#define MPC85xx_L2CTL_L2E 0x80000000
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#define MPC85xx_L2_CTL_OFFSET 0x0 /* L2 configuration 0 */
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#define MPC85xx_L2CTL_L2E 0x80000000
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#define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
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#define MPC85xx_L2_L2SRBAR0_OFFSET 0x100
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#define MPC85xx_L2_L2ERRDIS_OFFSET 0xe44
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#define MPC85xx_L2ERRDIS_MBECC 0x00000008
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#define MPC85xx_L2ERRDIS_SBECC 0x00000004
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/* PIC registers offsets */
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#define MPC85xx_PIC_WHOAMI_OFFSET 0x090
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#define MPC85xx_GUTS_PORDEVSR2_OFFSET 0x14
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#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
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#define MPC85xx_GUTS_PMUXCR_OFFSET 0x60
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#define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
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#define MPC85xx_GUTS_PMUXCR2_OFFSET 0x64
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#define MPC85xx_GUTS_DEVDISR_OFFSET 0x70
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#define MPC85xx_DEVDISR_TB0 0x00004000
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