sysmo-bts
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barebox
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Merge branch 'next'

This commit is contained in:
Sascha Hauer 2010-08-30 21:06:33 +02:00
parent 3d5d2279c0 0d35c3c8a0
commit 80f9963207
229 changed files with 14942 additions and 3384 deletions
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4
.gitignore vendored
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@ -19,6 +19,7 @@
*.symtypes
*.elf
*.mcp
*.orig
#
# Top-level generic files
@ -59,3 +60,6 @@ series
# cscope files
cscope.*
# patches
*.patch

6
Makefile
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@ -290,7 +290,7 @@ LINUXINCLUDE := -Iinclude \
$(if $(KBUILD_SRC),-Iinclude2 -I$(srctree)/include) \
-I$(srctree)/arch/$(ARCH)/include \
-I$(objtree)/arch/$(ARCH)/include \
-include include/linux/autoconf.h
-include include/generated/autoconf.h
CPPFLAGS := -D__KERNEL__ -D__BAREBOX__ $(LINUXINCLUDE) -fno-builtin -ffreestanding
@ -305,7 +305,7 @@ KERNELRELEASE = $(shell cat include/config/kernel.release 2> /dev/null)
KERNELVERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
export VERSION PATCHLEVEL SUBLEVEL KERNELRELEASE KERNELVERSION
export ARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC
export ARCH SRCARCH CONFIG_SHELL HOSTCC HOSTCFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM STRIP OBJCOPY OBJDUMP MAKE AWK GENKSYMS PERL UTS_MACHINE
export HOSTCXX HOSTCXXFLAGS LDFLAGS_MODULE CHECK CHECKFLAGS
@ -978,7 +978,7 @@ CLEAN_FILES += barebox System.map include/barebox_default_env.h \
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include2 usr/include
MRPROPER_FILES += .config .config.old include/asm .version .old_version \
include/linux/autoconf.h include/linux/version.h \
include/generated/autoconf.h include/linux/version.h \
include/linux/utsrelease.h include/config.h \
Module.symvers tags TAGS cscope*

16
arch/arm/Kconfig
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@ -18,6 +18,9 @@ config ARM
select HAVE_CONFIGURABLE_TEXT_BASE
default y
config ARM_AMBA
bool
menu "System Type"
choice
@ -27,10 +30,6 @@ config ARCH_AT91
bool "Atmel AT91"
select GENERIC_GPIO
config ARCH_AT91RM9200
bool "Atmel AT91RM9200"
select CPU_ARM920T
config ARCH_EP93XX
bool "Cirrus Logic EP93xx"
select CPU_ARM920T
@ -44,6 +43,12 @@ config ARCH_NETX
bool "Hilscher NetX based"
select CPU_ARM926T
config ARCH_NOMADIK
bool "STMicroelectronics Nomadik"
select CPU_ARM926T
help
Support for the Nomadik platform by ST-Ericsson
config ARCH_OMAP
bool "TI OMAP"
@ -53,12 +58,13 @@ config ARCH_S3C24xx
endchoice
source arch/arm/common/Kconfig
source arch/arm/cpu/Kconfig
source arch/arm/mach-at91/Kconfig
source arch/arm/mach-at91rm9200/Kconfig
source arch/arm/mach-ep93xx/Kconfig
source arch/arm/mach-imx/Kconfig
source arch/arm/mach-netx/Kconfig
source arch/arm/mach-nomadik/Kconfig
source arch/arm/mach-omap/Kconfig
source arch/arm/mach-s3c24xx/Kconfig

5
arch/arm/Makefile
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@ -39,9 +39,9 @@ CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) := at91
machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
machine-$(CONFIG_ARCH_EP93XX) := ep93xx
machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx
@ -69,6 +69,7 @@ board-$(CONFIG_MACH_IMX21ADS) := imx21ads
board-$(CONFIG_MACH_IMX27ADS) := imx27ads
board-$(CONFIG_MACH_MMCCPU) := mmccpu
board-$(CONFIG_MACH_MX1ADS) := mx1ads
board-$(CONFIG_MACH_NOMADIK_8815NHK) := nhk8815
board-$(CONFIG_MACH_NXDB500) := netx
board-$(CONFIG_ARCH_OMAP) := omap
board-$(CONFIG_MACH_PCA100) := phycard-i.MX27
@ -130,7 +131,7 @@ MACH :=
endif
common-y += $(BOARD) $(MACH)
common-y += arch/arm/lib/ arch/arm/cpu/
common-y += arch/arm/lib/ arch/arm/cpu/ arch/arm/common/
lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/arm/lib/barebox.lds
lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/barebox.lds

2
arch/arm/boards/at91sam9260ek/config.h
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@ -1,6 +1,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
#endif /* __CONFIG_H */

2
arch/arm/boards/at91sam9263ek/config.h
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@ -1,7 +1,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MASTER_CLOCK 100000000 /* peripheral = main / 2 */
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
#define MASTER_PLL_MUL 171
#define MASTER_PLL_DIV 14

3
arch/arm/boards/at91sam9263ek/init.c
View File

@ -108,9 +108,6 @@ static int at91sam9263ek_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
at91_add_device_sdram(64 * 1024 * 1024);
ek_add_device_nand();
at91_add_device_eth(&macb_pdata);

2
arch/arm/boards/freescale-mx25-3-stack/3stack.c
View File

@ -36,6 +36,7 @@
#include <nand.h>
#include <mach/imx-flash-header.h>
#include <mach/iomux-mx25.h>
#include <mach/generic.h>
#include <linux/err.h>
#include <i2c/i2c.h>
#include <i2c/mc34704.h>
@ -275,6 +276,7 @@ static int imx25_devices_init(void)
armlinux_add_dram(&sdram0_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX25_3DS);
armlinux_set_serial(imx_uid());
return 0;
}

2
arch/arm/boards/mmccpu/config.h
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@ -1,7 +1,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MASTER_CLOCK 99532800 /* peripheral = main / 2 */
#define AT91_MAIN_CLOCK 18432000
/* values */
#define MASTER_PLL_MUL 54

3
arch/arm/boards/mmccpu/init.c
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@ -58,9 +58,6 @@ static int mmccpu_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
at91_add_device_sdram(128 * 1024 * 1024);
at91_add_device_eth(&macb_pdata);
register_device(&cfi_dev);

1
arch/arm/boards/nhk8815/Makefile Normal file
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@ -0,0 +1 @@
obj-y += setup.o

0
arch/arm/boards/nhk8815/config.h Normal file
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36
arch/arm/boards/nhk8815/env/bin/_update vendored Normal file
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@ -0,0 +1,36 @@
#!/bin/sh
if [ -z "$part" -o -z "$image" ]; then
echo "define \$part and \$image"
exit 1
fi
if [ \! -e "$part" ]; then
echo "Partition $part does not exist"
exit 1
fi
if [ $# = 1 ]; then
image=$1
fi
if [ x$ip = xdhcp ]; then
dhcp
fi
ping $eth0.serverip
if [ $? -ne 0 ] ; then
echo "update aborted"
exit 1
fi
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing $image to $part"
echo
tftp $image $part

38
arch/arm/boards/nhk8815/env/bin/boot vendored Normal file
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@ -0,0 +1,38 @@
#!/bin/sh
. /env/config
if [ x$1 = xflash ]; then
root=flash
kernel=flash
fi
if [ x$1 = xnet ]; then
root=net
kernel=net
fi
if [ x$ip = xdhcp ]; then
bootargs="$bootargs ip=dhcp"
else
bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::"
fi
if [ x$root = xflash ]; then
bootargs="$bootargs root=$rootpart rootfstype=jffs2"
else
bootargs="$bootargs root=/dev/nfs nfsroot=192.168.23.111:$nfsroot"
fi
bootargs="$bootargs"
if [ $kernel = net ]; then
if [ x$ip = xdhcp ]; then
dhcp
fi
tftp $uimage uImage
bootm uImage
else
bootm /dev/nor0.kernel
fi

28
arch/arm/boards/nhk8815/env/bin/init vendored Normal file
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@ -0,0 +1,28 @@
#!/bin/sh
PATH=/env/bin
export PATH
. /env/config
if [ -e /dev/nand0 ]; then
addpart /dev/nand0 $nand_parts
# Uh, oh, hush first expands wildcards and then starts executing
# commands. What a bug!
source /env/bin/hush_hack
fi
echo
echo -n "Hit any key to stop autoboot: "
timeout -a $autoboot_timeout
if [ $? != 0 ]; then
echo
echo "type update_kernel [<imagename>] to update kernel into flash"
echo "type udate_root [<imagename>] to update rootfs into flash"
echo "type update_barebox_xmodem nor to update barebox into flash"
echo
exit
fi
boot

19
arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem vendored Normal file
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@ -0,0 +1,19 @@
#!/bin/sh
. /env/config
part=/dev/nand0.barebox
loadb -f barebox.bin -c
unprotect $part
echo
echo "erasing partition $part"
erase $part
echo
echo "flashing barebox.bin to $part"
echo
cp barebox.bin $part
crc32 -f barebox.bin
crc32 -f $part

8
arch/arm/boards/nhk8815/env/bin/update_kernel vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$uimage
part=/dev/nand0.kernel
. /env/bin/_update $1

8
arch/arm/boards/nhk8815/env/bin/update_root vendored Normal file
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@ -0,0 +1,8 @@
#!/bin/sh
. /env/config
image=$jffs2
part=/dev/nand0.rootfs
. /env/bin/_update $1

32
arch/arm/boards/nhk8815/env/config vendored Normal file
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@ -0,0 +1,32 @@
#!/bin/sh
# can be either 'net' or 'flash'
kernel=net
root=net
# use 'dhcp' todo dhcp in uboot and in kernel
ip=dhcp
#
# setup default ethernet address
#
#eth0.serverip=192.168.23.108
# Partition Size Start
# XloaderTOC + X-Loader 256KB 0x00000000
# Memory init function 256KB 0x00040000
# Barebox + env 2MB 0x00080000
# Kernel Image 3MB 0x00280000
# JFFS2 Root filesystem 22MB 0x00580000
# JFFS2 User Data 100MB 0x01b80000
nand_parts="256k(xloader)ro,256k(meminit),2M(uboot),3M(kernel),22M(rootfs),100M(userfs),384k(free),128k(ubootenv)"
uimage=uImage-nhk15
# use 'dhcp' to do dhcp in uboot and in kernel
ip=dhcp
autoboot_timeout=3
bootargs="root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc"

106
arch/arm/boards/nhk8815/setup.c Normal file
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@ -0,0 +1,106 @@
/*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <init.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <partition.h>
#include <nand.h>
#include <asm/armlinux.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <mach/hardware.h>
#include <mach/board.h>
#include <mach/nand.h>
#include <mach/fsmc.h>
static struct device_d nhk8815_network_dev = {
.name = "smc91c111",
.map_base = 0x34000300,
.size = 16,
};
static int nhk8815_nand_init(void)
{
/* FSMC setup for nand chip select (8-bit nand in 8815NHK) */
writel(0x0000000E, FSMC_PCR(0));
writel(0x000D0A00, FSMC_PMEM(0));
writel(0x00100A00, FSMC_PATT(0));
/* enable access to the chip select area */
writel(readl(FSMC_PCR(0)) | 0x04, FSMC_PCR(0));
return 0;
}
static struct nomadik_nand_platform_data nhk8815_nand_data = {
.addr_va = NAND_IO_ADDR,
.cmd_va = NAND_IO_CMD,
.data_va = NAND_IO_DATA,
.options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \
| NAND_NO_READRDY | NAND_NO_AUTOINCR,
.init = nhk8815_nand_init,
};
static struct device_d nhk8815_nand_device = {
.name = "nomadik_nand",
.platform_data = &nhk8815_nand_data,
};
static int nhk8815_devices_init(void)
{
st8815_add_device_sdram(64 * 1024 *1024);
writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20);
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24);
writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28);
writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE);
/* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */
writel(0x0000305b, FSMC_BCR(1));
writel(0x00033f33, FSMC_BTR(1));
register_device(&nhk8815_network_dev);
register_device(&nhk8815_nand_device);
armlinux_set_architecture(MACH_TYPE_NOMADIK);
armlinux_set_bootparams((void *)(0x00000100));
devfs_add_partition("nand0", 0x0000000, 0x040000, PARTITION_FIXED, "xloader_raw");
devfs_add_partition("nand0", 0x0040000, 0x080000, PARTITION_FIXED, "meminit_raw");
devfs_add_partition("nand0", 0x0080000, 0x200000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x7FE0000, 0x020000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
return 0;
}
device_initcall(nhk8815_devices_init);
static int nhk8815_console_init(void)
{
st8815_register_uart(1);
return 0;
}
console_initcall(nhk8815_console_init);

64
arch/arm/boards/omap/board-beagle.c
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@ -59,6 +59,7 @@
#include <asm/io.h>
#include <ns16550.h>
#include <asm/armlinux.h>
#include <asm/mach-types.h>
#include <mach/silicon.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
@ -67,6 +68,10 @@
#include <mach/omap3-mux.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
#include <mach/ehci.h>
#include <i2c/i2c.h>
#include <linux/err.h>
#include <usb/ehci.h>
#include "board.h"
/******************** Board Boot Time *******************/
@ -189,6 +194,20 @@ static void mux_config(void)
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0));
/* I2C1_SCL default mux mode is mode0 */
/* I2C1_SDA default mux mode is mode0 */
/* USB EHCI (port 2) */
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTU | DIS | M3));
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTU | DIS | M3));
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3));
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M3));
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/;
}
/**
@ -254,6 +273,42 @@ static struct device_d sdram_dev = {
.platform_data = &sram_pdata,
};
#ifdef CONFIG_USB_EHCI_OMAP
static struct omap_hcd omap_ehci_pdata = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.phy_reset = 1,
.reset_gpio_port[0] = -EINVAL,
.reset_gpio_port[1] = 147,
.reset_gpio_port[2] = -EINVAL
};
static struct ehci_platform_data ehci_pdata = {
.flags = 0,
.hccr_offset = 0x100,
.hcor_offset = 0x110,
};
static struct device_d usbh_dev = {
.name = "ehci",
.map_base = 0x48064700,
.size = 4 * 1024,
.platform_data = &ehci_pdata,
};
#endif /* CONFIG_USB_EHCI_OMAP */
static struct device_d i2c_dev = {
.name = "i2c-omap",
.map_base = OMAP_I2C1_BASE,
};
static struct i2c_board_info i2c_devices[] = {
{
I2C_BOARD_INFO("twl4030", 0x48),
},
};
static int beagle_devices_init(void)
{
int ret;
@ -262,6 +317,13 @@ static int beagle_devices_init(void)
if (ret)
goto failed;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
#ifdef CONFIG_USB_EHCI_OMAP
if (ehci_omap_init(&omap_ehci_pdata) >= 0)
register_device(&usbh_dev);
#endif /* CONFIG_USB_EHCI_OMAP */
#ifdef CONFIG_GPMC
/* WP is made high and WAIT1 active Low */
gpmc_generic_init(0x10);
@ -269,6 +331,8 @@ static int beagle_devices_init(void)
gpmc_generic_nand_devices_init(0, 16, 1);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_OMAP3_BEAGLE);
failed:
return ret;
}

2
arch/arm/boards/pm9263/config.h
View File

@ -1,7 +1,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define AT91_MASTER_CLOCK 99328000 /* peripheral = main / 2 */
#define AT91_MAIN_CLOCK 18432000
#define MASTER_PLL_DIV 6
#define MASTER_PLL_MUL 65

3
arch/arm/boards/pm9263/init.c
View File

@ -107,9 +107,6 @@ static int pm9263_devices_init(void)
at91_set_gpio_output(AT91_PIN_PB27, 1);
at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
at91_add_device_sdram(64 * 1024 * 1024);
pm_add_device_nand();
at91_add_device_eth(&macb_pdata);

1
arch/arm/boards/scb9328/scb9328.c
View File

@ -55,6 +55,7 @@ static struct dm9000_platform_data dm9000_data = {
.iobase = 0x16000000,
.iodata = 0x16000004,
.buswidth = DM9000_WIDTH_16,
.srom = 1;
};
static struct device_d dm9000_dev = {

2
arch/arm/common/Kconfig Normal file
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@ -0,0 +1,2 @@
config COMMON_CLKDEV
bool

5
arch/arm/common/Makefile Normal file
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@ -0,0 +1,5 @@
#
# Makefile for the linux kernel.
#
obj-$(CONFIG_COMMON_CLKDEV) += clkdev.o

160
arch/arm/common/clkdev.c Normal file
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@ -0,0 +1,160 @@
/*
* arch/arm/common/clkdev.c
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#include <common.h>
#include <linux/list.h>
#include <errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <init.h>
#include <malloc.h>
#include <stdio.h>
#include <asm/clkdev.h>
#include <mach/clkdev.h>
static LIST_HEAD(clocks);
/*
* Find the correct struct clk for the device and connection ID.
* We do slightly fuzzy matching here:
* An entry with a NULL ID is assumed to be a wildcard.
* If an entry has a device ID, it must match
* If an entry has a connection ID, it must match
* Then we take the most specific entry - with the following
* order of precidence: dev+con > dev only > con only.
*/
static struct clk *clk_find(const char *dev_id, const char *con_id)
{
struct clk_lookup *p;
struct clk *clk = NULL;
int match, best = 0;
list_for_each_entry(p, &clocks, node) {
match = 0;
if (p->dev_id) {
if (!dev_id || strcmp(p->dev_id, dev_id))
continue;
match += 2;
}
if (p->con_id) {
if (!con_id || strcmp(p->con_id, con_id))
continue;
match += 1;
}
if (match == 0)
continue;
if (match > best) {
clk = p->clk;
best = match;
}
}
return clk;
}
struct clk *clk_get_sys(const char *dev_id, const char *con_id)
{
struct clk *clk;
clk = clk_find(dev_id, con_id);
if (clk && !__clk_get(clk))
clk = NULL;
return clk ? clk : ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get_sys);
struct clk *clk_get(struct device_d *dev, const char *con_id)
{
const char *dev_id = dev ? dev_name(dev) : NULL;
return clk_get_sys(dev_id, con_id);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
__clk_put(clk);
}
EXPORT_SYMBOL(clk_put);
void clkdev_add(struct clk_lookup *cl)
{
list_add_tail(&cl->node, &clocks);
}
EXPORT_SYMBOL(clkdev_add);
#define MAX_DEV_ID 20
#define MAX_CON_ID 16
struct clk_lookup_alloc {
struct clk_lookup cl;
char dev_id[MAX_DEV_ID];
char con_id[MAX_CON_ID];
};
struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
const char *dev_fmt, ...)
{
struct clk_lookup_alloc *cla;
cla = kzalloc(sizeof(*cla), GFP_KERNEL);
if (!cla)
return NULL;
cla->cl.clk = clk;
if (con_id) {
strlcpy(cla->con_id, con_id, sizeof(cla->con_id));
cla->cl.con_id = cla->con_id;
}
if (dev_fmt) {
va_list ap;
va_start(ap, dev_fmt);
vscnprintf(cla->dev_id, sizeof(cla->dev_id), dev_fmt, ap);
cla->cl.dev_id = cla->dev_id;
va_end(ap);
}
return &cla->cl;
}
EXPORT_SYMBOL(clkdev_alloc);
int clk_add_alias(const char *alias, const char *alias_dev_name, char *id,
struct device_d *dev)
{
struct clk *r = clk_get(dev, id);
struct clk_lookup *l;
if (IS_ERR(r))
return PTR_ERR(r);
l = clkdev_alloc(r, alias, alias_dev_name);
clk_put(r);
if (!l)
return -ENODEV;
clkdev_add(l);
return 0;
}
EXPORT_SYMBOL(clk_add_alias);
/*
* clkdev_drop - remove a clock dynamically allocated
*/
void clkdev_drop(struct clk_lookup *cl)
{
list_del(&cl->node);
kfree(cl);
}
EXPORT_SYMBOL(clkdev_drop);

2
arch/arm/configs/a9m2410_defconfig
View File

@ -198,7 +198,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_S3C24X0=y
# CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/a9m2440_defconfig
View File

@ -200,7 +200,7 @@ CONFIG_NET_TFTP=y
CONFIG_DRIVER_SERIAL_S3C24X0=y
# CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC is not set
CONFIG_HAS_CS8900=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/at91sam9260ek_defconfig
View File

@ -185,7 +185,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_ATMEL=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/at91sam9263ek_defconfig
View File

@ -189,7 +189,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_ATMEL=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/edb93xx_defconfig
View File

@ -199,7 +199,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_PL010=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/eukrea_cpuimx25_defconfig
View File

@ -211,7 +211,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/eukrea_cpuimx27_defconfig
View File

@ -219,7 +219,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/eukrea_cpuimx35_defconfig
View File

@ -214,7 +214,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/freescale_mx25_3stack_defconfig
View File

@ -201,7 +201,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/freescale_mx35_3stack_defconfig
View File

@ -201,7 +201,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/mmccpu_defconfig
View File

@ -189,7 +189,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_ATMEL=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/neso_defconfig
View File

@ -212,7 +212,7 @@ CONFIG_NET_RESOLV=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/netx_nxdb500_defconfig
View File

@ -184,7 +184,7 @@ CONFIG_NET_TFTP=y
CONFIG_DRIVER_SERIAL_NETX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_HAS_NETX_ETHER=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

232
arch/arm/configs/nhk8815_defconfig Normal file
View File

@ -0,0 +1,232 @@
#
# Automatically generated make config: don't edit
# U-Boot version: 2.0.0-rc10
# Mon Oct 12 18:36:24 2009
#
# CONFIG_BOARD_LINKER_SCRIPT is not set
CONFIG_GENERIC_LINKER_SCRIPT=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
#
# System Type
#
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_NETX is not set
CONFIG_ARCH_NOMADIK=y
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_S3C24xx is not set
CONFIG_COMMON_CLKDEV=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
#
# processor features
#
CONFIG_ARCH_TEXT_BASE=0x03c00000
CONFIG_BOARDINFO="NHK8815"
CONFIG_MACH_NOMADIK_8815NHK=y
CONFIG_NOMADIK_8815=y
# CONFIG_AEABI is not set
#
# Arm specific settings
#
CONFIG_CMD_ARM_CPUINFO=y
CONFIG_CMDLINE_TAG=y
CONFIG_SETUP_MEMORY_TAGS=y
# CONFIG_INITRD_TAG is not set
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_GREGORIAN_CALENDER=y
CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
#
# General Settings
#
CONFIG_LOCALVERSION_AUTO=y
#
# memory layout
#
CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
CONFIG_TEXT_BASE=0x03F80000
CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
CONFIG_MEMORY_LAYOUT_DEFAULT=y
# CONFIG_MEMORY_LAYOUT_FIXED is not set
CONFIG_STACK_SIZE=0x8000
CONFIG_MALLOC_SIZE=0x400000
# CONFIG_BROKEN is not set
# CONFIG_EXPERIMENTAL is not set
CONFIG_PROMPT="Nomadik:"
CONFIG_BAUDRATE=115200
CONFIG_LONGHELP=y
CONFIG_CBSIZE=1024
CONFIG_MAXARGS=16
CONFIG_SHELL_HUSH=y
# CONFIG_SHELL_SIMPLE is not set
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="> "
# CONFIG_HUSH_FANCY_PROMPT is not set
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_ERRNO_MESSAGES=y
CONFIG_TIMESTAMP=y
CONFIG_CONSOLE_FULL=y
CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
CONFIG_DEFAULT_ENVIRONMENT=y
CONFIG_DEFAULT_ENVIRONMENT_PATH="board/nhk8815/env"
#
# Debugging
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_FLASH_NOISE is not set
# CONFIG_ENABLE_PARTITION_NOISE is not set
# CONFIG_ENABLE_DEVICE_NOISE is not set
#
# Commands
#
#
# scripting
#
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TRUE=y
CONFIG_CMD_FALSE=y
#
# file commands
#
CONFIG_CMD_LS=y
CONFIG_CMD_RM=y
CONFIG_CMD_CAT=y
CONFIG_CMD_MKDIR=y
CONFIG_CMD_RMDIR=y
CONFIG_CMD_CP=y
CONFIG_CMD_PWD=y
CONFIG_CMD_CD=y
CONFIG_CMD_MOUNT=y
CONFIG_CMD_UMOUNT=y
#
# console
#
CONFIG_CMD_CLEAR=y
CONFIG_CMD_ECHO=y
# CONFIG_CMD_ECHO_E is not set
#
# memory
#
# CONFIG_CMD_LOADB is not set
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_CRC=y
CONFIG_CMD_MTEST=y
# CONFIG_CMD_MTEST_ALTERNATIVE is not set
#
# flash
#
CONFIG_CMD_FLASH=y
# CONFIG_CMD_UBI is not set
#
# booting
#
CONFIG_CMD_BOOTM=y
CONFIG_CMD_BOOTM_ZLIB=y
CONFIG_CMD_BOOTM_BZLIB=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTU=y
# CONFIG_CMD_LINUX16 is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_DEVINFO=y
# CONFIG_CMD_UNLZO is not set
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
# CONFIG_NET_TFTP_PUSH is not set
# CONFIG_NET_NETCONSOLE is not set
# CONFIG_NET_RESOLV is not set
#
# Drivers
#
#
# serial drivers
#
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_SERIAL_AMBA_PL011=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIDEV=y
#
# Network drivers
#
# CONFIG_DRIVER_NET_SMC911X is not set
CONFIG_DRIVER_NET_SMC91111=y
#
# SPI drivers
#
# CONFIG_SPI is not set
# CONFIG_I2C is not set
#
# flash drivers
#
# CONFIG_DRIVER_CFI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_MTD_NAND_VERIFY_WRITE=y
CONFIG_MTD_NAND_ECC_SMC=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_NOMADIK=y
# CONFIG_UBI is not set
# CONFIG_ATA is not set
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
# CONFIG_VIDEO is not set
#
# Filesystem support
#
# CONFIG_FS_CRAMFS is not set
CONFIG_FS_RAMFS=y
CONFIG_FS_DEVFS=y
CONFIG_ZLIB=y
CONFIG_BZLIB=y
CONFIG_CRC32=y
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set

257
arch/arm/configs/omap3530_beagle_defconfig Normal file
View File

@ -0,0 +1,257 @@
#
# Automatically generated make config: don't edit
# barebox version: 2010.08.0
# Tue Aug 10 18:52:24 2010
#
# CONFIG_BOARD_LINKER_SCRIPT is not set
CONFIG_GENERIC_LINKER_SCRIPT=y
CONFIG_ARM=y
#
# System Type
#
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_AT91RM9200 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_NOMADIK is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_S3C24xx is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
#
# processor features
#
CONFIG_ARCH_TEXT_BASE=0x80e80000
CONFIG_BOARDINFO="Texas Instrument's Beagle"
#
# OMAP Features
#
CONFIG_ARCH_OMAP3=y
CONFIG_OMAP_CLOCK_ALL=y
CONFIG_OMAP_CLOCK_SOURCE_S32K=y
CONFIG_OMAP3_CLOCK_CONFIG=y
# CONFIG_OMAP3_COPY_CLOCK_SRAM is not set
CONFIG_GPMC=y
CONFIG_GPIO=y
#
# OMAP Platform Features
#
# CONFIG_MACH_OMAP343xSDP is not set
CONFIG_MACH_BEAGLE=y
# CONFIG_MACH_OMAP3EVM is not set
CONFIG_HAS_OMAP_NAND=y
CONFIG_AEABI=y
#
# Arm specific settings
#
CONFIG_CMD_ARM_CPUINFO=y
# CONFIG_CPU_V7_DCACHE_SKIP is not set
# CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS is not set
CONFIG_HAS_KALLSYMS=y
CONFIG_HAS_MODULES=y
CONFIG_CMD_MEMORY=y
CONFIG_ENV_HANDLING=y
CONFIG_GENERIC_GPIO=y
#
# General Settings
#
CONFIG_LOCALVERSION_AUTO=y
#
# memory layout
#
CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y
CONFIG_MEMORY_LAYOUT_DEFAULT=y
# CONFIG_MEMORY_LAYOUT_FIXED is not set
CONFIG_STACK_SIZE=0x8000
CONFIG_MALLOC_SIZE=0x400000
# CONFIG_BROKEN is not set
# CONFIG_EXPERIMENTAL is not set
CONFIG_MACH_HAS_LOWLEVEL_INIT=y
CONFIG_MACH_DO_LOWLEVEL_INIT=y
CONFIG_ARCH_HAS_LOWLEVEL_INIT=y
CONFIG_PROMPT="barebox> "
CONFIG_BAUDRATE=115200
CONFIG_LONGHELP=y
CONFIG_CBSIZE=1024
CONFIG_MAXARGS=16
CONFIG_SHELL_HUSH=y
# CONFIG_SHELL_SIMPLE is not set
CONFIG_GLOB=y
CONFIG_PROMPT_HUSH_PS2="> "
CONFIG_HUSH_FANCY_PROMPT=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_DYNAMIC_CRC_TABLE=y
CONFIG_ERRNO_MESSAGES=y
# CONFIG_TIMESTAMP is not set
CONFIG_CONSOLE_FULL=y
CONFIG_CONSOLE_ACTIVATE_FIRST=y
# CONFIG_OF_FLAT_TREE is not set
CONFIG_PARTITION=y
# CONFIG_DEFAULT_ENVIRONMENT is not set
#
# Debugging
#
# CONFIG_DEBUG_INFO is not set
# CONFIG_ENABLE_FLASH_NOISE is not set
# CONFIG_ENABLE_PARTITION_NOISE is not set
# CONFIG_ENABLE_DEVICE_NOISE is not set
#
# Commands
#
#
# scripting
#
CONFIG_CMD_EDIT=y
CONFIG_CMD_SLEEP=y
CONFIG_CMD_SAVEENV=y
CONFIG_CMD_LOADENV=y
CONFIG_CMD_EXPORT=y
CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_TRUE=y
CONFIG_CMD_FALSE=y
#
# file commands
#
CONFIG_CMD_LS=y
CONFIG_CMD_RM=y
CONFIG_CMD_CAT=y
CONFIG_CMD_MKDIR=y
CONFIG_CMD_RMDIR=y
CONFIG_CMD_CP=y
CONFIG_CMD_PWD=y
CONFIG_CMD_CD=y
CONFIG_CMD_MOUNT=y
CONFIG_CMD_UMOUNT=y
#
# console
#
CONFIG_CMD_CLEAR=y
CONFIG_CMD_ECHO=y
CONFIG_CMD_ECHO_E=y
#
# memory
#
CONFIG_CMD_LOADB=y
# CONFIG_CMD_MEMINFO is not set
# CONFIG_CMD_CRC is not set
# CONFIG_CMD_MTEST is not set
#
# flash
#
CONFIG_CMD_FLASH=y
# CONFIG_CMD_UBI is not set
#
# booting
#
# CONFIG_CMD_BOOTM is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_BOOTU=y
# CONFIG_CMD_LINUX16 is not set
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_TEST=y
CONFIG_CMD_VERSION=y
CONFIG_CMD_HELP=y
CONFIG_CMD_DEVINFO=y
# CONFIG_CMD_GPIO is not set
CONFIG_CMD_UNLZO=y
CONFIG_CMD_I2C=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
CONFIG_NET_PING=y
CONFIG_NET_TFTP=y
# CONFIG_NET_TFTP_PUSH is not set
# CONFIG_NET_NETCONSOLE is not set
# CONFIG_NET_RESOLV is not set
#
# Drivers
#
#
# serial drivers
#
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
CONFIG_MIIDEV=y
#
# Network drivers
#
# CONFIG_DRIVER_NET_SMC911X is not set
# CONFIG_DRIVER_NET_SMC91111 is not set
CONFIG_NET_USB=y
CONFIG_NET_USB_ASIX=y
#
# SPI drivers
#
# CONFIG_SPI is not set
CONFIG_I2C=y
CONFIG_DRIVER_I2C_OMAP=y
# CONFIG_DRIVER_I2C_MC13892 is not set
# CONFIG_DRIVER_I2C_MC34704 is not set
# CONFIG_DRIVER_I2C_MC9SDZ60 is not set
# CONFIG_DRIVER_I2C_LP3972 is not set
CONFIG_DRIVER_I2C_TWL4030=y
#
# flash drivers
#
# CONFIG_DRIVER_CFI is not set
CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_NAND_OMAP_GPMC=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_UBI is not set
# CONFIG_ATA is not set
CONFIG_USB=y
CONFIG_USB_EHCI=y
CONFIG_USB_EHCI_OMAP=y
# CONFIG_USB_ISP1504 is not set
CONFIG_USB_TWL4030=y
# CONFIG_USB_GADGET is not set
# CONFIG_VIDEO is not set
#
# Filesystem support
#
# CONFIG_FS_CRAMFS is not set
CONFIG_FS_RAMFS=y
CONFIG_FS_DEVFS=y
CONFIG_CRC32=y
CONFIG_CRC16=y
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
CONFIG_PROCESS_ESCAPE_SEQUENCE=y
CONFIG_LZO_DECOMPRESS=y

2
arch/arm/configs/pca100_defconfig
View File

@ -210,7 +210,7 @@ CONFIG_NET_NETCONSOLE=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/pcm037_defconfig
View File

@ -211,7 +211,7 @@ CONFIG_NET_NETCONSOLE=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/pcm038_defconfig
View File

@ -211,7 +211,7 @@ CONFIG_NET_NETCONSOLE=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/pcm043_defconfig
View File

@ -213,7 +213,7 @@ CONFIG_NET_NETCONSOLE=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/pm9263_defconfig
View File

@ -189,7 +189,7 @@ CONFIG_NET_TFTP=y
# CONFIG_DRIVER_SERIAL_ARM_DCC is not set
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_DRIVER_SERIAL_ATMEL=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

2
arch/arm/configs/scb9328_defconfig
View File

@ -201,7 +201,7 @@ CONFIG_NET_TFTP=y
CONFIG_DRIVER_SERIAL_IMX=y
# CONFIG_DRIVER_SERIAL_NS16550 is not set
CONFIG_HAS_DM9000=y
CONFIG_MIIPHY=y
CONFIG_MIIDEV=y
#
# Network drivers

6
arch/arm/include/asm/armlinux.h
View File

@ -7,6 +7,7 @@ void armlinux_set_bootparams(void *params);
void armlinux_set_architecture(int architecture);
void armlinux_add_dram(struct device_d *dev);
void armlinux_set_revision(unsigned int);
void armlinux_set_serial(u64);
#else
static inline void armlinux_set_bootparams(void *params)
{
@ -20,10 +21,13 @@ static inline void armlinux_add_dram(struct device_d *dev)
{
}
static inline void armlinux_set_revision(unsigned int)
static inline void armlinux_set_revision(unsigned int rev)
{
}
void armlinux_set_serial(u64)
{
}
#endif
#endif /* __ARCH_ARMLINUX_H */

30
arch/arm/include/asm/clkdev.h Normal file
View File

@ -0,0 +1,30 @@
/*
* arch/arm/include/asm/clkdev.h
*
* Copyright (C) 2008 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Helper for the clk API to assist looking up a struct clk.
*/
#ifndef __ASM_CLKDEV_H
#define __ASM_CLKDEV_H
struct clk;
struct clk_lookup {
struct list_head node;
const char *dev_id;
const char *con_id;
struct clk *clk;
};
struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
const char *dev_fmt, ...);
void clkdev_add(struct clk_lookup *cl);
void clkdev_drop(struct clk_lookup *cl);
#endif

6
arch/arm/include/asm/unaligned.h
View File

@ -1,9 +1,9 @@
#ifndef _ASM_ARM_UNALIGNED_H
#define _ASM_ARM_UNALIGNED_H
#include <unaligned/le_byteshift.h>
#include <unaligned/be_byteshift.h>
#include <unaligned/generic.h>
#include <linux/unaligned/le_byteshift.h>
#include <linux/unaligned/be_byteshift.h>
#include <linux/unaligned/generic.h>
/*
* Select endianness

19
arch/arm/lib/armlinux.c
View File

@ -46,6 +46,7 @@ static int armlinux_architecture = 0;
static void *armlinux_bootparams = NULL;
static unsigned int system_rev;
static u64 system_serial;
static void setup_start_tag(void)
{
@ -121,6 +122,19 @@ static void setup_revision_tag(void)
}
}
static void setup_serial_tag(void)
{
if (system_serial) {
params->hdr.tag = ATAG_SERIAL;
params->hdr.size = tag_size(tag_serialnr);
params->u.serialnr.low = system_serial & 0xffffffff;
params->u.serialnr.high = system_serial >> 32;
params = tag_next(params);
}
}
#if 0
static void setup_initrd_tag(ulong initrd_start, ulong initrd_end)
{
@ -155,6 +169,7 @@ static void setup_tags(void)
setup_initrd_tag (initrd_start, initrd_end);
#endif
setup_revision_tag();
setup_serial_tag();
setup_end_tag();
printf("commandline: %s\n"
@ -186,6 +201,10 @@ void armlinux_set_revision(unsigned int rev)
system_rev = rev;
}
void armlinux_set_serial(u64 serial)
{
system_serial = serial;
}
#ifdef CONFIG_CMD_BOOTM
int do_bootm_linux(struct image_data *data)

2
arch/arm/mach-at91/Kconfig
View File

@ -18,11 +18,13 @@ choice
config ARCH_AT91SAM9260
bool "AT91SAM9260"
select CPU_ARM926T
select HAS_MACB
config ARCH_AT91SAM9263
bool "AT91SAM9263"
select CPU_ARM926T
select MACH_HAS_LOWLEVEL_INIT
select HAS_MACB
endchoice

6
arch/arm/mach-at91/Makefile
View File

@ -1,7 +1,7 @@
obj-y += clocksource.o gpio.o
obj-y += clock.o gpio.o
obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o
# CPU-specific support
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o

207
arch/arm/mach-at91/at91sam9260.c
View File

@ -2,22 +2,229 @@
#include <gpio.h>
#include <init.h>
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
#include "generic.h"
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9260_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9260_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91SAM9260_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
.name = "adc_clk",
.pmc_mask = 1 << AT91SAM9260_ID_ADC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
.name = "mci_clk",
.pmc_mask = 1 << AT91SAM9260_ID_MCI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91SAM9260_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9260_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9260_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
.name = "ssc_clk",
.pmc_mask = 1 << AT91SAM9260_ID_SSC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9260_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91SAM9260_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9260_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart4_clk = {
.name = "usart4_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart5_clk = {
.name = "usart5_clk",
.pmc_mask = 1 << AT91SAM9260_ID_US5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
.name = "tc3_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
.name = "tc4_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
.name = "tc5_clk",
.pmc_mask = 1 << AT91SAM9260_ID_TC5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&adc_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc_clk,
&udc_clk,
&twi_clk,
&spi0_clk,
&spi1_clk,
&ssc_clk,
&tc0_clk,
&tc1_clk,
&tc2_clk,
&ohci_clk,
&macb_clk,
&isi_clk,
&usart3_clk,
&usart4_clk,
&usart5_clk,
&tc3_clk,
&tc4_clk,
&tc5_clk,
// irq0 .. irq2
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9260_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9260_gpio[] = {
{
.id = AT91SAM9260_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9260_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9260_ID_PIOC,
.offset = AT91_PIOC,
.clock = &pioC_clk,
}
};
static int at91sam9260_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
/* Register the processor-specific clocks */
at91sam9260_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9260_gpio, 3);
return 0;

18
arch/arm/mach-at91/at91sam9260_devices.c
View File

@ -18,6 +18,8 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include "generic.h"
static struct memory_platform_data sram_pdata = {
.name = "sram0",
.flags = DEVFS_RDWR,
@ -107,8 +109,6 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
nand_dev.platform_data = data;
register_device(&nand_dev);
}
@ -233,37 +233,37 @@ void at91_register_uart(unsigned id, unsigned pins)
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
break;
case AT91SAM9260_ID_US0:
configure_usart0_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
break;
case AT91SAM9260_ID_US1:
configure_usart1_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
break;
case AT91SAM9260_ID_US2:
configure_usart2_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
break;
case AT91SAM9260_ID_US3:
configure_usart3_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US3);
at91_clock_associate("usart3_clk", &uart3_serial_device, "usart");
register_device(&uart3_serial_device);
break;
case AT91SAM9260_ID_US4:
configure_usart4_pins();
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US4);
at91_clock_associate("usart4_clk", &uart4_serial_device, "usart");
register_device(&uart4_serial_device);
break;
case AT91SAM9260_ID_US5:
configure_usart5_pins();
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US5);
at91_clock_associate("usart5_clk", &uart5_serial_device, "usart");
register_device(&uart5_serial_device);
break;
default:

217
arch/arm/mach-at91/at91sam9263.c
View File

@ -2,28 +2,245 @@
#include <gpio.h>
#include <init.h>
#include <asm/hardware.h>
#include <mach/at91_pmc.h>
#include "clock.h"
#include "generic.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
.name = "pioCDE_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9263_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
.name = "can_clk",
.pmc_mask = 1 << AT91SAM9263_ID_CAN,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
.name = "ac97_clk",
.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
.name = "macb_clk",
.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9263_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
.name = "2dge_clk",
.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9263_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91SAM9263_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] = {
&pioA_clk,
&pioB_clk,
&pioCDE_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&mmc0_clk,
&mmc1_clk,
&can_clk,
&twi_clk,
&spi0_clk,
&spi1_clk,
&ssc0_clk,
&ssc1_clk,
&ac97_clk,
&tcb_clk,
&pwm_clk,
&macb_clk,
&twodge_clk,
&udc_clk,
&isi_clk,
&lcdc_clk,
&dma_clk,
&ohci_clk,
// irq0 .. irq1
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91sam9263_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91sam9263_gpio[] = {
{
.id = AT91SAM9263_ID_PIOA,
.offset = AT91_PIOA,
.clock = &pioA_clk,
}, {
.id = AT91SAM9263_ID_PIOB,
.offset = AT91_PIOB,
.clock = &pioB_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOC,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOD,
.clock = &pioCDE_clk,
}, {
.id = AT91SAM9263_ID_PIOCDE,
.offset = AT91_PIOE,
.clock = &pioCDE_clk,
}
};
static int at91sam9263_initialize(void)
{
/* Init clock subsystem */
at91_clock_init(AT91_MAIN_CLOCK);
/* Register the processor-specific clocks */
at91sam9263_register_clocks();
/* Register GPIO subsystem */
at91_gpio_init(at91sam9263_gpio, 5);
return 0;

13
arch/arm/mach-at91/at91sam9263_devices.c
View File

@ -18,6 +18,8 @@
#include <mach/gpio.h>
#include <mach/io.h>
#include "generic.h"
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
@ -106,9 +108,6 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (data->det_pin)
at91_set_gpio_input(data->det_pin, 1);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
1 << AT91SAM9263_ID_PIOCDE);
nand_dev.platform_data = data;
register_device(&nand_dev);
}
@ -184,22 +183,22 @@ void at91_register_uart(unsigned id, unsigned pins)
switch (id) {
case 0: /* DBGU */
configure_dbgu_pins();
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
at91_clock_associate("mck", &dbgu_serial_device, "usart");
register_device(&dbgu_serial_device);
break;
case AT91SAM9263_ID_US0:
configure_usart0_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
at91_clock_associate("usart0_clk", &uart0_serial_device, "usart");
register_device(&uart0_serial_device);
break;
case AT91SAM9263_ID_US1:
configure_usart1_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
at91_clock_associate("usart1_clk", &uart1_serial_device, "usart");
register_device(&uart1_serial_device);
break;
case AT91SAM9263_ID_US2:
configure_usart2_pins(pins);
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
at91_clock_associate("usart2_clk", &uart2_serial_device, "usart");
register_device(&uart2_serial_device);
break;
default:

0
arch/arm/mach-at91/clocksource.c → arch/arm/mach-at91/at91sam926x_time.c
View File

718
arch/arm/mach-at91/clock.c Normal file
View File

@ -0,0 +1,718 @@
/*
* linux/arch/arm/mach-at91/clock.c
*
* Copyright (C) 2005 David Brownell
* Copyright (C) 2005 Ivan Kokshaysky
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <common.h>
#include <linux/list.h>
#include <errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <init.h>
#include <mach/hardware.h>
#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
#include "clock.h"
#include "generic.h"
/*
* There's a lot more which can be done with clocks, including cpufreq
* integration, slow clock mode support (for system suspend), letting
* PLLB be used at other rates (on boards that don't need USB), etc.
*/
#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
/*
* Chips have some kind of clocks : group them by functionality
*/
#define cpu_has_utmi() ( cpu_is_at91cap9() \
|| cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45())
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|| cpu_is_at91sam9g45())
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45()))
#define cpu_has_upll() (cpu_is_at91sam9g45())
/* USB host HS & FS */
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
/* USB device FS only */
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45()))
static LIST_HEAD(clocks);
static u32 at91_pllb_usb_init;
/*
* Four primary clock sources: two crystal oscillators (32K, main), and
* two PLLs. PLLA usually runs the master clock; and PLLB must run at
* 48 MHz (unless no USB function clocks are needed). The main clock and
* both PLLs are turned off to run in "slow clock mode" (system suspend).
*/
static struct clk clk32k = {
.name = "clk32k",
.rate_hz = AT91_SLOW_CLOCK,
.users = 1, /* always on */
.id = 0,
.type = CLK_TYPE_PRIMARY,
};
static struct clk main_clk = {
.name = "main",
.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
.id = 1,
.type = CLK_TYPE_PRIMARY,
};
static struct clk plla = {
.name = "plla",
.parent = &main_clk,
.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
.id = 2,
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};
static void pllb_mode(struct clk *clk, int is_on)
{
u32 value;
if (is_on) {
is_on = AT91_PMC_LOCKB;
value = at91_pllb_usb_init;
} else
value = 0;
// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
at91_sys_write(AT91_CKGR_PLLBR, value);
do {
barrier();
} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}
static struct clk pllb = {
.name = "pllb",
.parent = &main_clk,
.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
.mode = pllb_mode,
.id = 3,
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};
static void pmc_sys_mode(struct clk *clk, int is_on)
{
if (is_on)
at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
else
at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
}
static void pmc_uckr_mode(struct clk *clk, int is_on)
{
unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
if (cpu_is_at91sam9g45()) {
if (is_on)
uckr |= AT91_PMC_BIASEN;
else
uckr &= ~AT91_PMC_BIASEN;
}
if (is_on) {
is_on = AT91_PMC_LOCKU;
at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
} else
at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
do {
barrier();
} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
}
/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
.name = "udpck",
.parent = &pllb,
.mode = pmc_sys_mode,
};
static struct clk utmi_clk = {
.name = "utmi_clk",
.parent = &main_clk,
.pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
.mode = pmc_uckr_mode,
.type = CLK_TYPE_PLL,
};
static struct clk uhpck = {
.name = "uhpck",
/*.parent = ... we choose parent at runtime */
.mode = pmc_sys_mode,
};
/*
* The master clock is divided from the CPU clock (by 1-4). It's used for
* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
* (e.g baud rate generation). It's sourced from one of the primary clocks.
*/
static struct clk mck = {
.name = "mck",
.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
};
static void pmc_periph_mode(struct clk *clk, int is_on)
{
if (is_on)
at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
else
at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
}
static struct clk *at91_css_to_clk(unsigned long css)
{
switch (css) {
case AT91_PMC_CSS_SLOW:
return &clk32k;
case AT91_PMC_CSS_MAIN:
return &main_clk;
case AT91_PMC_CSS_PLLA:
return &plla;
case AT91_PMC_CSS_PLLB:
if (cpu_has_upll())
/* CSS_PLLB == CSS_UPLL */
return &utmi_clk;
else if (cpu_has_pllb())
return &pllb;
}
return NULL;
}
/*
* Associate a particular clock with a function (eg, "uart") and device.
* The drivers can then request the same 'function' with several different
* devices and not care about which clock name to use.
*/
void at91_clock_associate(const char *id, struct device_d *dev, const char *func)
{
struct clk *clk = clk_get(NULL, id);
if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
return;
clk->function = func;
clk->dev = dev;
}
/* clocks cannot be de-registered no refcounting necessary */
struct clk *clk_get(struct device_d *dev, const char *id)
{
struct clk *clk;
list_for_each_entry(clk, &clocks, node) {
if (strcmp(id, clk->name) == 0)
return clk;
if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
return clk;
}
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);
static void __clk_enable(struct clk *clk)
{
if (clk->parent)
__clk_enable(clk->parent);
if (clk->users++ == 0 && clk->mode)
clk->mode(clk, 1);
}
int clk_enable(struct clk *clk)
{
__clk_enable(clk);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void __clk_disable(struct clk *clk)
{
BUG_ON(clk->users == 0);
if (--clk->users == 0 && clk->mode)
clk->mode(clk, 0);
if (clk->parent)
__clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
__clk_disable(clk);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long rate;
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
/*------------------------------------------------------------------------*/
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
/*
* For now, only the programmable clocks support reparenting (MCK could
* do this too, with care) or rate changing (the PLLs could do this too,
* ditto MCK but that's more for cpufreq). Drivers may reparent to get
* a better rate match; we don't.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long actual;
unsigned long prev = ULONG_MAX;
if (!clk_is_programmable(clk))
return -EINVAL;
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual > rate)
prev = actual;
if (actual && actual <= rate) {
if ((prev - rate) < (rate - actual)) {
actual = prev;
prescale--;
}
break;
}
actual >>= 1;
}
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long actual;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->users)
return -EBUSY;
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual && actual <= rate) {
u32 pckr;
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
pckr &= AT91_PMC_CSS; /* clock selection */
pckr |= prescale << 2;
at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
clk->rate_hz = actual;
break;
}
actual >>= 1;
}
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
if (clk->users)
return -EBUSY;
if (!clk_is_primary(parent) || !clk_is_programmable(clk))
return -EINVAL;
if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
return -EINVAL;
clk->rate_hz = parent->rate_hz;
clk->parent = parent;
at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
/* establish PCK0..PCKN parentage and rate */
static void init_programmable_clock(struct clk *clk)
{
struct clk *parent;
u32 pckr;
pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
clk->parent = parent;
clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
}
#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
/*------------------------------------------------------------------------*/
/* Register a new clock */
int clk_register(struct clk *clk)
{
if (clk_is_peripheral(clk)) {
clk->parent = &mck;
clk->mode = pmc_periph_mode;
list_add_tail(&clk->node, &clocks);
}
else if (clk_is_sys(clk)) {
clk->parent = &mck;
clk->mode = pmc_sys_mode;
list_add_tail(&clk->node, &clocks);
}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
else if (clk_is_programmable(clk)) {
clk->mode = pmc_sys_mode;
init_programmable_clock(clk);
list_add_tail(&clk->node, &clocks);
}
#endif
return 0;
}
/*------------------------------------------------------------------------*/
static u32 at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
unsigned mul, div;
div = reg & 0xff;
mul = (reg >> 16) & 0x7ff;
if (div && mul) {
freq /= div;
freq *= mul + 1;
} else
freq = 0;
return freq;
}
static u32 at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
else
return freq;
}
static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
/* PLL output max 240 MHz (or 180 MHz per errata) */
if (out_freq > 240000000)
goto fail;
for (i = 1; i < 256; i++) {
int diff1;
unsigned input, mul1;
/*
* PLL input between 1MHz and 32MHz per spec, but lower
* frequences seem necessary in some cases so allow 100K.
* Warning: some newer products need 2MHz min.
*/
input = main_freq / i;
if (cpu_is_at91sam9g20() && input < 2000000)
continue;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
if (cpu_is_at91sam9g20() && mul > 63)
continue;
if (mul1 > 2048)
continue;
if (mul1 < 2)
goto fail;
diff1 = out_freq - input * mul1;
if (diff1 < 0)
diff1 = -diff1;
if (diff > diff1) {
diff = diff1;
div = i;
mul = mul1;
if (diff == 0)
break;
}
}
if (i == 256 && diff > (out_freq >> 5))
goto fail;
return ret | ((mul - 1) << 16) | div;
fail:
return 0;
}
static struct clk *const standard_pmc_clocks[] = {
/* four primary clocks */
&clk32k,
&main_clk,
&plla,
/* MCK */
&mck
};
/* PLLB generated USB full speed clock init */
static void at91_pllb_usbfs_clock_init(unsigned long main_clock)
{
/*
* USB clock init: choose 48 MHz PLLB value,
* disable 48MHz clock during usb peripheral suspend.
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
uhpck.parent = &pllb;
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
if (cpu_is_at91rm9200()) {
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
} else if (cpu_is_at91cap9()) {
uhpck.pmc_mask = AT91CAP9_PMC_UHP;
}
at91_sys_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
}
/* UPLL generated USB full speed clock init */
static void at91_upll_usbfs_clock_init(unsigned long main_clock)
{
/*
* USB clock init: choose 480 MHz from UPLL,
*/
unsigned int usbr = AT91_PMC_USBS_UPLL;
/* Setup divider by 10 to reach 48 MHz */
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
at91_sys_write(AT91_PMC_USB, usbr);
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
uhpck.rate_hz = utmi_clk.parent->rate_hz;
uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
}
static int pll_overclock = 0;
int at91_clock_init(unsigned long main_clock)
{
unsigned tmp, freq, mckr;
int i;
/*
* When the bootloader initialized the main oscillator correctly,
* there's no problem using the cycle counter. But if it didn't,
* or when using oscillator bypass mode, we must be told the speed
* of the main clock.
*/
if (!main_clock) {
do {
tmp = at91_sys_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
if (cpu_has_300M_plla()) {
if (plla.rate_hz > 300000000)
pll_overclock = 1;
} else if (cpu_has_800M_plla()) {
if (plla.rate_hz > 800000000)
pll_overclock = 1;
} else {
if (plla.rate_hz > 209000000)
pll_overclock = 1;
}
if (cpu_is_at91sam9g45()) {
mckr = at91_sys_read(AT91_PMC_MCKR);
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
}
if (!cpu_has_pllb() && cpu_has_upll()) {
/* setup UTMI clock as the fourth primary clock
* (instead of pllb) */
utmi_clk.type |= CLK_TYPE_PRIMARY;
utmi_clk.id = 3;
}
/*
* USB HS clock init
*/
if (cpu_has_utmi()) {
/*
* multiplier is hard-wired to 40
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
*/
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
}
/*
* USB FS clock init
*/
if (cpu_has_pllb())
at91_pllb_usbfs_clock_init(main_clock);
if (cpu_has_upll())
/* assumes that we choose UPLL for USB and not PLLA */
at91_upll_usbfs_clock_init(main_clock);
/*
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
mckr = at91_sys_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
if (cpu_is_at91rm9200()) {
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
} else if (cpu_is_at91sam9g20()) {
mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
if (mckr & AT91_PMC_PDIV)
freq /= 2; /* processor clock division */
} else if (cpu_is_at91sam9g45()) {
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
} else {
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
}
/* Register the PMC's standard clocks */
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
if (cpu_has_pllb())
list_add_tail(&pllb.node, &clocks);
if (cpu_has_uhp())
list_add_tail(&uhpck.node, &clocks);
if (cpu_has_udpfs())
list_add_tail(&udpck.node, &clocks);
if (cpu_has_utmi())
list_add_tail(&utmi_clk.node, &clocks);
/* MCK and CPU clock are "always on" */
clk_enable(&mck);
return 0;
}
static int at91_clock_display(void)
{
if (pll_overclock)
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
printf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
mck.parent->rate_hz / 1000000, (unsigned) mck.rate_hz / 1000000,
(unsigned) main_clk.rate_hz / 1000000,
((unsigned) main_clk.rate_hz % 1000000) / 1000);
return 0;
}
postconsole_initcall(at91_clock_display);
/*
* Several unused clocks may be active. Turn them off.
*/
static int at91_clock_reset(void)
{
unsigned long pcdr = 0;
unsigned long scdr = 0;
struct clk *clk;
list_for_each_entry(clk, &clocks, node) {
if (clk->users > 0)
continue;
if (clk->mode == pmc_periph_mode)
pcdr |= clk->pmc_mask;
if (clk->mode == pmc_sys_mode)
scdr |= clk->pmc_mask;
pr_debug("Clocks: disable unused %s\n", clk->name);
}
at91_sys_write(AT91_PMC_PCDR, pcdr);
at91_sys_write(AT91_PMC_SCDR, scdr);
return 0;
}
late_initcall(at91_clock_reset);

31
arch/arm/mach-at91/clock.h Normal file
View File

@ -0,0 +1,31 @@
/*
* linux/arch/arm/mach-at91/clock.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define CLK_TYPE_PRIMARY 0x1
#define CLK_TYPE_PLL 0x2
#define CLK_TYPE_PROGRAMMABLE 0x4
#define CLK_TYPE_PERIPHERAL 0x8
#define CLK_TYPE_SYSTEM 0x10
struct clk {
struct list_head node;
const char *name; /* unique clock name */
const char *function; /* function of the clock */
struct device_d *dev; /* device associated with function */
unsigned long rate_hz;
struct clk *parent;
u32 pmc_mask;
void (*mode)(struct clk *, int);
unsigned id:3; /* PCK0..4, or 32k/main/a/b */
unsigned type; /* clock type */
u16 users;
};
extern int __init clk_register(struct clk *clk);

14
arch/arm/mach-at91/generic.h Normal file
View File

@ -0,0 +1,14 @@
/*
* linux/arch/arm/mach-at91/generic.h
*
* Copyright (C) 2005 David Brownell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Clocks */
extern int __init at91_clock_init(unsigned long main_clock);
struct device_d;
extern void __init at91_clock_associate(const char *id, struct device_d *dev, const char *func);

3
arch/arm/mach-at91/gpio.c
View File

@ -22,6 +22,7 @@
*/
#include <common.h>
#include <linux/clk.h>
#include <errno.h>
#include <asm/io.h>
#include <mach/gpio.h>
@ -245,6 +246,8 @@ int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
data->regbase = data->offset +
(void __iomem *)AT91_BASE_SYS;
/* enable PIO controller's clock */
clk_enable(data->clock);
/* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
if (last && last->id == data->id)

66
arch/arm/mach-at91/include/mach/at91_dbgu.h Normal file
View File

@ -0,0 +1,66 @@
/*
* arch/arm/mach-at91/include/mach/at91_dbgu.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#ifdef AT91_DBGU
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif /* AT91_DBGU */
/*
* Some AT91 parts that don't have full DEBUG units still support the ID
* and extensions register.
*/
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_SRAMSIZ_1K (1 << 16)
#define AT91_CIDR_SRAMSIZ_2K (2 << 16)
#define AT91_CIDR_SRAMSIZ_112K (4 << 16)
#define AT91_CIDR_SRAMSIZ_4K (5 << 16)
#define AT91_CIDR_SRAMSIZ_80K (6 << 16)
#define AT91_CIDR_SRAMSIZ_160K (7 << 16)
#define AT91_CIDR_SRAMSIZ_8K (8 << 16)
#define AT91_CIDR_SRAMSIZ_16K (9 << 16)
#define AT91_CIDR_SRAMSIZ_32K (10 << 16)
#define AT91_CIDR_SRAMSIZ_64K (11 << 16)
#define AT91_CIDR_SRAMSIZ_128K (12 << 16)
#define AT91_CIDR_SRAMSIZ_256K (13 << 16)
#define AT91_CIDR_SRAMSIZ_96K (14 << 16)
#define AT91_CIDR_SRAMSIZ_512K (15 << 16)
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#endif

39
arch/arm/mach-at91/include/mach/clk.h
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@ -1,39 +0,0 @@
/*
* (C) Copyright 2007
* Stelian Pop <stelian.pop@leadtechdesign.com>
* Lead Tech Design <www.leadtechdesign.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_CLK_H__
#define __ASM_ARM_ARCH_CLK_H__
#include <mach/hardware.h>
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
{
return AT91_MASTER_CLOCK;
}
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
{
return AT91_MASTER_CLOCK;
}
#endif /* __ASM_ARM_ARCH_CLK_H__ */

158
arch/arm/mach-at91/include/mach/cpu.h Normal file
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@ -0,0 +1,158 @@
/*
* arch/arm/mach-at91/include/mach/cpu.h
*
* Copyright (C) 2006 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_CPU_H
#define __ASM_ARCH_CPU_H
#include <mach/hardware.h>
#include <mach/at91_dbgu.h>
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
#define ARCH_ID_AT91SAM9263 0x019607a0
#define ARCH_ID_AT91SAM9G10 0x019903a0
#define ARCH_ID_AT91SAM9G20 0x019905a0
#define ARCH_ID_AT91SAM9RL64 0x019b03a0
#define ARCH_ID_AT91SAM9G45 0x819b05a0
#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */
#define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */
#define ARCH_ID_AT91CAP9 0x039A03A0
#define ARCH_ID_AT91SAM9XE128 0x329973a0
#define ARCH_ID_AT91SAM9XE256 0x329a93a0
#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
#define ARCH_ID_AT572D940HF 0x0e0303e0
#define ARCH_ID_AT91M40800 0x14080044
#define ARCH_ID_AT91R40807 0x44080746
#define ARCH_ID_AT91M40807 0x14080745
#define ARCH_ID_AT91R40008 0x44000840
static inline unsigned long at91_cpu_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
}
static inline unsigned long at91_cpu_fully_identify(void)
{
return at91_sys_read(AT91_DBGU_CIDR);
}
#define ARCH_EXID_AT91SAM9M11 0x00000001
#define ARCH_EXID_AT91SAM9M10 0x00000002
#define ARCH_EXID_AT91SAM9G45 0x00000004
static inline unsigned long at91_exid_identify(void)
{
return at91_sys_read(AT91_DBGU_EXID);
}
#define ARCH_FAMILY_AT91X92 0x09200000
#define ARCH_FAMILY_AT91SAM9 0x01900000
#define ARCH_FAMILY_AT91SAM9XE 0x02900000
static inline unsigned long at91_arch_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH);
}
#ifdef CONFIG_ARCH_AT91CAP9
#include <mach/at91_pmc.h>
#define ARCH_REVISION_CAP9_B 0x399
#define ARCH_REVISION_CAP9_C 0x601
static inline unsigned long at91cap9_rev_identify(void)
{
return (at91_sys_read(AT91_PMC_VER));
}
#endif
#ifdef CONFIG_ARCH_AT91RM9200
#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
#else
#define cpu_is_at91rm9200() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9260
#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE)
#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) || cpu_is_at91sam9xe())
#else
#define cpu_is_at91sam9xe() (0)
#define cpu_is_at91sam9260() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G20
#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
#else
#define cpu_is_at91sam9g20() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9261
#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
#else
#define cpu_is_at91sam9261() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G10
#define cpu_is_at91sam9g10() ((at91_cpu_identify() & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10)
#else
#define cpu_is_at91sam9g10() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9263
#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
#else
#define cpu_is_at91sam9263() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9RL
#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64)
#else
#define cpu_is_at91sam9rl() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9G45
#define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
#define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES)
#else
#define cpu_is_at91sam9g45() (0)
#define cpu_is_at91sam9g45es() (0)
#endif
#ifdef CONFIG_ARCH_AT91CAP9
#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
#define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
#define cpu_is_at91cap9_revC() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_C)
#else
#define cpu_is_at91cap9() (0)
#define cpu_is_at91cap9_revB() (0)
#define cpu_is_at91cap9_revC() (0)
#endif
#ifdef CONFIG_ARCH_AT572D940HF
#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
#else
#define cpu_is_at572d940hf() (0)
#endif
/*
* Since this is ARM, we will never run on any AVR32 CPU. But these
* definitions may reduce clutter in common drivers.
*/
#define cpu_is_at32ap7000() (0)
#endif

1
arch/arm/mach-at91/include/mach/gpio.h
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@ -241,6 +241,7 @@ struct at91_gpio_bank {
struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */
unsigned short id; /* peripheral ID */
unsigned long offset; /* offset from system peripheral base */
struct clk *clock;
};
extern int at91_gpio_init(struct at91_gpio_bank *data, int nr_banks);

1
arch/arm/mach-at91/lowlevel_init.S
View File

@ -26,7 +26,6 @@
* MA 02111-1307 USA
*/
#include <linux/autoconf.h>
#include <config.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>

16
arch/arm/mach-at91rm9200/Kconfig
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@ -1,16 +0,0 @@
if ARCH_AT91RM9200
config ARCH_TEXT_BASE
hex
config BOARDINFO
comment "Atmel AT91RM9200 System-on-Chip"
choice
prompt "AT91RM9200 Board Type"
endchoice
endif

762
arch/arm/mach-at91rm9200/include/mach/AT91RM9200.h
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@ -1,762 +0,0 @@
/*
* (C) Copyright 2003
* AT91RM9200 definitions
* Author : ATMEL AT91 application group
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef AT91RM9200_H
#define AT91RM9200_H
typedef volatile unsigned int AT91_REG; /* Hardware register definition */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */
/******************************************************************************/
typedef struct _AT91S_TC
{
AT91_REG TC_CCR; /* Channel Control Register */
AT91_REG TC_CMR; /* Channel Mode Register */
AT91_REG Reserved0[2]; /* */
AT91_REG TC_CV; /* Counter Value */
AT91_REG TC_RA; /* Register A */
AT91_REG TC_RB; /* Register B */
AT91_REG TC_RC; /* Register C */
AT91_REG TC_SR; /* Status Register */
AT91_REG TC_IER; /* Interrupt Enable Register */
AT91_REG TC_IDR; /* Interrupt Disable Register */
AT91_REG TC_IMR; /* Interrupt Mask Register */
} AT91S_TC, *AT91PS_TC;
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Usart */
/******************************************************************************/
typedef struct _AT91S_USART
{
AT91_REG US_CR; /* Control Register */
AT91_REG US_MR; /* Mode Register */
AT91_REG US_IER; /* Interrupt Enable Register */
AT91_REG US_IDR; /* Interrupt Disable Register */
AT91_REG US_IMR; /* Interrupt Mask Register */
AT91_REG US_CSR; /* Channel Status Register */
AT91_REG US_RHR; /* Receiver Holding Register */
AT91_REG US_THR; /* Transmitter Holding Register */
AT91_REG US_BRGR; /* Baud Rate Generator Register */
AT91_REG US_RTOR; /* Receiver Time-out Register */
AT91_REG US_TTGR; /* Transmitter Time-guard Register */
AT91_REG Reserved0[5]; /* */
AT91_REG US_FIDI; /* FI_DI_Ratio Register */
AT91_REG US_NER; /* Nb Errors Register */
AT91_REG US_XXR; /* XON_XOFF Register */
AT91_REG US_IF; /* IRDA_FILTER Register */
AT91_REG Reserved1[44]; /* */
AT91_REG US_RPR; /* Receive Pointer Register */
AT91_REG US_RCR; /* Receive Counter Register */
AT91_REG US_TPR; /* Transmit Pointer Register */
AT91_REG US_TCR; /* Transmit Counter Register */
AT91_REG US_RNPR; /* Receive Next Pointer Register */
AT91_REG US_RNCR; /* Receive Next Counter Register */
AT91_REG US_TNPR; /* Transmit Next Pointer Register */
AT91_REG US_TNCR; /* Transmit Next Counter Register */
AT91_REG US_PTCR; /* PDC Transfer Control Register */
AT91_REG US_PTSR; /* PDC Transfer Status Register */
} AT91S_USART, *AT91PS_USART;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Clock Generator Controler */
/******************************************************************************/
typedef struct _AT91S_CKGR
{
AT91_REG CKGR_MOR; /* Main Oscillator Register */
AT91_REG CKGR_MCFR; /* Main Clock Frequency Register */
AT91_REG CKGR_PLLAR; /* PLL A Register */
AT91_REG CKGR_PLLBR; /* PLL B Register */
} AT91S_CKGR, *AT91PS_CKGR;
/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) /* (CKGR) Main Oscillator Enable */
#define AT91C_CKGR_OSCTEST ((unsigned int) 0x1 << 1) /* (CKGR) Oscillator Test */
#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) /* (CKGR) Main Oscillator Start-up Time */
/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) /* (CKGR) Main Clock Frequency */
#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) /* (CKGR) Main Clock Ready */
/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
#define AT91C_CKGR_DIVA ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
#define AT91C_CKGR_DIVA_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
#define AT91C_CKGR_PLLACOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL A Counter */
#define AT91C_CKGR_OUTA ((unsigned int) 0x3 << 14) /* (CKGR) PLL A Output Frequency Range */
#define AT91C_CKGR_OUTA_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLA datasheet */
#define AT91C_CKGR_OUTA_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLA datasheet */
#define AT91C_CKGR_OUTA_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLA datasheet */
#define AT91C_CKGR_OUTA_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLA datasheet */
#define AT91C_CKGR_MULA ((unsigned int) 0x7FF << 16) /* (CKGR) PLL A Multiplier */
#define AT91C_CKGR_SRCA ((unsigned int) 0x1 << 29) /* (CKGR) PLL A Source */
/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
#define AT91C_CKGR_DIVB ((unsigned int) 0xFF << 0) /* (CKGR) Divider Selected */
#define AT91C_CKGR_DIVB_0 ((unsigned int) 0x0) /* (CKGR) Divider output is 0 */
#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1) /* (CKGR) Divider is bypassed */
#define AT91C_CKGR_PLLBCOUNT ((unsigned int) 0x3F << 8) /* (CKGR) PLL B Counter */
#define AT91C_CKGR_OUTB ((unsigned int) 0x3 << 14) /* (CKGR) PLL B Output Frequency Range */
#define AT91C_CKGR_OUTB_0 ((unsigned int) 0x0 << 14) /* (CKGR) Please refer to the PLLB datasheet */
#define AT91C_CKGR_OUTB_1 ((unsigned int) 0x1 << 14) /* (CKGR) Please refer to the PLLB datasheet */
#define AT91C_CKGR_OUTB_2 ((unsigned int) 0x2 << 14) /* (CKGR) Please refer to the PLLB datasheet */
#define AT91C_CKGR_OUTB_3 ((unsigned int) 0x3 << 14) /* (CKGR) Please refer to the PLLB datasheet */
#define AT91C_CKGR_MULB ((unsigned int) 0x7FF << 16) /* (CKGR) PLL B Multiplier */
#define AT91C_CKGR_USB_96M ((unsigned int) 0x1 << 28) /* (CKGR) Divider for USB Ports */
#define AT91C_CKGR_USB_PLL ((unsigned int) 0x1 << 29) /* (CKGR) PLL Use */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */
/******************************************************************************/
typedef struct _AT91S_PIO
{
AT91_REG PIO_PER; /* PIO Enable Register */
AT91_REG PIO_PDR; /* PIO Disable Register */
AT91_REG PIO_PSR; /* PIO Status Register */
AT91_REG Reserved0[1]; /* */
AT91_REG PIO_OER; /* Output Enable Register */
AT91_REG PIO_ODR; /* Output Disable Registerr */
AT91_REG PIO_OSR; /* Output Status Register */
AT91_REG Reserved1[1]; /* */
AT91_REG PIO_IFER; /* Input Filter Enable Register */
AT91_REG PIO_IFDR; /* Input Filter Disable Register */
AT91_REG PIO_IFSR; /* Input Filter Status Register */
AT91_REG Reserved2[1]; /* */
AT91_REG PIO_SODR; /* Set Output Data Register */
AT91_REG PIO_CODR; /* Clear Output Data Register */
AT91_REG PIO_ODSR; /* Output Data Status Register */
AT91_REG PIO_PDSR; /* Pin Data Status Register */
AT91_REG PIO_IER; /* Interrupt Enable Register */
AT91_REG PIO_IDR; /* Interrupt Disable Register */
AT91_REG PIO_IMR; /* Interrupt Mask Register */
AT91_REG PIO_ISR; /* Interrupt Status Register */
AT91_REG PIO_MDER; /* Multi-driver Enable Register */
AT91_REG PIO_MDDR; /* Multi-driver Disable Register */
AT91_REG PIO_MDSR; /* Multi-driver Status Register */
AT91_REG Reserved3[1]; /* */
AT91_REG PIO_PPUDR; /* Pull-up Disable Register */
AT91_REG PIO_PPUER; /* Pull-up Enable Register */
AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */
AT91_REG Reserved4[1]; /* */
AT91_REG PIO_ASR; /* Select A Register */
AT91_REG PIO_BSR; /* Select B Register */
AT91_REG PIO_ABSR; /* AB Select Status Register */
AT91_REG Reserved5[9]; /* */
AT91_REG PIO_OWER; /* Output Write Enable Register */
AT91_REG PIO_OWDR; /* Output Write Disable Register */
AT91_REG PIO_OWSR; /* Output Write Status Register */
} AT91S_PIO, *AT91PS_PIO;
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Debug Unit */
/******************************************************************************/
typedef struct _AT91S_DBGU
{
AT91_REG DBGU_CR; /* Control Register */
AT91_REG DBGU_MR; /* Mode Register */
AT91_REG DBGU_IER; /* Interrupt Enable Register */
AT91_REG DBGU_IDR; /* Interrupt Disable Register */
AT91_REG DBGU_IMR; /* Interrupt Mask Register */
AT91_REG DBGU_CSR; /* Channel Status Register */
AT91_REG DBGU_RHR; /* Receiver Holding Register */
AT91_REG DBGU_THR; /* Transmitter Holding Register */
AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */
AT91_REG Reserved0[7]; /* */
AT91_REG DBGU_C1R; /* Chip ID1 Register */
AT91_REG DBGU_C2R; /* Chip ID2 Register */
AT91_REG DBGU_FNTR; /* Force NTRST Register */
AT91_REG Reserved1[45]; /* */
AT91_REG DBGU_RPR; /* Receive Pointer Register */
AT91_REG DBGU_RCR; /* Receive Counter Register */
AT91_REG DBGU_TPR; /* Transmit Pointer Register */
AT91_REG DBGU_TCR; /* Transmit Counter Register */
AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */
AT91_REG DBGU_RNCR; /* Receive Next Counter Register */
AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */
AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */
AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */
AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */
} AT91S_DBGU, *AT91PS_DBGU;
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */
/******************************************************************************/
typedef struct _AT91S_SMC2
{
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */
} AT91S_SMC2, *AT91PS_SMC2;
/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register -------- */
#define AT91C_SMC2_NWS ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
#define AT91C_SMC2_TDF ((unsigned int) 0xF << 8) /* (SMC2) Data Float Time */
#define AT91C_SMC2_BAT ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
#define AT91C_SMC2_DBW ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
#define AT91C_SMC2_DBW_16 ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
#define AT91C_SMC2_DRP ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
#define AT91C_SMC2_ACSS ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
#define AT91C_SMC2_ACSS_1_CYCLE ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
#define AT91C_SMC2_ACSS_2_CYCLES ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
#define AT91C_SMC2_ACSS_3_CYCLES ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
#define AT91C_SMC2_RWSETUP ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
#define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Power Management Controler */
/******************************************************************************/
typedef struct _AT91S_PMC
{
AT91_REG PMC_SCER; /* System Clock Enable Register */
AT91_REG PMC_SCDR; /* System Clock Disable Register */
AT91_REG PMC_SCSR; /* System Clock Status Register */
AT91_REG Reserved0[1]; /* */
AT91_REG PMC_PCER; /* Peripheral Clock Enable Register */
AT91_REG PMC_PCDR; /* Peripheral Clock Disable Register */
AT91_REG PMC_PCSR; /* Peripheral Clock Status Register */
AT91_REG Reserved1[5]; /* */
AT91_REG PMC_MCKR; /* Master Clock Register */
AT91_REG Reserved2[3]; /* */
AT91_REG PMC_PCKR[8]; /* Programmable Clock Register */
AT91_REG PMC_IER; /* Interrupt Enable Register */
AT91_REG PMC_IDR; /* Interrupt Disable Register */
AT91_REG PMC_SR; /* Status Register */
AT91_REG PMC_IMR; /* Interrupt Mask Register */
} AT91S_PMC, *AT91PS_PMC;
/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) /* (PMC) Processor Clock */
#define AT91C_PMC_UDP ((unsigned int) 0x1 << 1) /* (PMC) USB Device Port Clock */
#define AT91C_PMC_MCKUDP ((unsigned int) 0x1 << 2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
#define AT91C_PMC_UHP ((unsigned int) 0x1 << 4) /* (PMC) USB Host Port Clock */
#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK3 ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK4 ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK5 ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK6 ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
#define AT91C_PMC_PCK7 ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) /* (PMC) Programmable Clock Selection */
#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) /* (PMC) Slow Clock is selected */
#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) /* (PMC) Main Clock is selected */
#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2) /* (PMC) Clock from PLL A is selected */
#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3) /* (PMC) Clock from PLL B is selected */
#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) /* (PMC) Programmable Clock Prescaler */
#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) /* (PMC) Selected clock */
#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) /* (PMC) Selected clock divided by 2 */
#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) /* (PMC) Selected clock divided by 4 */
#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) /* (PMC) Selected clock divided by 8 */
#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) /* (PMC) Selected clock divided by 16 */
#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) /* (PMC) Selected clock divided by 32 */
#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) /* (PMC) Selected clock divided by 64 */
#define AT91C_PMC_MDIV ((unsigned int) 0x3 << 8) /* (PMC) Master Clock Division */
#define AT91C_PMC_MDIV_1 ((unsigned int) 0x0 << 8) /* (PMC) The master clock and the processor clock are the same */
#define AT91C_PMC_MDIV_2 ((unsigned int) 0x1 << 8) /* (PMC) The processor clock is twice as fast as the master clock */
#define AT91C_PMC_MDIV_3 ((unsigned int) 0x2 << 8) /* (PMC) The processor clock is three times faster than the master clock */
#define AT91C_PMC_MDIV_4 ((unsigned int) 0x3 << 8) /* (PMC) The processor clock is four times faster than the master clock */
/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) /* (PMC) MOSC Status/Enable/Disable/Mask */
#define AT91C_PMC_LOCKA ((unsigned int) 0x1 << 1) /* (PMC) PLL A Status/Enable/Disable/Mask */
#define AT91C_PMC_LOCKB ((unsigned int) 0x1 << 2) /* (PMC) PLL B Status/Enable/Disable/Mask */
#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK3RDY ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK4RDY ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK5RDY ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK6RDY ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
#define AT91C_PMC_PCK7RDY ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Ethernet MAC */
/******************************************************************************/
typedef struct _AT91S_EMAC
{
AT91_REG EMAC_CTL; /* Network Control Register */
AT91_REG EMAC_CFG; /* Network Configuration Register */
AT91_REG EMAC_SR; /* Network Status Register */
AT91_REG EMAC_TAR; /* Transmit Address Register */
AT91_REG EMAC_TCR; /* Transmit Control Register */
AT91_REG EMAC_TSR; /* Transmit Status Register */
AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */
AT91_REG Reserved0[1]; /* */
AT91_REG EMAC_RSR; /* Receive Status Register */
AT91_REG EMAC_ISR; /* Interrupt Status Register */
AT91_REG EMAC_IER; /* Interrupt Enable Register */
AT91_REG EMAC_IDR; /* Interrupt Disable Register */
AT91_REG EMAC_IMR; /* Interrupt Mask Register */
AT91_REG EMAC_MAN; /* PHY Maintenance Register */
AT91_REG Reserved1[2]; /* */
AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */
AT91_REG EMAC_SCOL; /* Single Collision Frame Register */
AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */
AT91_REG EMAC_OK; /* Frames Received OK Register */
AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */
AT91_REG EMAC_ALE; /* Alignment Error Register */
AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */
AT91_REG EMAC_LCOL; /* Late Collision Register */
AT91_REG EMAC_ECOL; /* Excessive Collision Register */
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */
AT91_REG EMAC_CDE; /* Code Error Register */
AT91_REG EMAC_ELR; /* Excessive Length Error Register */
AT91_REG EMAC_RJB; /* Receive Jabber Register */
AT91_REG EMAC_USF; /* Undersize Frame Register */
AT91_REG EMAC_SQEE; /* SQE Test Error Register */
AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */
AT91_REG Reserved2[3]; /* */
AT91_REG EMAC_HSH; /* Hash Address High[63:32] */
AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */
AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */
AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */
AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */
AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */
AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */
AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */
AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */
AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */
} AT91S_EMAC, *AT91PS_EMAC;
/* -------- EMAC_CTL : (EMAC Offset: 0x0) -------- */
#define AT91C_EMAC_LB ((unsigned int) 0x1 << 0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
#define AT91C_EMAC_LBL ((unsigned int) 0x1 << 1) /* (EMAC) Loopback local. */
#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */
#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */
#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */
#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */
#define AT91C_EMAC_ISR ((unsigned int) 0x1 << 6) /* (EMAC) Increment statistics registers. */
#define AT91C_EMAC_WES ((unsigned int) 0x1 << 7) /* (EMAC) Write enable for statistics registers. */
#define AT91C_EMAC_BP ((unsigned int) 0x1 << 8) /* (EMAC) Back pressure. */
/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register -------- */
#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */
#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */
#define AT91C_EMAC_BR ((unsigned int) 0x1 << 2) /* (EMAC) Bit rate. */
#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */
#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */
#define AT91C_EMAC_MTI ((unsigned int) 0x1 << 6) /* (EMAC) Multicast hash enable */
#define AT91C_EMAC_UNI ((unsigned int) 0x1 << 7) /* (EMAC) Unicast hash enable. */
#define AT91C_EMAC_BIG ((unsigned int) 0x1 << 8) /* (EMAC) Receive 1522 bytes. */
#define AT91C_EMAC_EAE ((unsigned int) 0x1 << 9) /* (EMAC) External address match enable. */
#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */
#define AT91C_EMAC_CLK_HCLK_8 ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
#define AT91C_EMAC_RTY ((unsigned int) 0x1 << 12) /* (EMAC) */
#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */
/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register -------- */
#define AT91C_EMAC_MDIO ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_IDLE ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register -------- */
#define AT91C_EMAC_LEN ((unsigned int) 0x7FF << 0) /* (EMAC) */
#define AT91C_EMAC_NCRC ((unsigned int) 0x1 << 15) /* (EMAC) */
/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register -------- */
#define AT91C_EMAC_OVR ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_COL ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RLE ((unsigned int) 0x1 << 2) /* (EMAC) */
#define AT91C_EMAC_TXIDLE ((unsigned int) 0x1 << 3) /* (EMAC) */
#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */
#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */
#define AT91C_EMAC_UND ((unsigned int) 0x1 << 6) /* (EMAC) */
/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */
/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- */
#define AT91C_EMAC_DONE ((unsigned int) 0x1 << 0) /* (EMAC) */
#define AT91C_EMAC_RCOM ((unsigned int) 0x1 << 1) /* (EMAC) */
#define AT91C_EMAC_RBNA ((unsigned int) 0x1 << 2) /* (EMAC) */
#define AT91C_EMAC_TOVR ((unsigned int) 0x1 << 3) /* (EMAC) */
#define AT91C_EMAC_TUND ((unsigned int) 0x1 << 4) /* (EMAC) */
#define AT91C_EMAC_RTRY ((unsigned int) 0x1 << 5) /* (EMAC) */
#define AT91C_EMAC_TBRE ((unsigned int) 0x1 << 6) /* (EMAC) */
#define AT91C_EMAC_TCOM ((unsigned int) 0x1 << 7) /* (EMAC) */
#define AT91C_EMAC_TIDLE ((unsigned int) 0x1 << 8) /* (EMAC) */
#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 9) /* (EMAC) */
#define AT91C_EMAC_ROVR ((unsigned int) 0x1 << 10) /* (EMAC) */
#define AT91C_EMAC_HRESP ((unsigned int) 0x1 << 11) /* (EMAC) */
/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- */
/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- */
/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
#define AT91C_EMAC_DATA ((unsigned int) 0xFFFF << 0) /* (EMAC) */
#define AT91C_EMAC_CODE ((unsigned int) 0x3 << 16) /* (EMAC) */
#define AT91C_EMAC_CODE_802_3 ((unsigned int) 0x2 << 16) /* (EMAC) Write Operation */
#define AT91C_EMAC_REGA ((unsigned int) 0x1F << 18) /* (EMAC) */
#define AT91C_EMAC_PHYA ((unsigned int) 0x1F << 23) /* (EMAC) */
#define AT91C_EMAC_RW ((unsigned int) 0x3 << 28) /* (EMAC) */
#define AT91C_EMAC_RW_R ((unsigned int) 0x2 << 28) /* (EMAC) Read Operation */
#define AT91C_EMAC_RW_W ((unsigned int) 0x1 << 28) /* (EMAC) Write Operation */
#define AT91C_EMAC_HIGH ((unsigned int) 0x1 << 30) /* (EMAC) */
#define AT91C_EMAC_LOW ((unsigned int) 0x1 << 31) /* (EMAC) */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Serial Parallel Interface */
/******************************************************************************/
typedef struct _AT91S_SPI
{
AT91_REG SPI_CR; /* Control Register */
AT91_REG SPI_MR; /* Mode Register */
AT91_REG SPI_RDR; /* Receive Data Register */
AT91_REG SPI_TDR; /* Transmit Data Register */
AT91_REG SPI_SR; /* Status Register */
AT91_REG SPI_IER; /* Interrupt Enable Register */
AT91_REG SPI_IDR; /* Interrupt Disable Register */
AT91_REG SPI_IMR; /* Interrupt Mask Register */
AT91_REG Reserved0[4]; /* */
AT91_REG SPI_CSR[4]; /* Chip Select Register */
AT91_REG Reserved1[48]; /* */
AT91_REG SPI_RPR; /* Receive Pointer Register */
AT91_REG SPI_RCR; /* Receive Counter Register */
AT91_REG SPI_TPR; /* Transmit Pointer Register */
AT91_REG SPI_TCR; /* Transmit Counter Register */
AT91_REG SPI_RNPR; /* Receive Next Pointer Register */
AT91_REG SPI_RNCR; /* Receive Next Counter Register */
AT91_REG SPI_TNPR; /* Transmit Next Pointer Register */
AT91_REG SPI_TNCR; /* Transmit Next Counter Register */
AT91_REG SPI_PTCR; /* PDC Transfer Control Register */
AT91_REG SPI_PTSR; /* PDC Transfer Status Register */
} AT91S_SPI, *AT91PS_SPI;
/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) /* (SPI) SPI Enable */
#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) /* (SPI) SPI Disable */
#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) /* (SPI) SPI Software reset */
/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) /* (SPI) Master/Slave Mode */
#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) /* (SPI) Peripheral Select */
#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) /* (SPI) Fixed Peripheral Select */
#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) /* (SPI) Variable Peripheral Select */
#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) /* (SPI) Chip Select Decode */
#define AT91C_SPI_DIV32 ((unsigned int) 0x1 << 3) /* (SPI) Clock Selection */
#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) /* (SPI) Mode Fault Detection */
#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) /* (SPI) Clock Selection */
#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) /* (SPI) Receive Data */
#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) /* (SPI) Transmit Data */
#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) /* (SPI) Receive Data Register Full */
#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) /* (SPI) Transmit Data Register Empty */
#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) /* (SPI) Mode Fault Error */
#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) /* (SPI) Overrun Error Status */
#define AT91C_SPI_SPENDRX ((unsigned int) 0x1 << 4) /* (SPI) End of Receiver Transfer */
#define AT91C_SPI_SPENDTX ((unsigned int) 0x1 << 5) /* (SPI) End of Receiver Transfer */
#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) /* (SPI) RXBUFF Interrupt */
#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) /* (SPI) TXBUFE Interrupt */
#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */
/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) /* (SPI) Clock Polarity */
#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) /* (SPI) Clock Phase */
#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) /* (SPI) Bits Per Transfer */
#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) /* (SPI) 8 Bits Per transfer */
#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) /* (SPI) 9 Bits Per transfer */
#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) /* (SPI) 10 Bits Per transfer */
#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) /* (SPI) 11 Bits Per transfer */
#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) /* (SPI) 12 Bits Per transfer */
#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) /* (SPI) 13 Bits Per transfer */
#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) /* (SPI) 14 Bits Per transfer */
#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) /* (SPI) 15 Bits Per transfer */
#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) /* (SPI) 16 Bits Per transfer */
#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
/******************************************************************************/
/* SOFTWARE API DEFINITION FOR Peripheral Data Controller */
/******************************************************************************/
typedef struct _AT91S_PDC
{
AT91_REG PDC_RPR; /* Receive Pointer Register */
AT91_REG PDC_RCR; /* Receive Counter Register */
AT91_REG PDC_TPR; /* Transmit Pointer Register */
AT91_REG PDC_TCR; /* Transmit Counter Register */
AT91_REG PDC_RNPR; /* Receive Next Pointer Register */
AT91_REG PDC_RNCR; /* Receive Next Counter Register */
AT91_REG PDC_TNPR; /* Transmit Next Pointer Register */
AT91_REG PDC_TNCR; /* Transmit Next Counter Register */
AT91_REG PDC_PTCR; /* PDC Transfer Control Register */
AT91_REG PDC_PTSR; /* PDC Transfer Status Register */
} AT91S_PDC, *AT91PS_PDC;
/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) /* (PDC) Receiver Transfer Enable */
#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) /* (PDC) Receiver Transfer Disable */
#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) /* (PDC) Transmitter Transfer Enable */
#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) /* (PDC) Transmitter Transfer Disable */
/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- */
/* ========== Register definition ==================================== */
#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) /* (SPI) Chip Select Register */
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) /* (PIOA) PIO Enable Register */
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */
#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) /* (PIOA) PIO Status Register */
#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) /* (PIOA) PIO Output Enable Register */
#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) /* (PIOA) PIO Output Disable Register */
#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) /* (PIOA) PIO Output Status Register */
#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
#define AT91C_PIOA_PUDR ((AT91_REG *) 0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
#define AT91C_PIOA_PUER ((AT91_REG *) 0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
#define AT91C_PIOA_PUSR ((AT91_REG *) 0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */
#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */
#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */
#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */
#define AT91C_PA25_TWD ((unsigned int) 1 << 25)
#define AT91C_PA26_TWCK ((unsigned int) 1 << 26)
#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) /* Pin Controlled by PA17 */
#define AT91C_PA17_TXD0 AT91C_PIO_PA17 /* USART0 Transmit Data */
#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) /* Pin Controlled by PA18 */
#define AT91C_PA18_RXD0 AT91C_PIO_PA18 /* USART0 Receive Data */
#define AT91C_PIO_PB20 ((unsigned int) 1 << 20) /* Pin Controlled by PB20 */
#define AT91C_PB20_RXD1 AT91C_PIO_PB20 /* USART1 Receive Data */
#define AT91C_PIO_PB21 ((unsigned int) 1 << 21) /* Pin Controlled by PB21 */
#define AT91C_PB21_TXD1 AT91C_PIO_PB21 /* USART1 Transmit Data */
#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */
#define AT91C_ID_PIOA ((unsigned int) 2) /* PIO port A */
#define AT91C_ID_PIOB ((unsigned int) 3) /* PIO port B */
#define AT91C_ID_PIOC ((unsigned int) 4) /* PIO port C */
#define AT91C_ID_USART0 ((unsigned int) 6) /* USART 0 */
#define AT91C_ID_USART1 ((unsigned int) 7) /* USART 1 */
#define AT91C_ID_TWI ((unsigned int) 12) /* Two Wire Interface */
#define AT91C_ID_SPI ((unsigned int) 13) /* Serial Peripheral Interface */
#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */
#define AT91C_ID_UHP ((unsigned int) 23) /* OHCI USB Host Port */
#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */
#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */
#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */
#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */
#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */
#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */
#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */
#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */
#define AT91C_PA23_TXD2 ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */
#define AT91C_PA0_MISO ((unsigned int) AT91C_PIO_PA0) /* SPI Master In Slave */
#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */
#define AT91C_PA1_MOSI ((unsigned int) AT91C_PIO_PA1) /* SPI Master Out Slave */
#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */
#define AT91C_PA2_SPCK ((unsigned int) AT91C_PIO_PA2) /* SPI Serial Clock */
#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) /* Pin Controlled by PA3 */
#define AT91C_PA3_NPCS0 ((unsigned int) AT91C_PIO_PA3) /* SPI Peripheral Chip Select 0 */
#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */
#define AT91C_PA4_NPCS1 ((unsigned int) AT91C_PIO_PA4) /* SPI Peripheral Chip Select 1 */
#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */
#define AT91C_PA5_NPCS2 ((unsigned int) AT91C_PIO_PA5) /* SPI Peripheral Chip Select 2 */
#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */
#define AT91C_PA6_NPCS3 ((unsigned int) AT91C_PIO_PA6) /* SPI Peripheral Chip Select 3 */
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */
#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */
#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */
#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */
#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */
#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */
#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */
#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */
#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */
#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */
#define AT91C_PIO_PB3 ((unsigned int) 1 << 3) /* Pin Controlled by PB3 */
#define AT91C_PIO_PB4 ((unsigned int) 1 << 4) /* Pin Controlled by PB4 */
#define AT91C_PIO_PB5 ((unsigned int) 1 << 5) /* Pin Controlled by PB5 */
#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */
#define AT91C_PIO_PB7 ((unsigned int) 1 << 7) /* Pin Controlled by PB7 */
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */
#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */
#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */
#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */
#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */
#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */
#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */
#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */
#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */
#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */
#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */
#define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */
#define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */
#define AT91C_PIOC_PDSR ((AT91_REG *) 0xFFFFF83C) /* (PIOC) Pin Data Status Register */
#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) /* (SPI) Base Address */
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */
#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) /* (CKGR) Base Address */
#define AT91C_BASE_PIOC ((AT91PS_PIO) 0xFFFFF800) /* (PIOC) Base Address */
#define AT91C_BASE_PIOB ((AT91PS_PIO) 0xFFFFF600) /* (PIOB) Base Address */
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */
#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */
#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */
#endif

78
arch/arm/mach-at91rm9200/include/mach/hardware.h
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@ -1,78 +0,0 @@
/*
* linux/include/asm-arm/arch-at91/hardware.h
*
* Copyright (C) 2003 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <sizes.h>
#ifndef __ASSEMBLY__
#include "AT91RM9200.h"
#else
#include "AT91RM9200_inc.h"
#endif
/* Virtual and Physical base address for system peripherals */
#define AT91_SYS_BASE 0xFFFFF000 /*4K */
/* Virtual and Physical base addresses of user peripherals */
#define AT91_SPI_BASE 0xFFFE0000 /*16K */
#define AT91_SSC2_BASE 0xFFFD8000 /*16K */
#define AT91_SSC1_BASE 0xFFFD4000 /*16K */
#define AT91_SSC0_BASE 0xFFFD0000 /*16K */
#define AT91_USART3_BASE 0xFFFCC000 /*16K */
#define AT91_USART2_BASE 0xFFFC8000 /*16K */
#define AT91_USART1_BASE 0xFFFC4000 /*16K */
#define AT91_USART0_BASE 0xFFFC0000 /*16K */
#define AT91_EMAC_BASE 0xFFFBC000 /*16K */
#define AT91_TWI_BASE 0xFFFB8000 /*16K */
#define AT91_MCI_BASE 0xFFFB4000 /*16K */
#define AT91_UDP_BASE 0xFFFB0000 /*16K */
#define AT91_TCB1_BASE 0xFFFA4000 /*16K */
#define AT91_TCB0_BASE 0xFFFA0000 /*16K */
#define AT91_USB_HOST_BASE 0x00300000
#define CFG_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
/*
* Where in virtual memory the IO devices (timers, system controllers
* and so on)
*/
#define AT91_IO_BASE 0xF0000000 /* Virt/Phys Address of IO */
/* FLASH */
#define AT91_FLASH_BASE 0x10000000 /* NCS0 */
/* SDRAM */
#define AT91_SDRAM_BASE 0x20000000 /* NCS1 */
/* SmartMedia */
#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3 */
/* Definition of interrupt priority levels */
#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
#endif

18
arch/arm/mach-imx/Kconfig
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@ -356,6 +356,24 @@ config IMX_CLKO
The i.MX SoCs have a Pin which can output different reference frequencies.
Say y here if you want to have the clko command which lets you select the
frequency to output on this pin.
config IMX_IIM
tristate "IIM fusebox device"
depends on ARCH_IMX25 || ARCH_IMX35
help
Device driver for the IC Identification Module (IIM) fusebox. Use the
regular md/mw commands to program and read the fusebox.
config IMX_IIM_FUSE_BLOW
bool "IIM fuses blow support"
depends on IMX_IIM
help
Enable this option to add permanent programming of the fusebox, using
fuses blowing.
Warning: blown fuses can not be unblown. Using this option may damage
your CPU, or make it unbootalbe. Use with care.
endmenu
endif

1
arch/arm/mach-imx/Makefile
View File

@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o
obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o
obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o
obj-$(CONFIG_IMX_CLKO) += clko.o
obj-$(CONFIG_IMX_IIM) += iim.o
obj-$(CONFIG_NAND_IMX) += nand.o
obj-y += speed.o

311
arch/arm/mach-imx/iim.c Normal file
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@ -0,0 +1,311 @@
/*
* iim.c - i.MX IIM fusebox driver
*
* Provide an interface for programming and sensing the information that are
* stored in on-chip fuse elements. This functionality is part of the IC
* Identification Module (IIM), which is present on some i.MX CPUs.
*
* Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
* Orex Computed Radiography
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
#include <init.h>
#include <driver.h>
#include <xfuncs.h>
#include <errno.h>
#include <param.h>
#include <asm/io.h>
#include <mach/iim.h>
#define DRIVERNAME "imx_iim"
static unsigned long mac_addr_base;
static int do_fuse_sense(unsigned long reg_base, unsigned int bank,
unsigned int row)
{
u8 err, stat;
if (bank > 7) {
printf("%s: invalid bank number\n", __func__);
return -EINVAL;
}
if (row > 0x3ff) {
printf("%s: invalid row offset\n", __func__);
return -EINVAL;
}
/* clear status and error registers */
writeb(3, reg_base + IIM_STATM);
writeb(0xfe, reg_base + IIM_ERR);
/* upper and lower address halves */
writeb((bank << 3) | (row >> 7), reg_base + IIM_UA);
writeb((row << 1) & 0xf8, reg_base + IIM_LA);
/* start fuse sensing */
writeb(0x08, reg_base + IIM_FCTL);
/* wait for sense done */
while ((readb(reg_base + IIM_STAT) & 0x80) != 0)
;
stat = readb(reg_base + IIM_STAT);
writeb(stat, reg_base + IIM_STAT);
err = readb(reg_base + IIM_ERR);
if (err) {
printf("%s: sense error (0x%02x)\n", __func__, err);
return -EIO;
}
return readb(reg_base + IIM_SDAT);
}
static ssize_t imx_iim_read(struct cdev *cdev, void *buf, size_t count,
ulong offset, ulong flags)
{
ulong size, i;
struct device_d *dev = cdev->dev;
const char *sense_param;
unsigned long explicit_sense = 0;
if (dev == NULL)
return -EINVAL;
if ((sense_param = dev_get_param(dev, "explicit_sense_enable")))
explicit_sense = simple_strtoul(sense_param, NULL, 0);
size = min((ulong)count, dev->size - offset);
if (explicit_sense) {
for (i = 0; i < size; i++) {
int row_val;
row_val = do_fuse_sense(dev->parent->map_base,
dev->id, (offset+i)*4);
if (row_val < 0)
return row_val;
((u8 *)buf)[i] = (u8)row_val;
}
} else {
for (i = 0; i < size; i++)
((u8 *)buf)[i] = ((u8 *)dev->map_base)[(offset+i)*4];
}
return size;
}
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
static int do_fuse_blow(unsigned long reg_base, unsigned int bank,
unsigned int row, u8 value)
{
int bit, ret = 0;
u8 err, stat;
if (bank > 7) {
printf("%s: invalid bank number\n", __func__);
return -EINVAL;
}
if (row > 0x3ff) {
printf("%s: invalid row offset\n", __func__);
return -EINVAL;
}
/* clear status and error registers */
writeb(3, reg_base + IIM_STATM);
writeb(0xfe, reg_base + IIM_ERR);
/* unprotect fuse programing */
writeb(0xaa, reg_base + IIM_PREG_P);
/* upper half address register */
writeb((bank << 3) | (row >> 7), reg_base + IIM_UA);
for (bit = 0; bit < 8; bit++) {
if (((value >> bit) & 1) == 0)
continue;
/* lower half address register */
writeb(((row << 1) | bit), reg_base + IIM_LA);
/* start fuse programing */
writeb(0x71, reg_base + IIM_FCTL);
/* wait for program done */
while ((readb(reg_base + IIM_STAT) & 0x80) != 0)
;
/* clear program done status */
stat = readb(reg_base + IIM_STAT);
writeb(stat, reg_base + IIM_STAT);
err = readb(reg_base + IIM_ERR);
if (err) {
printf("%s: bank %u, row %u, bit %d program error "
"(0x%02x)\n", __func__, bank, row, bit,
err);
ret = -EIO;
goto out;
}
}
out:
/* protect fuse programing */
writeb(0, reg_base + IIM_PREG_P);
return ret;
}
#endif /* CONFIG_IMX_IIM_FUSE_BLOW */
static ssize_t imx_iim_write(struct cdev *cdev, const void *buf, size_t count,
ulong offset, ulong flags)
{
ulong size, i;
struct device_d *dev = cdev->dev;
const char *write_param;
unsigned int blow_enable = 0;
if (dev == NULL)
return -EINVAL;
if ((write_param = dev_get_param(dev, "permanent_write_enable")))
blow_enable = simple_strtoul(write_param, NULL, 0);
size = min((ulong)count, dev->size - offset);
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
if (blow_enable) {
for (i = 0; i < size; i++) {
int ret;
ret = do_fuse_blow(dev->parent->map_base, dev->id,
(offset+i)*4, ((u8 *)buf)[i]);
if (ret < 0)
return ret;
}
} else
#endif /* CONFIG_IMX_IIM_FUSE_BLOW */
{
for (i = 0; i < size; i++)
((u8 *)dev->map_base)[(offset+i)*4] = ((u8 *)buf)[i];
}
return size;
}
static struct file_operations imx_iim_ops = {
.read = imx_iim_read,
.write = imx_iim_write,
.lseek = dev_lseek_default,
};
static int imx_iim_blow_enable_set(struct device_d *dev, struct param_d *param,
const char *val)
{
unsigned long blow_enable;
if (val == NULL)
return -EINVAL;
blow_enable = simple_strtoul(val, NULL, 0);
if (blow_enable > 1)
return -EINVAL;
return dev_param_set_generic(dev, param, blow_enable ? "1" : "0");
}
static int imx_iim_probe(struct device_d *dev)
{
struct imx_iim_platform_data *pdata = dev->platform_data;
if (pdata)
mac_addr_base = pdata->mac_addr_base;
return 0;
}
static int imx_iim_bank_probe(struct device_d *dev)
{
struct cdev *cdev;
struct device_d *parent;
int err;
cdev = xzalloc(sizeof (struct cdev));
dev->priv = cdev;
cdev->dev = dev;
cdev->ops = &imx_iim_ops;
cdev->size = dev->size;
cdev->name = asprintf(DRIVERNAME "_bank%d", dev->id);
if (cdev->name == NULL)
return -ENOMEM;
parent = get_device_by_name(DRIVERNAME "0");
if (parent == NULL)
return -ENODEV;
err = dev_add_child(parent, dev);
if (err < 0)
return err;
#ifdef CONFIG_IMX_IIM_FUSE_BLOW
err = dev_add_param(dev, "permanent_write_enable",
imx_iim_blow_enable_set, NULL, 0);
if (err < 0)
return err;
err = dev_set_param(dev, "permanent_write_enable", "0");
if (err < 0)
return err;
#endif /* CONFIG_IMX_IIM_FUSE_BLOW */
err = dev_add_param(dev, "explicit_sense_enable",
imx_iim_blow_enable_set, NULL, 0);
if (err < 0)
return err;
err = dev_set_param(dev, "explicit_sense_enable", "0");
if (err < 0)
return err;
return devfs_create(cdev);
}
static struct driver_d imx_iim_driver = {
.name = DRIVERNAME,
.probe = imx_iim_probe,
};
static struct driver_d imx_iim_bank_driver = {
.name = DRIVERNAME "_bank",
.probe = imx_iim_bank_probe,
};
static int imx_iim_init(void)
{
register_driver(&imx_iim_driver);
register_driver(&imx_iim_bank_driver);
return 0;
}
coredevice_initcall(imx_iim_init);
int imx_iim_get_mac(unsigned char *mac)
{
int i;
if (mac_addr_base == 0)
return -EINVAL;
for (i = 0; i < 6; i++)
mac[i] = readb(mac_addr_base + i*4);
return 0;
}

62
arch/arm/mach-imx/imx25.c
View File

@ -16,6 +16,10 @@
*/
#include <common.h>
#include <init.h>
#include <mach/imx-regs.h>
#include <mach/iim.h>
#include <asm/io.h>
#include "gpio.h"
@ -28,3 +32,61 @@ void *imx_gpio_base[] = {
int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32;
u64 imx_uid(void)
{
u64 uid = 0;
int i;
/*
* This code assumes that the UID is stored little-endian. The
* Freescale AN3682 document is silent about the endianess, but
* experimentation shows that this is the case. All other multi-byte
* values in IIM are big-endian as per AN3682.
*/
for (i = 0; i < 8; i++)
uid |= (u64)readb(IIM_UID + i*4) << (i*8);
return uid;
}
static struct imx_iim_platform_data imx25_iim_pdata = {
.mac_addr_base = IIM_MAC_ADDR,
};
static struct device_d imx25_iim_dev = {
.name = "imx_iim",
.map_base = IMX_IIM_BASE,
.platform_data = &imx25_iim_pdata,
};
static struct device_d imx25_iim_bank0_dev = {
.name = "imx_iim_bank",
.id = 0,
.map_base = IIM_BANK0_BASE,
.size = IIM_BANK_SIZE,
};
static struct device_d imx25_iim_bank1_dev = {
.name = "imx_iim_bank",
.id = 1,
.map_base = IIM_BANK1_BASE,
.size = IIM_BANK_SIZE,
};
static struct device_d imx25_iim_bank2_dev = {
.name = "imx_iim_bank",
.id = 2,
.map_base = IIM_BANK2_BASE,
.size = IIM_BANK_SIZE,
};
static int imx25_iim_init(void)
{
register_device(&imx25_iim_dev);
register_device(&imx25_iim_bank0_dev);
register_device(&imx25_iim_bank1_dev);
register_device(&imx25_iim_bank2_dev);
return 0;
}
coredevice_initcall(imx25_iim_init);

1
arch/arm/mach-imx/imx35.c
View File

@ -18,6 +18,7 @@
#include <common.h>
#include <asm/io.h>
#include <mach/imx-regs.h>
#include <mach/iim.h>
#include <mach/generic.h>
#include "gpio.h"

1
arch/arm/mach-imx/include/mach/generic.h
View File

@ -6,6 +6,7 @@ int imx_silicon_revision(void);
#define IMX35_CHIP_REVISION_1_0 0x10
#define IMX35_CHIP_REVISION_2_0 0x20
u64 imx_uid(void);
#ifdef CONFIG_ARCH_IMX1

57
arch/arm/mach-imx/include/mach/iim.h Normal file
View File

@ -0,0 +1,57 @@
/*
* (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MACH_IMX_IIM_H
#define __MACH_IMX_IIM_H
#include <errno.h>
#define IIM_STAT 0x0000
#define IIM_STATM 0x0004
#define IIM_ERR 0x0008
#define IIM_EMASK 0x000C
#define IIM_FCTL 0x0010
#define IIM_UA 0x0014
#define IIM_LA 0x0018
#define IIM_SDAT 0x001C
#define IIM_PREV 0x0020
#define IIM_SREV 0x0024
#define IIM_PREG_P 0x0028
#define IIM_SCS0 0x002C
#define IIM_SCS1 0x0030
#define IIM_SCS2 0x0034
#define IIM_SCS3 0x0038
struct imx_iim_platform_data {
unsigned long mac_addr_base;
};
#ifdef CONFIG_IMX_IIM
int imx_iim_get_mac(unsigned char *mac);
#else
static inline int imx_iim_get_mac(unsigned char *mac)
{
return -EINVAL;
}
#endif /* CONFIG_IMX_IIM */
#endif /* __MACH_IMX_IIM_H */

9
arch/arm/mach-imx/include/mach/imx25-regs.h
View File

@ -140,5 +140,14 @@
/* important definition of some bits of WCR */
#define WCR_WDE 0x04
/* IIM fuse definitions */
#define IIM_BANK_SIZE 32 /* excluding alignment padding for each row */
#define IIM_BANK0_BASE (IMX_IIM_BASE + 0x800)
#define IIM_BANK1_BASE (IMX_IIM_BASE + 0xc00)
#define IIM_BANK2_BASE (IMX_IIM_BASE + 0x1000)
#define IIM_UID (IIM_BANK0_BASE + 0x20)
#define IIM_MAC_ADDR (IIM_BANK0_BASE + 0x68)
#endif /* __ASM_ARCH_MX25_REGS_H */

18
arch/arm/mach-imx/include/mach/imx35-regs.h
View File

@ -76,24 +76,6 @@
#define PDR0_AUTO_CON (1 << 0)
#define PDR0_PER_SEL (1 << 26)
#define IIM_STAT 0x0000
#define IIM_STATM 0x0004
#define IIM_ERR 0x0008
#define IIM_EMASK 0x000C
#define IIM_FCTL 0x0010
#define IIM_UA 0x0014
#define IIM_LA 0x0018
#define IIM_SDAT 0x001C
#define IIM_PREV 0x0020
#define IIM_SREV 0x0024
#define IIM_PREG_P 0x0028
#define IIM_SCS0 0x002C
#define IIM_SCS1 0x0030
#define IIM_SCS2 0x0034
#define IIM_SCS3 0x0038
/*
* Adresses and ranges of the external chip select lines
*/

76
arch/arm/mach-nomadik/8815.c Normal file
View File

@ -0,0 +1,76 @@
/*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <init.h>
#include <asm/hardware.h>
#include <mach/hardware.h>
#include <asm/armlinux.h>
#include <asm/mach-types.h>
#include "clock.h"
static struct clk st8815_clk_48 = {
.rate = 48 * 1000 * 1000,
};
static struct memory_platform_data ram_pdata = {
.name = "ram0",
.flags = DEVFS_RDWR,
};
static struct device_d sdram_dev = {
.name = "mem",
.map_base = 0x00000000,
.platform_data = &ram_pdata,
};
void st8815_add_device_sdram(u32 size)
{
sdram_dev.size = size;
register_device(&sdram_dev);
armlinux_add_dram(&sdram_dev);
}
static struct device_d uart0_serial_device = {
.name = "uart-pl011",
.map_base = NOMADIK_UART0_BASE,
.size = 4096,
};
static struct device_d uart1_serial_device = {
.name = "uart-pl011",
.map_base = NOMADIK_UART1_BASE,
.size = 4096,
};
void st8815_register_uart(unsigned id)
{
switch (id) {
case 0:
nmdk_clk_create(&st8815_clk_48, uart0_serial_device.name);
register_device(&uart0_serial_device);
break;
case 1:
nmdk_clk_create(&st8815_clk_48, uart1_serial_device.name);
register_device(&uart1_serial_device);
break;
}
}

24
arch/arm/mach-nomadik/Kconfig Normal file
View File

@ -0,0 +1,24 @@
if ARCH_NOMADIK
config ARCH_TEXT_BASE
hex
default 0x03c00000 if MACH_NOMADIK_8815NHK
config BOARDINFO
default "NHK8815" if MACH_NOMADIK_8815NHK
choice
prompt "Nomadik boards"
config MACH_NOMADIK_8815NHK
bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
select NOMADIK_8815
select COMMON_CLKDEV
endchoice
config NOMADIK_8815
bool
select ARM_AMBA
endif

3
arch/arm/mach-nomadik/Makefile Normal file
View File

@ -0,0 +1,3 @@
obj-y += clock.o reset.o timer.o
obj-y += 8815.o

52
arch/arm/mach-nomadik/clock.c Normal file
View File

@ -0,0 +1,52 @@
/*
* linux/arch/arm/mach-nomadik/clock.c
*
* Copyright (C) 2009 Alessandro Rubini
*/
#include <common.h>
#include <errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <init.h>
#include <asm/clkdev.h>
#include "clock.h"
/*
* The nomadik board uses generic clocks, but the serial pl011 file
* calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
*/
unsigned long clk_get_rate(struct clk *clk)
{
return clk->rate;
}
EXPORT_SYMBOL(clk_get_rate);
/* enable and disable do nothing */
int clk_enable(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
int __clk_get(struct clk *clk)
{
return 1;
}
/* Create a clock structure with the given name */
int nmdk_clk_create(struct clk *clk, const char *dev_id)
{
struct clk_lookup *clkdev;
clkdev = clkdev_alloc(clk, NULL, dev_id);
if (!clkdev)
return -ENOMEM;
clkdev_add(clkdev);
return 0;
}

14
arch/arm/mach-nomadik/clock.h Normal file
View File

@ -0,0 +1,14 @@
/*
* linux/arch/arm/mach-nomadik/clock.h
*
* Copyright (C) 2009 Alessandro Rubini
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
struct clk {
unsigned long rate;
};
int nmdk_clk_create(struct clk *clk, const char *dev_id);

28
arch/arm/mach-nomadik/include/mach/board.h Normal file
View File

@ -0,0 +1,28 @@
/*
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __ASM_ARCH_BOARD_H
#define __ASM_ARCH_BOARD_H
void st8815_add_device_sdram(u32 size);
void st8815_register_uart(unsigned id);
#endif

7
arch/arm/mach-nomadik/include/mach/clkdev.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __ASM_MACH_CLKDEV_H
#define __ASM_MACH_CLKDEV_H
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif

28
arch/arm/mach-nomadik/include/mach/fsmc.h Normal file
View File

@ -0,0 +1,28 @@
/* Definitions for the Nomadik FSMC "Flexible Static Memory controller" */
#ifndef __ASM_ARCH_FSMC_H
#define __ASM_ARCH_FSMC_H
#include <mach/hardware.h>
/*
* Register list
*/
/* bus control reg. and bus timing reg. for CS0..CS3 */
#define FSMC_BCR(x) (NOMADIK_FSMC_VA + (x << 3))
#define FSMC_BTR(x) (NOMADIK_FSMC_VA + (x << 3) + 0x04)
/* PC-card and NAND:
* PCR = control register
* PMEM = memory timing
* PATT = attribute timing
* PIO = I/O timing
* PECCR = ECC result
*/
#define FSMC_PCR(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x00)
#define FSMC_PMEM(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x08)
#define FSMC_PATT(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x0c)
#define FSMC_PIO(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x10)
#define FSMC_PECCR(x) (NOMADIK_FSMC_VA + ((2 + x) << 5) + 0x14)
#endif /* __ASM_ARCH_FSMC_H */

91
arch/arm/mach-nomadik/include/mach/hardware.h Normal file
View File

@ -0,0 +1,91 @@
/*
* This file contains the hardware definitions of the Nomadik.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* YOU should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
#define NOMADIK_IO_VIRTUAL 0xF0000000 /* VA of IO */
#define NOMADIK_IO_PHYSICAL 0x10000000 /* PA of IO */
#define NOMADIK_IO_SIZE 0x00300000 /* 3MB for all regs */
#ifndef CONFIG_MMU
#define io_p2v(x) (x)
#define io_v2p(x) (x)
#else
#define io_p2v(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
#define io_v2p(x) ((x) - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
#endif
#define IO_ADDRESS(x) (io_p2v(x)) /* used in asm and more */
/*
* Base address defination for Nomadik Onchip Logic Block
*/
#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
#define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
#define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
#define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
#define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
#define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
#define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
#define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
#define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
#define NOMADIK_XTI_BASE 0x101A0000 /* XTI */
#define NOMADIK_RNG_BASE 0x101B0000 /* Random number generator */
#define NOMADIK_SRC_BASE 0x101E0000 /* SRC base */
#define NOMADIK_WDOG_BASE 0x101E1000 /* Watchdog */
#define NOMADIK_MTU0_BASE 0x101E2000 /* Multiple Timer 0 */
#define NOMADIK_MTU1_BASE 0x101E3000 /* Multiple Timer 1 */
#define NOMADIK_GPIO0_BASE 0x101E4000 /* GPIO0 */
#define NOMADIK_GPIO1_BASE 0x101E5000 /* GPIO1 */
#define NOMADIK_GPIO2_BASE 0x101E6000 /* GPIO2 */
#define NOMADIK_GPIO3_BASE 0x101E7000 /* GPIO3 */
#define NOMADIK_RTC_BASE 0x101E8000 /* Real Time Clock base */
#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
#define NOMADIK_OWM_BASE 0x101EA000 /* One wire master */
#define NOMADIK_SCR_BASE 0x101EF000 /* Secure Control registers */
#define NOMADIK_MSP2_BASE 0x101F0000 /* MSP 2 interface */
#define NOMADIK_MSP1_BASE 0x101F1000 /* MSP 1 interface */
#define NOMADIK_UART2_BASE 0x101F2000 /* UART 2 interface */
#define NOMADIK_SSIRx_BASE 0x101F3000 /* SSI 8-ch rx interface */
#define NOMADIK_SSITx_BASE 0x101F4000 /* SSI 8-ch tx interface */
#define NOMADIK_MSHC_BASE 0x101F5000 /* Memory Stick(Pro) Host */
#define NOMADIK_SDI_BASE 0x101F6000 /* SD-card/MM-Card */
#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
#define NOMADIK_MSP0_BASE 0x101F9000 /* MSP 0 interface */
#define NOMADIK_FIRDA_BASE 0x101FA000 /* FIrDA interface */
#define NOMADIK_UART1_BASE 0x101FB000 /* UART 1 interface */
#define NOMADIK_SSP_BASE 0x101FC000 /* SSP interface */
#define NOMADIK_UART0_BASE 0x101FD000 /* UART 0 interface */
#define NOMADIK_SGA_BASE 0x101FE000 /* SGA interface */
#define NOMADIK_L2CC_BASE 0x10210000 /* L2 Cache controller */
/* Other ranges, not for p2v/v2p */
#define NOMADIK_BACKUP_RAM 0x80010000
#define NOMADIK_EBROM 0x80000000 /* Embedded boot ROM */
#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000 /* HAMACV Data Memory Start */
#define NOMADIK_HAMACV_DMEM_END 0xA01FFFFF /* HAMACV Data Memory End */
#define NOMADIK_HAMACA_DMEM 0xA0200000 /* HAMACA Data Memory Space */
#define NOMADIK_FSMC_VA IO_ADDRESS(NOMADIK_FSMC_BASE)
#define NOMADIK_MTU0_VA IO_ADDRESS(NOMADIK_MTU0_BASE)
#define NOMADIK_MTU1_VA IO_ADDRESS(NOMADIK_MTU1_BASE)
#endif /* __ASM_ARCH_HARDWARE_H */

46
arch/arm/mach-nomadik/include/mach/mtu.h Normal file
View File

@ -0,0 +1,46 @@
#ifndef __ASM_ARCH_MTU_H
#define __ASM_ARCH_MTU_H
/*
* The MTU device hosts four different counters, with 4 set of
* registers. These are register names.
*/
#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
#define MTU_RIS 0x04 /* Raw interrupt status */
#define MTU_MIS 0x08 /* Masked interrupt status */
#define MTU_ICR 0x0C /* Interrupt clear register */
/* per-timer registers take 0..3 as argument */
#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
/* bits for the control register */
#define MTU_CRn_ENA 0x80
#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK 0x0c
#define MTU_CRn_PRESCALE_1 0x00
#define MTU_CRn_PRESCALE_16 0x04
#define MTU_CRn_PRESCALE_256 0x08
#define MTU_CRn_32BITS 0x02
#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR 0xff0
#define MTU_ITOP 0xff4
#define MTU_PERIPH_ID0 0xfe0
#define MTU_PERIPH_ID1 0xfe4
#define MTU_PERIPH_ID2 0xfe8
#define MTU_PERIPH_ID3 0xfeC
#define MTU_PCELL0 0xff0
#define MTU_PCELL1 0xff4
#define MTU_PCELL2 0xff8
#define MTU_PCELL3 0xffC
#endif /* __ASM_ARCH_MTU_H */

16
arch/arm/mach-nomadik/include/mach/nand.h Normal file
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@ -0,0 +1,16 @@
#ifndef __ASM_ARCH_NAND_H
#define __ASM_ARCH_NAND_H
struct nomadik_nand_platform_data {
unsigned long data_va;
unsigned long cmd_va;
unsigned long addr_va;
int options;
int (*init) (void);
};
#define NAND_IO_DATA 0x40000000
#define NAND_IO_CMD 0x40800000
#define NAND_IO_ADDR 0x41000000
#endif /* __ASM_ARCH_NAND_H */

6
arch/arm/mach-nomadik/include/mach/timex.h Normal file
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@ -0,0 +1,6 @@
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#define CLOCK_TICK_RATE 2400000
#endif

36
arch/arm/mach-nomadik/reset.c Normal file
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@ -0,0 +1,36 @@
/*
* mach-nomadik/include/mach/system.h
*
* Copyright (C) 2008 STMicroelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <mach/hardware.h>
void __noreturn reset_cpu(unsigned long addr)
{
void __iomem *src_rstsr = (void *)(NOMADIK_SRC_BASE + 0x18);
/* FIXME: use egpio when implemented */
/* Write anything to Reset status register */
writel(1, src_rstsr);
/* Not reached */
while (1);
}
EXPORT_SYMBOL(reset_cpu);

81
arch/arm/mach-nomadik/timer.c Normal file
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@ -0,0 +1,81 @@
/*
* linux/arch/arm/mach-nomadik/timer.c
*
* Copyright (C) 2008 STMicroelectronics
* Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <init.h>
#include <clock.h>
#include <asm/io.h>
#include <mach/hardware.h>
#include <mach/mtu.h>
#include <mach/timex.h>
/* Initial value for SRC control register: all timers use MXTAL/8 source */
#define SRC_CR_INIT_MASK 0x00007fff
#define SRC_CR_INIT_VAL 0x2aaa8000
static u32 nmdk_cycle; /* write-once */
static __iomem void *mtu_base;
/*
* clocksource: the MTU device is a decrementing counters, so we negate
* the value being read.
*/
static uint64_t nmdk_read_timer(void)
{
return nmdk_cycle - readl(mtu_base + MTU_VAL(0));
}
static struct clocksource nmdk_clksrc = {
.read = nmdk_read_timer,
.shift = 20,
.mask = 0xffffffff,
};
static void nmdk_timer_reset(void)
{
u32 cr;
writel(0, mtu_base + MTU_CR(0)); /* off */
/* configure load and background-load, and fire it up */
writel(nmdk_cycle, mtu_base + MTU_LR(0));
writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
cr = MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
writel(cr, mtu_base + MTU_CR(0));
writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
}
static int nmdk_timer_init(void)
{
u32 src_cr;
unsigned long rate;
rate = CLOCK_TICK_RATE; /* 2.4MHz */
nmdk_cycle = (rate + 1000 / 2) / 1000;
/* Configure timer sources in "system reset controller" ctrl reg */
src_cr = readl(NOMADIK_SRC_BASE);
src_cr &= SRC_CR_INIT_MASK;
src_cr |= SRC_CR_INIT_VAL;
writel(src_cr, NOMADIK_SRC_BASE);
/* Save global pointer to mtu, used by functions above */
mtu_base = (void *)NOMADIK_MTU0_BASE;
/* Init the timer and register clocksource */
nmdk_timer_reset();
nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
init_clock(&nmdk_clksrc);
return 0;
}
core_initcall(nmdk_timer_init);

15
arch/arm/mach-omap/Kconfig
View File

@ -78,9 +78,18 @@ config GPMC
depends on (ARCH_OMAP2 || ARCH_OMAP3)
default y
help
Enable this if you use Texas Instrument's General purpose Memory
Controller(GPMC). GPMC allows you to configure devices such as NOR,
NAND, OneNAND etc.
Enable this if you use Texas Instrument's General purpose Memory
Controller(GPMC). GPMC allows you to configure devices such as NOR,
NAND, OneNAND etc.
config GPIO
prompt "Support for GPIO configuration"
bool
select GENERIC_GPIO
depends on (ARCH_OMAP2 || ARCH_OMAP3)
default y
help
Enable this if you use Texas Instrument's General Purpose IO
# Get the board specific configurations
source arch/arm/boards/omap/Kconfig

1
arch/arm/mach-omap/Makefile
View File

@ -24,3 +24,4 @@ obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_core.o omap3_generic.o
obj-$(CONFIG_OMAP3_CLOCK_CONFIG) += omap3_clock_core.o omap3_clock.o
obj-$(CONFIG_GPMC) += gpmc.o
obj-$(CONFIG_GPIO) += gpio.o

206
arch/arm/mach-omap/gpio.c Normal file
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@ -0,0 +1,206 @@
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <mach/gpio.h>
#include <asm/io.h>
#include <errno.h>
static struct gpio_bank gpio_bank_34xx[6] = {
{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
};
static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
static inline struct gpio_bank *get_gpio_bank(int gpio)
{
return &gpio_bank[gpio >> 5];
}
static inline int get_gpio_index(int gpio)
{
return gpio & 0x1f;
}
static inline int gpio_valid(int gpio)
{
if (gpio < 0)
return -1;
if (gpio < 192)
return 0;
return -1;
}
static int check_gpio(int gpio)
{
if (gpio_valid(gpio) < 0) {
printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
return -1;
}
return 0;
}
void gpio_set_value(unsigned gpio, int value)
{
struct gpio_bank *bank;
void *reg;
u32 l = 0;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
reg = bank->base;
switch (bank->method) {
case METHOD_GPIO_24XX:
if (value)
reg += OMAP24XX_GPIO_SETDATAOUT;
else
reg += OMAP24XX_GPIO_CLEARDATAOUT;
l = 1 << get_gpio_index(gpio);
break;
default:
printf("omap3-gpio unknown bank method %s %d\n",
__FILE__, __LINE__);
return;
}
__raw_writel(l, reg);
}
int gpio_direction_input(unsigned gpio)
{
struct gpio_bank *bank;
void *reg;
u32 val;
if (check_gpio(gpio) < 0)
return -EINVAL;
bank = get_gpio_bank(gpio);
reg = bank->base;
switch (bank->method) {
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
default:
return -EINVAL;
}
val = __raw_readl(reg);
val |= 1 << get_gpio_index(gpio);
__raw_writel(val, reg);
return 0;
}
int gpio_direction_output(unsigned gpio, int value)
{
struct gpio_bank *bank;
void *reg;
u32 val;
if (check_gpio(gpio) < 0)
return -EINVAL;
bank = get_gpio_bank(gpio);
reg = bank->base;
gpio_set_value(gpio, value);
switch (bank->method) {
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_OE;
break;
default:
return -EINVAL;
}
val = __raw_readl(reg);
val &= ~(1 << get_gpio_index(gpio));
__raw_writel(val, reg);
return 0;
}
int gpio_get_value(unsigned gpio)
{
struct gpio_bank *bank;
void *reg;
if (check_gpio(gpio) < 0)
return -EINVAL;
bank = get_gpio_bank(gpio);
reg = bank->base;
switch (bank->method) {
case METHOD_GPIO_24XX:
reg += OMAP24XX_GPIO_DATAIN;
break;
default:
return -EINVAL;
}
return (__raw_readl(reg)
& (1 << get_gpio_index(gpio))) != 0;
}
static void _reset_gpio(int gpio)
{
gpio_direction_input(gpio);
}
int omap_request_gpio(int gpio)
{
if (check_gpio(gpio) < 0)
return -EINVAL;
return 0;
}
void omap_free_gpio(int gpio)
{
struct gpio_bank *bank;
if (check_gpio(gpio) < 0)
return;
bank = get_gpio_bank(gpio);
_reset_gpio(gpio);
}

799
arch/arm/mach-omap/include/mach/cm-regbits-34xx.h Normal file
View File

@ -0,0 +1,799 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_34XX_H
/*
* OMAP3430 Clock Management register bits
*
* Copyright (C) 2007-2008 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation
*
* Written by Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* Bits shared between registers */
/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
#define OMAP3430ES2_EN_MMC3_SHIFT 30
#define OMAP3430_EN_MSPRO_MASK (1 << 23)
#define OMAP3430_EN_MSPRO_SHIFT 23
#define OMAP3430_EN_HDQ_MASK (1 << 22)
#define OMAP3430_EN_HDQ_SHIFT 22
#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
#define OMAP3430ES1_EN_D2D_SHIFT 3
#define OMAP3430_EN_SSI_MASK (1 << 0)
#define OMAP3430_EN_SSI_SHIFT 0
/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
#define OMAP3430ES2_EN_USBTLL_SHIFT 2
#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
#define OMAP3430_EN_WDT2_MASK (1 << 5)
#define OMAP3430_EN_WDT2_SHIFT 5
/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
#define OMAP3430_EN_CAM_MASK (1 << 0)
#define OMAP3430_EN_CAM_SHIFT 0
/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
#define OMAP3430_EN_WDT3_MASK (1 << 12)
#define OMAP3430_EN_WDT3_SHIFT 12
/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
/* Bits specific to each register */
/* CM_FCLKEN_IVA2 */
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
/* CM_CLKEN_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_IVA2 */
#define OMAP3430_ST_IVA2_MASK (1 << 0)
/* CM_IDLEST_PLL_IVA2 */
#define OMAP3430_ST_IVA2_CLK_SHIFT 0
#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL_IVA2 */
#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_IVA2 */
#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
#define OMAP3430_IVA2_CLK_SRC_MASK (0x3 << 19)
#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_IVA2 */
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* CM_CLKSTCTRL_IVA2 */
#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
/* CM_CLKSTST_IVA2 */
#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
/* CM_REVISION specific bits */
/* CM_SYSCONFIG specific bits */
/* CM_CLKEN_PLL_MPU */
#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_MPU_DPLL_SHIFT 0
#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_MPU */
#define OMAP3430_ST_MPU_MASK (1 << 0)
/* CM_IDLEST_PLL_MPU */
#define OMAP3430_ST_MPU_CLK_SHIFT 0
#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL_MPU */
#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL_MPU */
#define OMAP3430_MPU_CLK_SRC_SHIFT 19
#define OMAP3430_MPU_CLK_SRC_MASK (0x3 << 19)
#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL2_PLL_MPU */
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
/* CM_CLKSTCTRL_MPU */
#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
/* CM_CLKSTST_MPU */
#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
/* CM_FCLKEN1_CORE specific bits */
#define OMAP3430_EN_MODEM_MASK (1 << 31)
#define OMAP3430_EN_MODEM_SHIFT 31
/* CM_ICLKEN1_CORE specific bits */
#define OMAP3430_EN_ICR_MASK (1 << 29)
#define OMAP3430_EN_ICR_SHIFT 29
#define OMAP3430_EN_AES2_MASK (1 << 28)
#define OMAP3430_EN_AES2_SHIFT 28
#define OMAP3430_EN_SHA12_MASK (1 << 27)
#define OMAP3430_EN_SHA12_SHIFT 27
#define OMAP3430_EN_DES2_MASK (1 << 26)
#define OMAP3430_EN_DES2_SHIFT 26
#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
#define OMAP3430ES1_EN_FAC_SHIFT 8
#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
#define OMAP3430_EN_MAILBOXES_SHIFT 7
#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_EN_OMAPCTRL_SHIFT 6
#define OMAP3430_EN_SAD2D_MASK (1 << 3)
#define OMAP3430_EN_SAD2D_SHIFT 3
#define OMAP3430_EN_SDRC_MASK (1 << 1)
#define OMAP3430_EN_SDRC_SHIFT 1
/* AM35XX specific CM_ICLKEN1_CORE bits */
#define AM35XX_EN_IPSS_MASK (1 << 4)
#define AM35XX_EN_IPSS_SHIFT 4
#define AM35XX_EN_UART4_MASK (1 << 23)
#define AM35XX_EN_UART4_SHIFT 23
/* CM_ICLKEN2_CORE */
#define OMAP3430_EN_PKA_MASK (1 << 4)
#define OMAP3430_EN_PKA_SHIFT 4
#define OMAP3430_EN_AES1_MASK (1 << 3)
#define OMAP3430_EN_AES1_SHIFT 3
#define OMAP3430_EN_RNG_MASK (1 << 2)
#define OMAP3430_EN_RNG_SHIFT 2
#define OMAP3430_EN_SHA11_MASK (1 << 1)
#define OMAP3430_EN_SHA11_SHIFT 1
#define OMAP3430_EN_DES1_MASK (1 << 0)
#define OMAP3430_EN_DES1_SHIFT 0
/* CM_ICLKEN3_CORE */
#define OMAP3430_EN_MAD2D_SHIFT 3
#define OMAP3430_EN_MAD2D_MASK (1 << 3)
/* CM_FCLKEN3_CORE specific bits */
#define OMAP3430ES2_EN_TS_SHIFT 1
#define OMAP3430ES2_EN_TS_MASK (1 << 1)
#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
/* CM_IDLEST1_CORE specific bits */
#define OMAP3430ES2_ST_MMC3_SHIFT 30
#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
#define OMAP3430_ST_ICR_SHIFT 29
#define OMAP3430_ST_ICR_MASK (1 << 29)
#define OMAP3430_ST_AES2_SHIFT 28
#define OMAP3430_ST_AES2_MASK (1 << 28)
#define OMAP3430_ST_SHA12_SHIFT 27
#define OMAP3430_ST_SHA12_MASK (1 << 27)
#define OMAP3430_ST_DES2_SHIFT 26
#define OMAP3430_ST_DES2_MASK (1 << 26)
#define OMAP3430_ST_MSPRO_SHIFT 23
#define OMAP3430_ST_MSPRO_MASK (1 << 23)
#define OMAP3430_ST_HDQ_SHIFT 22
#define OMAP3430_ST_HDQ_MASK (1 << 22)
#define OMAP3430ES1_ST_FAC_SHIFT 8
#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
#define OMAP3430_ST_MAILBOXES_SHIFT 7
#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
#define OMAP3430_ST_OMAPCTRL_SHIFT 6
#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_ST_SDMA_SHIFT 2
#define OMAP3430_ST_SDMA_MASK (1 << 2)
#define OMAP3430_ST_SDRC_SHIFT 1
#define OMAP3430_ST_SDRC_MASK (1 << 1)
#define OMAP3430_ST_SSI_STDBY_SHIFT 0
#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
/* AM35xx specific CM_IDLEST1_CORE bits */
#define AM35XX_ST_IPSS_SHIFT 5
#define AM35XX_ST_IPSS_MASK (1 << 5)
/* CM_IDLEST2_CORE */
#define OMAP3430_ST_PKA_SHIFT 4
#define OMAP3430_ST_PKA_MASK (1 << 4)
#define OMAP3430_ST_AES1_SHIFT 3
#define OMAP3430_ST_AES1_MASK (1 << 3)
#define OMAP3430_ST_RNG_SHIFT 2
#define OMAP3430_ST_RNG_MASK (1 << 2)
#define OMAP3430_ST_SHA11_SHIFT 1
#define OMAP3430_ST_SHA11_MASK (1 << 1)
#define OMAP3430_ST_DES1_SHIFT 0
#define OMAP3430_ST_DES1_MASK (1 << 0)
/* CM_IDLEST3_CORE */
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
/* CM_AUTOIDLE1_CORE */
#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
#define OMAP3430_AUTO_MODEM_SHIFT 31
#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
#define OMAP3430ES2_AUTO_ICR_SHIFT 29
#define OMAP3430_AUTO_AES2_MASK (1 << 28)
#define OMAP3430_AUTO_AES2_SHIFT 28
#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
#define OMAP3430_AUTO_SHA12_SHIFT 27
#define OMAP3430_AUTO_DES2_MASK (1 << 26)
#define OMAP3430_AUTO_DES2_SHIFT 26
#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
#define OMAP3430_AUTO_MMC2_SHIFT 25
#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
#define OMAP3430_AUTO_MMC1_SHIFT 24
#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
#define OMAP3430_AUTO_MSPRO_SHIFT 23
#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
#define OMAP3430_AUTO_HDQ_SHIFT 22
#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
#define OMAP3430_AUTO_MCSPI4_SHIFT 21
#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
#define OMAP3430_AUTO_MCSPI3_SHIFT 20
#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
#define OMAP3430_AUTO_MCSPI2_SHIFT 19
#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
#define OMAP3430_AUTO_MCSPI1_SHIFT 18
#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
#define OMAP3430_AUTO_I2C3_SHIFT 17
#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
#define OMAP3430_AUTO_I2C2_SHIFT 16
#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
#define OMAP3430_AUTO_I2C1_SHIFT 15
#define OMAP3430_AUTO_UART2_MASK (1 << 14)
#define OMAP3430_AUTO_UART2_SHIFT 14
#define OMAP3430_AUTO_UART1_MASK (1 << 13)
#define OMAP3430_AUTO_UART1_SHIFT 13
#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
#define OMAP3430_AUTO_GPT11_SHIFT 12
#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
#define OMAP3430_AUTO_GPT10_SHIFT 11
#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
#define OMAP3430_AUTO_MCBSP5_SHIFT 10
#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
#define OMAP3430_AUTO_MCBSP1_SHIFT 9
#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
#define OMAP3430ES1_AUTO_FAC_SHIFT 8
#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
#define OMAP3430ES1_AUTO_D2D_SHIFT 3
#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
#define OMAP3430_AUTO_SAD2D_SHIFT 3
#define OMAP3430_AUTO_SSI_MASK (1 << 0)
#define OMAP3430_AUTO_SSI_SHIFT 0
/* CM_AUTOIDLE2_CORE */
#define OMAP3430_AUTO_PKA_MASK (1 << 4)
#define OMAP3430_AUTO_PKA_SHIFT 4
#define OMAP3430_AUTO_AES1_MASK (1 << 3)
#define OMAP3430_AUTO_AES1_SHIFT 3
#define OMAP3430_AUTO_RNG_MASK (1 << 2)
#define OMAP3430_AUTO_RNG_SHIFT 2
#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
#define OMAP3430_AUTO_SHA11_SHIFT 1
#define OMAP3430_AUTO_DES1_MASK (1 << 0)
#define OMAP3430_AUTO_DES1_SHIFT 0
/* CM_AUTOIDLE3_CORE */
#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
#define OMAP3430_AUTO_MAD2D_SHIFT 3
#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
/* CM_CLKSEL_CORE */
#define OMAP3430_CLKSEL_SSI_SHIFT 8
#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT11_SHIFT 7
#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT10_SHIFT 6
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_L4_SHIFT 2
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
#define OMAP3630_CLKSEL_96M_SHIFT 12
#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
/* CM_CLKSTCTRL_CORE */
#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */
#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
/* CM_FCLKEN_GFX */
#define OMAP3430ES1_EN_3D_MASK (1 << 2)
#define OMAP3430ES1_EN_3D_SHIFT 2
#define OMAP3430ES1_EN_2D_MASK (1 << 1)
#define OMAP3430ES1_EN_2D_SHIFT 1
/* CM_ICLKEN_GFX specific bits */
/* CM_IDLEST_GFX specific bits */
/* CM_CLKSEL_GFX specific bits */
/* CM_SLEEPDEP_GFX specific bits */
/* CM_CLKSTCTRL_GFX */
#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
/* CM_CLKSTST_GFX */
#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
/* CM_FCLKEN_SGX */
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
/* CM_IDLEST_SGX */
#define OMAP3430ES2_ST_SGX_SHIFT 1
#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
/* CM_ICLKEN_SGX */
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
/* CM_CLKSEL_SGX */
#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
/* CM_CLKSTCTRL_SGX */
#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
/* CM_CLKSTST_SGX */
#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
/* CM_FCLKEN_WKUP specific bits */
#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
/* CM_ICLKEN_WKUP specific bits */
#define OMAP3430_EN_WDT1_MASK (1 << 4)
#define OMAP3430_EN_WDT1_SHIFT 4
#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
#define OMAP3430_EN_32KSYNC_SHIFT 2
/* CM_IDLEST_WKUP specific bits */
#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
#define OMAP3430_ST_WDT2_SHIFT 5
#define OMAP3430_ST_WDT2_MASK (1 << 5)
#define OMAP3430_ST_WDT1_SHIFT 4
#define OMAP3430_ST_WDT1_MASK (1 << 4)
#define OMAP3430_ST_32KSYNC_SHIFT 2
#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
/* CM_AUTOIDLE_WKUP */
#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
#define OMAP3430_AUTO_WDT2_SHIFT 5
#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
#define OMAP3430_AUTO_WDT1_SHIFT 4
#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
#define OMAP3430_AUTO_GPIO1_SHIFT 3
#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
#define OMAP3430_AUTO_32KSYNC_SHIFT 2
#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
#define OMAP3430_AUTO_GPT12_SHIFT 1
#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
#define OMAP3430_AUTO_GPT1_SHIFT 0
/* CM_CLKSEL_WKUP */
#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
#define OMAP3430_CLKSEL_RM_SHIFT 1
#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
#define OMAP3430_CLKSEL_GPT1_SHIFT 0
#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
/* CM_CLKEN_PLL */
#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
#define OMAP3430_PWRDN_CAM_SHIFT 30
#define OMAP3430_PWRDN_DSS1_SHIFT 29
#define OMAP3430_PWRDN_TV_SHIFT 28
#define OMAP3430_PWRDN_96M_SHIFT 27
#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
#define OMAP3430_EN_CORE_DPLL_SHIFT 0
#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
/* CM_CLKEN2_PLL */
#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_IDLEST_CKGEN */
#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
#define OMAP3430_ST_CORE_CLK_SHIFT 0
#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
/* CM_IDLEST2_CKGEN */
#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
/* CM_AUTOIDLE_PLL */
#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
/* CM_AUTOIDLE2_PLL */
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
/* CM_CLKSEL1_PLL */
/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
#define OMAP3430_SOURCE_96M_SHIFT 6
#define OMAP3430_SOURCE_96M_MASK (1 << 6)
#define OMAP3430_SOURCE_54M_SHIFT 5
#define OMAP3430_SOURCE_54M_MASK (1 << 5)
#define OMAP3430_SOURCE_48M_SHIFT 3
#define OMAP3430_SOURCE_48M_MASK (1 << 3)
/* CM_CLKSEL2_PLL */
#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
/* CM_CLKSEL3_PLL */
#define OMAP3430_DIV_96M_SHIFT 0
#define OMAP3430_DIV_96M_MASK (0x1f << 0)
#define OMAP3630_DIV_96M_MASK (0x3f << 0)
/* CM_CLKSEL4_PLL */
#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
/* CM_CLKSEL5_PLL */
#define OMAP3430ES2_DIV_120M_SHIFT 0
#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
/* CM_CLKOUT_CTRL */
#define OMAP3430_CLKOUT2_EN_SHIFT 7
#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
#define OMAP3430_CLKOUT2_DIV_SHIFT 3
#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
/* CM_FCLKEN_DSS */
#define OMAP3430_EN_TV_MASK (1 << 2)
#define OMAP3430_EN_TV_SHIFT 2
#define OMAP3430_EN_DSS2_MASK (1 << 1)
#define OMAP3430_EN_DSS2_SHIFT 1
#define OMAP3430_EN_DSS1_MASK (1 << 0)
#define OMAP3430_EN_DSS1_SHIFT 0
/* CM_ICLKEN_DSS */
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
/* CM_IDLEST_DSS */
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
#define OMAP3430ES1_ST_DSS_SHIFT 0
#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
/* CM_AUTOIDLE_DSS */
#define OMAP3430_AUTO_DSS_MASK (1 << 0)
#define OMAP3430_AUTO_DSS_SHIFT 0
/* CM_CLKSEL_DSS */
#define OMAP3430_CLKSEL_TV_SHIFT 8
#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
#define OMAP3430_CLKSEL_DSS1_SHIFT 0
#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
/* CM_SLEEPDEP_DSS specific bits */
/* CM_CLKSTCTRL_DSS */
#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
/* CM_CLKSTST_DSS */
#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
/* CM_FCLKEN_CAM specific bits */
#define OMAP3430_EN_CSI2_MASK (1 << 1)
#define OMAP3430_EN_CSI2_SHIFT 1
/* CM_ICLKEN_CAM specific bits */
/* CM_IDLEST_CAM */
#define OMAP3430_ST_CAM_MASK (1 << 0)
/* CM_AUTOIDLE_CAM */
#define OMAP3430_AUTO_CAM_MASK (1 << 0)
#define OMAP3430_AUTO_CAM_SHIFT 0
/* CM_CLKSEL_CAM */
#define OMAP3430_CLKSEL_CAM_SHIFT 0
#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
/* CM_SLEEPDEP_CAM specific bits */
/* CM_CLKSTCTRL_CAM */
#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
/* CM_CLKSTST_CAM */
#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
/* CM_FCLKEN_PER specific bits */
/* CM_ICLKEN_PER specific bits */
/* CM_IDLEST_PER */
#define OMAP3430_ST_WDT3_SHIFT 12
#define OMAP3430_ST_WDT3_MASK (1 << 12)
#define OMAP3430_ST_MCBSP4_SHIFT 2
#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
#define OMAP3430_ST_MCBSP3_SHIFT 1
#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
#define OMAP3430_ST_MCBSP2_SHIFT 0
#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
/* CM_AUTOIDLE_PER */
#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
#define OMAP3430_AUTO_GPIO6_SHIFT 17
#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
#define OMAP3430_AUTO_GPIO5_SHIFT 16
#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
#define OMAP3430_AUTO_GPIO4_SHIFT 15
#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
#define OMAP3430_AUTO_GPIO3_SHIFT 14
#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
#define OMAP3430_AUTO_GPIO2_SHIFT 13
#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
#define OMAP3430_AUTO_WDT3_SHIFT 12
#define OMAP3430_AUTO_UART3_MASK (1 << 11)
#define OMAP3430_AUTO_UART3_SHIFT 11
#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
#define OMAP3430_AUTO_GPT9_SHIFT 10
#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
#define OMAP3430_AUTO_GPT8_SHIFT 9
#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
#define OMAP3430_AUTO_GPT7_SHIFT 8
#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
#define OMAP3430_AUTO_GPT6_SHIFT 7
#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
#define OMAP3430_AUTO_GPT5_SHIFT 6
#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
#define OMAP3430_AUTO_GPT4_SHIFT 5
#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
#define OMAP3430_AUTO_GPT3_SHIFT 4
#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
#define OMAP3430_AUTO_GPT2_SHIFT 3
#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
#define OMAP3430_AUTO_MCBSP4_SHIFT 2
#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
#define OMAP3430_AUTO_MCBSP3_SHIFT 1
#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
#define OMAP3430_AUTO_MCBSP2_SHIFT 0
/* CM_CLKSEL_PER */
#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
#define OMAP3430_CLKSEL_GPT9_SHIFT 7
#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT8_SHIFT 6
#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
#define OMAP3430_CLKSEL_GPT7_SHIFT 5
#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
#define OMAP3430_CLKSEL_GPT6_SHIFT 4
#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
#define OMAP3430_CLKSEL_GPT5_SHIFT 3
#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
#define OMAP3430_CLKSEL_GPT4_SHIFT 2
#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
#define OMAP3430_CLKSEL_GPT3_SHIFT 1
#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
#define OMAP3430_CLKSEL_GPT2_SHIFT 0
/* CM_SLEEPDEP_PER specific bits */
#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_PER */
#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
/* CM_CLKSTST_PER */
#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
/* CM_CLKSEL1_EMU */
#define OMAP3430_DIV_DPLL4_SHIFT 24
#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
#define OMAP3430_DIV_DPLL3_SHIFT 16
#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
#define OMAP3430_CLKSEL_PCLK_SHIFT 8
#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
#define OMAP3430_MUX_CTRL_SHIFT 0
#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
/* CM_CLKSTCTRL_EMU */
#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
/* CM_CLKSTST_EMU */
#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
/* CM_CLKSEL2_EMU specific bits */
#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_CLKSEL3_EMU specific bits */
#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
/* CM_POLCTRL */
#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
/* CM_IDLEST_NEON */
#define OMAP3430_ST_NEON_MASK (1 << 0)
/* CM_CLKSTCTRL_NEON */
#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
/* CM_FCLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
/* CM_ICLKEN_USBHOST */
#define OMAP3430ES2_EN_USBHOST_SHIFT 0
#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
/* CM_IDLEST_USBHOST */
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
/* CM_AUTOIDLE_USBHOST */
#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
/* CM_SLEEPDEP_USBHOST */
#define OMAP3430ES2_EN_MPU_SHIFT 1
#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
#define OMAP3430ES2_EN_IVA2_SHIFT 2
#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
/* CM_CLKSTCTRL_USBHOST */
#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
/* CM_CLKSTST_USBHOST */
#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
#endif

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arch/arm/mach-omap/include/mach/ehci.h Normal file
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/*
* Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de>
*
* This file is released under the GPLv2
*
*/
#ifndef __OMAP_EHCI_H
#define __OMAP_EHCI_H
/* TLL Register Set */
#define OMAP_USBTLL_REVISION (0x00)
#define OMAP_USBTLL_SYSCONFIG (0x10)
#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
#define OMAP_USBTLL_SYSSTATUS (0x14)
#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
#define OMAP_USBTLL_IRQSTATUS (0x18)
#define OMAP_USBTLL_IRQENABLE (0x1C)
#define OMAP_TLL_SHARED_CONF (0x30)
#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
#define OMAP_TLL_CHANNEL_COUNT 3
#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 1)
#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 2)
#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 4)
/* UHH Register Set */
#define OMAP_UHH_REVISION (0x00)
#define OMAP_UHH_SYSCONFIG (0x10)
#define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12)
#define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8)
#define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3)
#define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2)
#define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1)
#define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0)
#define OMAP_UHH_SYSSTATUS (0x14)
#define OMAP_UHH_HOSTCONFIG (0x40)
#define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0)
#define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0)
#define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11)
#define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12)
#define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2)
#define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3)
#define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4)
#define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5)
#define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8)
#define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9)
#define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10)
#define OMAP_UHH_DEBUG_CSR (0x44)
/* EHCI Register Set */
#define EHCI_INSNREG05_ULPI (0xA4)
#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31
#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24
#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22
#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16
#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8
#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0
#define OMAP3_HS_USB_PORTS 3
enum ehci_hcd_omap_mode {
EHCI_HCD_OMAP_MODE_UNKNOWN,
EHCI_HCD_OMAP_MODE_PHY,
EHCI_HCD_OMAP_MODE_TLL,
};
struct omap_hcd {
enum ehci_hcd_omap_mode port_mode[OMAP3_HS_USB_PORTS];
unsigned phy_reset:1;
/* have to be valid if phy_reset is true and portx is in phy mode */
int reset_gpio_port[OMAP3_HS_USB_PORTS];
};
void omap_usb_utmi_init(struct omap_hcd *omap, u8 tll_channel_mask);
int ehci_omap_init(struct omap_hcd *omap);
#endif /* __OMAP_EHCI_H */

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arch/arm/mach-omap/include/mach/generic.h Normal file
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/* I2C controller revisions */
#define OMAP_I2C_REV_2 0x20
/* I2C controller revisions present on specific hardware */
#define OMAP_I2C_REV_ON_2430 0x36
#define OMAP_I2C_REV_ON_3430 0x3C
#ifdef CONFIG_ARCH_OMAP
#define cpu_is_omap2430() (1)
#else
#define cpu_is_omap2430() (0)
#endif
#ifdef CONFIG_ARCH_OMAP3
#define cpu_is_omap34xx() (1)
#else
#define cpu_is_omap34xx() (0)
#endif

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