dts: update to v4.5
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
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6ea52c3bc3
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83e61900b0
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@ -23,6 +23,7 @@ Optional properties:
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during suspend.
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- ti,no-reset-on-init: When present, the module should not be reset at init
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- ti,no-idle-on-init: When present, the module should not be idled at init
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- ti,no-idle: When present, the module is never allowed to idle.
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Example:
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@ -70,8 +70,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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@ -76,8 +76,8 @@
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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devbus-bootcs {
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status = "okay";
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@ -95,8 +95,8 @@
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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devbus-bootcs {
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status = "okay";
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@ -65,8 +65,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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@ -70,8 +70,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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@ -68,8 +68,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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internal-regs {
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serial@12000 {
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@ -64,8 +64,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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@ -65,9 +65,9 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x01, 0x2f) 0 0 0xe8000000 0x8000000
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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devbus-bootcs {
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status = "okay";
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@ -78,8 +78,8 @@
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x09) 0 0 0xf8100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf8110000 0x10000>;
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MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
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pcie-controller {
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status = "okay";
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@ -1500,6 +1500,16 @@
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0x48485200 0x2E00>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* Do not allow gating of cpsw clock as workaround
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* for errata i877. Keeping internal clock disabled
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* causes the device switching characteristics
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* to degrade over time and eventually fail to meet
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* the data manual delay time/skew specs.
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*/
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ti,no-idle;
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/*
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* rx_thresh_pend
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* rx_pend
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