ppc 8xxx: DIMM parameters calculation
This code calculates the DIMM characteritics i.e DIMM organization parameters and timings for DDR2 memory based on SPD data. It also provides a function to find out the lowest common DIMM parameters to be used for all DIMMs. This code is based on the equivalent files in directory arch/powerpc/cpu/mpc8xxx/ddr from U-Boot version git-a71d45d. Signed-off-by: Renaud Barbier <renaud.barbier@ge.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Renaud Barbier
Sascha Hauer
parent
c6594ae1a3
commit
8567f00489
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@ -0,0 +1,303 @@
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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/*
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* Calculate the Density of each Physical Rank.
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* Returned size is in bytes.
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*
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* Table comes from Byte 31 of JEDEC SPD Spec.
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*
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* DDR II
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* Bit Size Size
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* --- -----
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* 7 high 512MB
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* 6 256MB
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* 5 128MB
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* 4 16GB
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* 3 8GB
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* 2 4GB
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* 1 2GB
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* 0 low 1GB
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*
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* Reorder Table to be linear by stripping the bottom
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* 2 or 5 bits off and shifting them up to the top.
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*
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*/
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static uint64_t compute_ranksize(uint32_t mem_type, unsigned char row_dens)
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{
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uint64_t bsize;
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bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
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bsize <<= 27ULL;
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return bsize;
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}
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/*
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* Convert a two-nibble BCD value into a cycle time.
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* While the spec calls for nano-seconds, picos are returned.
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*/
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static uint32_t convert_bcd_tenths_to_cycle_time_ps(uint32_t spd_val)
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{
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uint32_t tenths_ps[16] = {
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0,
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100,
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200,
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300,
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400,
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500,
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600,
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700,
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800,
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900,
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250,
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330,
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660,
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750,
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0,
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0
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};
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uint32_t whole_ns = (spd_val & 0xF0) >> 4;
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uint32_t tenth_ns = spd_val & 0x0F;
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uint32_t ps = (whole_ns * 1000) + tenths_ps[tenth_ns];
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return ps;
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}
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static uint32_t convert_bcd_hundredths_to_cycle_time_ps(uint32_t spd_val)
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{
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uint32_t tenth_ns = (spd_val & 0xF0) >> 4;
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uint32_t hundredth_ns = spd_val & 0x0F;
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uint32_t ps = (tenth_ns * 100) + (hundredth_ns * 10);
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return ps;
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}
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static uint32_t byte40_table_ps[8] = {
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0,
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250,
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330,
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500,
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660,
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750,
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0,
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0
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};
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static uint32_t
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compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
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{
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uint32_t trfc_ps;
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trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000;
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trfc_ps += byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
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return trfc_ps;
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}
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static uint32_t
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compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
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{
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uint32_t trc_ps;
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trc_ps = (trc * 1000);
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trc_ps += byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
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return trc_ps;
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}
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/*
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* Determine Refresh Rate.
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* Table from SPD Spec, Byte 12, converted to picoseconds and
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* filled in with "default" normal values.
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*/
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static uint32_t determine_refresh_rate_ps(const uint32_t spd_refresh)
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{
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uint32_t refresh_time_ps[8] = {
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15625000, /* 0 Normal 1.00x */
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3900000, /* 1 Reduced .25x */
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7800000, /* 2 Extended .50x */
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31300000, /* 3 Extended 2.00x */
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62500000, /* 4 Extended 4.00x */
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125000000, /* 5 Extended 8.00x */
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15625000, /* 6 Normal 1.00x filler */
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15625000, /* 7 Normal 1.00x filler */
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};
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return refresh_time_ps[spd_refresh & 0x7];
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}
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/*
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* The purpose of this function is to compute a suitable
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* CAS latency given the DRAM clock period. The SPD only
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* defines at most 3 CAS latencies. Typically the slower in
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* frequency the DIMM runs at, the shorter its CAS latency can.
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* be. If the DIMM is operating at a sufficiently low frequency,
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* it may be able to run at a CAS latency shorter than the
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* shortest SPD-defined CAS latency.
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*
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* If a CAS latency is not found, 0 is returned.
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*
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* Do this by finding in the standard speed table the longest
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* tCKmin that doesn't exceed the value of mclk_ps (tCK).
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*
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* An assumption made is that the SDRAM device allows the
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* CL to be programmed for a value that is lower than those
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* advertised by the SPD. This is not always the case,
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* as those modes not defined in the SPD are optional.
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*
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* CAS latency de-rating based upon values JEDEC Standard No. 79-2C
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* Table 40, "DDR2 SDRAM standard speed bins and tCK, tRCD, tRP, tRAS,
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* and tRC for corresponding bin"
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*
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* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
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* Not certain if any good value exists for CL=2
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*/
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/* CL2 CL3 CL4 CL5 CL6 CL7 */
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uint16_t ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
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uint32_t compute_derated_DDR2_CAS_latency(uint32_t mclk_ps)
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{
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const uint32_t num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
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uint32_t lowest_tCKmin_found = 0, lowest_tCKmin_CL = 0, i, x;
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for (i = 0; i < num_speed_bins; i++) {
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x = ddr2_speed_bins[i];
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if (x && (x <= mclk_ps) && (x >= lowest_tCKmin_found)) {
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lowest_tCKmin_found = x;
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lowest_tCKmin_CL = i + 2;
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}
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}
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return lowest_tCKmin_CL;
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}
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/*
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* compute_dimm_parameters for DDR2 SPD
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*
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* Compute DIMM parameters based upon the SPD information in SPD.
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* Writes the results to the dimm_params_s structure pointed by pdimm.
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*/
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uint32_t
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compute_dimm_parameters(const generic_spd_eeprom_t *spdin,
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struct dimm_params_s *pdimm)
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{
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const struct ddr2_spd_eeprom_s *spd = spdin;
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uint32_t retval;
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if (!spd->mem_type) {
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memset(pdimm, 0, sizeof(struct dimm_params_s));
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goto error;
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}
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if (spd->mem_type != SPD_MEMTYPE_DDR2)
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goto error;
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retval = ddr2_spd_checksum_pass(spd);
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if (retval)
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goto spd_err;
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/*
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* The part name in ASCII in the SPD EEPROM is not null terminated.
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* Guarantee null termination here by presetting all bytes to 0
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* and copying the part name in ASCII from the SPD onto it
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*/
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
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/* DIMM organization parameters */
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pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
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pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
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pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
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pdimm->data_width = spd->dataw;
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pdimm->primary_sdram_width = spd->primw;
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pdimm->ec_sdram_width = spd->ecw;
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/* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
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switch (spd->dimm_type) {
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case DDR2_SPD_DIMMTYPE_RDIMM:
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case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
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case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
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/* Registered/buffered DIMMs */
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pdimm->registered_dimm = 1;
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break;
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case DDR2_SPD_DIMMTYPE_UDIMM:
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case DDR2_SPD_DIMMTYPE_SO_DIMM:
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case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
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case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
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/* Unbuffered DIMMs */
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pdimm->registered_dimm = 0;
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break;
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case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
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default:
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goto error;
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}
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pdimm->n_row_addr = spd->nrow_addr;
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pdimm->n_col_addr = spd->ncol_addr;
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pdimm->n_banks_per_sdram_device = spd->nbanks;
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pdimm->edc_config = spd->config;
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pdimm->burst_lengths_bitmask = spd->burstl;
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pdimm->row_density = spd->rank_dens;
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/*
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* Calculate the Maximum Data Rate based on the Minimum Cycle time.
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* The SPD clk_cycle field (tCKmin) is measured in tenths of
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* nanoseconds and represented as BCD.
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*/
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pdimm->tCKmin_X_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
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pdimm->tCKmin_X_minus_1_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
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pdimm->tCKmin_X_minus_2_ps
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= convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
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pdimm->tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
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/*
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* Compute CAS latencies defined by SPD
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* The SPD caslat_X should have at least 1 and at most 3 bits set.
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*
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* If cas_lat after masking is 0, the __ilog2 function returns
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* 255 into the variable. This behavior is abused once.
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*/
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pdimm->caslat_X = __ilog2(spd->cas_lat);
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pdimm->caslat_X_minus_1 = __ilog2(spd->cas_lat
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& ~(1 << pdimm->caslat_X));
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pdimm->caslat_X_minus_2 = __ilog2(spd->cas_lat & ~(1 << pdimm->caslat_X)
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& ~(1 << pdimm->caslat_X_minus_1));
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pdimm->caslat_lowest_derated
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= compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
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pdimm->tRCD_ps = spd->trcd * 250;
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pdimm->tRP_ps = spd->trp * 250;
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pdimm->tRAS_ps = spd->tras * 1000;
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pdimm->tWR_ps = spd->twr * 250;
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pdimm->tWTR_ps = spd->twtr * 250;
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pdimm->tRFC_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
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pdimm->tRRD_ps = spd->trrd * 250;
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pdimm->tRC_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
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pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
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pdimm->tIS_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
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pdimm->tIH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
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pdimm->tDS_ps
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= convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
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pdimm->tDH_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
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pdimm->tRTP_ps = spd->trtp * 250;
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pdimm->tDQSQ_max_ps = spd->tdqsq * 10;
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pdimm->tQHS_ps = spd->tqhs * 10;
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return 0;
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error:
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return 1;
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spd_err:
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return 2;
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}
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@ -0,0 +1,214 @@
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/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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static unsigned int common_burst_length(
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const struct dimm_params_s *dimm_params,
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const unsigned int number_of_dimms)
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{
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unsigned int i, temp;
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temp = 0xff;
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for (i = 0; i < number_of_dimms; i++)
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if (dimm_params[i].n_ranks)
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temp &= dimm_params[i].burst_lengths_bitmask;
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return temp;
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}
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/* Compute a CAS latency suitable for all DIMMs */
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static unsigned int compute_lowest_caslat(
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const struct dimm_params_s *dimm_params,
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const unsigned int number_of_dimms)
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{
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uint32_t temp1, temp2, i, not_ok, lowest_good_caslat,
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tCKmin_X_minus_1_ps, tCKmin_X_minus_2_ps;
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
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* operation.
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*/
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temp1 = 0xFF;
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for (i = 0; i < number_of_dimms; i++)
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if (dimm_params[i].n_ranks) {
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temp2 = 0;
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temp2 |= 1 << dimm_params[i].caslat_X;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
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/*
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* FIXME: If there was no entry for X-2 (X-1) in
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* the SPD, then caslat_X_minus_2
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* (caslat_X_minus_1) contains either 255 or
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* 0xFFFFFFFF because that's what the __ilog2
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* function returns for an input of 0.
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* On 32-bit PowerPC, left shift counts with bit
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* 26 set (that the value of 255 or 0xFFFFFFFF
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* will have), cause the destination register to
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* be 0. That is why this works.
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*/
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temp1 &= temp2;
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}
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/*
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* Step 2: check each common CAS latency against tCK of each
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* DIMM's SPD.
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*/
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lowest_good_caslat = 0;
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temp2 = 0;
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while (temp1) {
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not_ok = 0;
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temp2 = __ilog2(temp1);
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for (i = 0; i < number_of_dimms; i++) {
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if (!dimm_params[i].n_ranks)
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continue;
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if (dimm_params[i].caslat_X == temp2) {
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if (mclk_ps >= dimm_params[i].tCKmin_X_ps)
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continue;
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else
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not_ok++;
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}
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if (dimm_params[i].caslat_X_minus_1 == temp2) {
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tCKmin_X_minus_1_ps =
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dimm_params[i].tCKmin_X_minus_1_ps;
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if (mclk_ps >= tCKmin_X_minus_1_ps)
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continue;
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else
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not_ok++;
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}
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if (dimm_params[i].caslat_X_minus_2 == temp2) {
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tCKmin_X_minus_2_ps
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= dimm_params[i].tCKmin_X_minus_2_ps;
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if (mclk_ps >= tCKmin_X_minus_2_ps)
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continue;
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else
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not_ok++;
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}
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}
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if (!not_ok)
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lowest_good_caslat = temp2;
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temp1 &= ~(1 << temp2);
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}
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return lowest_good_caslat;
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}
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/*
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* compute_lowest_common_dimm_parameters()
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*
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* Determine the worst-case DIMM timing parameters from the set of DIMMs
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* whose parameters have been computed into the array pointed to
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* by dimm_params.
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*/
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unsigned int
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compute_lowest_common_dimm_parameters(const struct dimm_params_s *dimm,
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struct common_timing_params_s *out,
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const unsigned int number_of_dimms)
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{
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const uint32_t mclk_ps = get_memory_clk_period_ps();
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uint32_t temp1, i;
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struct common_timing_params_s tmp = {0};
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tmp.tCKmax_ps = 0xFFFFFFFF;
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm[i].n_ranks == 0) {
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temp1++;
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continue;
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}
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/*
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* Find minimum tCKmax_ps to find fastest slow speed,
|
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* i.e., this is the slowest the whole system can go.
|
||||
*/
|
||||
tmp.tCKmax_ps = min(tmp.tCKmax_ps, dimm[i].tCKmax_ps);
|
||||
|
||||
/* Find maximum value to determine slowest speed, delay, etc */
|
||||
tmp.tCKmin_X_ps = max(tmp.tCKmin_X_ps, dimm[i].tCKmin_X_ps);
|
||||
tmp.tCKmax_max_ps = max(tmp.tCKmax_max_ps, dimm[i].tCKmax_ps);
|
||||
tmp.tRCD_ps = max(tmp.tRCD_ps, dimm[i].tRCD_ps);
|
||||
tmp.tRP_ps = max(tmp.tRP_ps, dimm[i].tRP_ps);
|
||||
tmp.tRAS_ps = max(tmp.tRAS_ps, dimm[i].tRAS_ps);
|
||||
tmp.tWR_ps = max(tmp.tWR_ps, dimm[i].tWR_ps);
|
||||
tmp.tWTR_ps = max(tmp.tWTR_ps, dimm[i].tWTR_ps);
|
||||
tmp.tRFC_ps = max(tmp.tRFC_ps, dimm[i].tRFC_ps);
|
||||
tmp.tRRD_ps = max(tmp.tRRD_ps, dimm[i].tRRD_ps);
|
||||
tmp.tRC_ps = max(tmp.tRC_ps, dimm[i].tRC_ps);
|
||||
tmp.tIS_ps = max(tmp.tIS_ps, dimm[i].tIS_ps);
|
||||
tmp.tIH_ps = max(tmp.tIH_ps, dimm[i].tIH_ps);
|
||||
tmp.tDS_ps = max(tmp.tDS_ps, dimm[i].tDS_ps);
|
||||
tmp.tDH_ps = max(tmp.tDH_ps, dimm[i].tDH_ps);
|
||||
tmp.tRTP_ps = max(tmp.tRTP_ps, dimm[i].tRTP_ps);
|
||||
tmp.tQHS_ps = max(tmp.tQHS_ps, dimm[i].tQHS_ps);
|
||||
tmp.refresh_rate_ps = max(tmp.refresh_rate_ps,
|
||||
dimm[i].refresh_rate_ps);
|
||||
/* Find maximum tDQSQ_max_ps to find slowest timing. */
|
||||
tmp.tDQSQ_max_ps = max(tmp.tDQSQ_max_ps, dimm[i].tDQSQ_max_ps);
|
||||
}
|
||||
tmp.ndimms_present = number_of_dimms - temp1;
|
||||
|
||||
if (temp1 == number_of_dimms)
|
||||
return 0;
|
||||
|
||||
temp1 = common_burst_length(dimm, number_of_dimms);
|
||||
tmp.all_DIMMs_burst_lengths_bitmask = temp1;
|
||||
tmp.all_DIMMs_registered = 0;
|
||||
|
||||
tmp.lowest_common_SPD_caslat = compute_lowest_caslat(dimm,
|
||||
number_of_dimms);
|
||||
/*
|
||||
* Compute a common 'de-rated' CAS latency.
|
||||
*
|
||||
* The strategy here is to find the *highest* de-rated cas latency
|
||||
* with the assumption that all of the DIMMs will support a de-rated
|
||||
* CAS latency higher than or equal to their lowest de-rated value.
|
||||
*/
|
||||
temp1 = 0;
|
||||
for (i = 0; i < number_of_dimms; i++)
|
||||
temp1 = max(temp1, dimm[i].caslat_lowest_derated);
|
||||
tmp.highest_common_derated_caslat = temp1;
|
||||
|
||||
temp1 = 1;
|
||||
for (i = 0; i < number_of_dimms; i++)
|
||||
if (dimm[i].n_ranks &&
|
||||
!(dimm[i].edc_config & EDC_ECC)) {
|
||||
temp1 = 0;
|
||||
break;
|
||||
}
|
||||
tmp.all_DIMMs_ECC_capable = temp1;
|
||||
|
||||
if (mclk_ps > tmp.tCKmax_max_ps)
|
||||
return 1;
|
||||
|
||||
/*
|
||||
* AL must be less or equal to tRCD. Typically, AL would
|
||||
* be AL = tRCD - 1;
|
||||
*
|
||||
* When ODT read or write is enabled the sum of CAS latency +
|
||||
* additive latency must be at least 3 cycles.
|
||||
*
|
||||
*/
|
||||
if ((tmp.lowest_common_SPD_caslat < 4) && (picos_to_mclk(tmp.tRCD_ps) >
|
||||
tmp.lowest_common_SPD_caslat))
|
||||
tmp.additive_latency = picos_to_mclk(tmp.tRCD_ps) -
|
||||
tmp.lowest_common_SPD_caslat;
|
||||
|
||||
memcpy(out, &tmp, sizeof(struct common_timing_params_s));
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue