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barebox
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Merge branch 'for-next/omap'

This commit is contained in:
Sascha Hauer 2013-08-05 12:50:09 +02:00
parent fbf082b565 ed1618261b
commit 8599b7aec2
33 changed files with 605 additions and 47 deletions
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5
arch/arm/boards/archosg9/lowlevel.c
View File

@ -14,6 +14,7 @@
#include <io.h>
#include <init.h>
#include <sizes.h>
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-clock.h>
@ -64,8 +65,10 @@ static noinline void archosg9_init_lowlevel(void)
omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core);
}
void __naked __bare_init barebox_arm_reset_vector(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)

6
arch/arm/boards/beagle/lowlevel.c
View File

@ -1,8 +1,10 @@
#include <init.h>
#include <io.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/control.h>
#include <mach/generic.h>
#include <mach/omap3-silicon.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
@ -178,8 +180,10 @@ static int beagle_board_init(void)
return 0;
}
void __naked barebox_arm_reset_vector(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
beagle_board_init();

7
arch/arm/boards/beaglebone/lowlevel.c
View File

@ -5,6 +5,7 @@
#include <asm/barebox-arm.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/generic.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
@ -197,7 +198,7 @@ void beaglebone_sram_init(void)
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
pll_init(MPUPLL_M_500);
beaglebone_config_ddr();
@ -248,8 +249,10 @@ static int beaglebone_board_init(void)
return 0;
}
void __naked barebox_arm_reset_vector(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
beaglebone_board_init();

6
arch/arm/boards/omap343xdsp/lowlevel.c
View File

@ -1,8 +1,10 @@
#include <common.h>
#include <init.h>
#include <io.h>
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/generic.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
#include <mach/control.h>
@ -545,8 +547,10 @@ static int sdp343x_board_init(void)
return 0;
}
void __naked barebox_arm_reset_vector(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
sdp343x_board_init();

5
arch/arm/boards/omap3evm/lowlevel.c
View File

@ -3,6 +3,7 @@
#include <sizes.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/generic.h>
#include <mach/omap3-mux.h>
#include <mach/sdrc.h>
#include <mach/control.h>
@ -159,8 +160,10 @@ static int omap3_evm_board_init(void)
return 0;
}
void __naked barebox_arm_reset_vector(void)
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
omap3_evm_board_init();

6
arch/arm/boards/panda/lowlevel.c
View File

@ -17,8 +17,10 @@
*
*/
#include <common.h>
#include <init.h>
#include <io.h>
#include <sizes.h>
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-clock.h>
@ -76,8 +78,10 @@ static void noinline panda_init_lowlevel(void)
omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210);
}
void barebox_arm_reset_vector(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)

6
arch/arm/boards/pcm049/lowlevel.c
View File

@ -17,8 +17,10 @@
*
*/
#include <common.h>
#include <init.h>
#include <io.h>
#include <sizes.h>
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-clock.h>
@ -106,8 +108,10 @@ static void noinline pcm049_init_lowlevel(void)
sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */
}
void barebox_arm_reset_vector(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)

69
arch/arm/boards/pcm051/board.c
View File

@ -17,9 +17,11 @@
*
*/
#include <bootsource.h>
#include <common.h>
#include <init.h>
#include <io.h>
#include <nand.h>
#include <sizes.h>
#include <ns16550.h>
#include <asm/armlinux.h>
@ -30,6 +32,9 @@
#include <mach/am33xx-mux.h>
#include <mach/am33xx-silicon.h>
#include <mach/cpsw.h>
#include <mach/generic.h>
#include <mach/gpmc.h>
#include <mach/gpmc_nand.h>
#include <spi/spi.h>
#include <spi/flash.h>
#include <i2c/i2c.h>
@ -45,6 +50,7 @@
*/
static int pcm051_console_init(void)
{
am33xx_enable_uart0_pin_mux();
/* Register the serial port */
am33xx_add_uart0();
@ -61,7 +67,7 @@ static int pcm051_mem_init(void)
mem_initcall(pcm051_mem_init);
static struct flash_platform_data pcm051_spi_flash = {
.name = "nor",
.name = "m25p",
.type = "w25q64",
};
@ -97,6 +103,32 @@ static struct i2c_board_info i2c0_devices[] = {
},
};
static struct gpmc_config pcm051_nand_cfg = {
.cfg = {
0x00000800, /* CONF1 */
0x00030300, /* CONF2 */
0x00030300, /* CONF3 */
0x02000311, /* CONF4 */
0x00030303, /* CONF5 */
0x03000540, /* CONF6 */
},
.base = 0x08000000,
.size = GPMC_SIZE_16M,
};
static struct gpmc_nand_platform_data nand_plat = {
.wait_mon_pin = 1,
.ecc_mode = OMAP_ECC_BCH8_CODE_HW,
.nand_cfg = &pcm051_nand_cfg,
};
static struct omap_barebox_part pcm051_barebox_part = {
.nand_offset = SZ_512K,
.nand_size = SZ_512K,
.nor_offset = SZ_128K,
.nor_size = SZ_512K,
};
static void pcm051_spi_init(void)
{
int ret;
@ -128,6 +160,15 @@ static void pcm051_i2c_init(void)
am33xx_add_i2c0(NULL);
}
static void pcm051_nand_init(void)
{
am33xx_enable_nand_pin_mux();
gpmc_generic_init(0x12);
omap_add_gpmc_nand_device(&nand_plat);
}
static int pcm051_devices_init(void)
{
pcm051_enable_mmc0_pin_mux();
@ -137,14 +178,34 @@ static int pcm051_devices_init(void)
pcm051_spi_init();
pcm051_eth_init();
pcm051_i2c_init();
pcm051_nand_init();
devfs_add_partition("nor0", 0x00000, SZ_128K,
pcm051_enable_user_led_pin_mux();
pcm051_enable_user_btn_pin_mux();
switch (bootsource_get()) {
case BOOTSOURCE_SPI:
devfs_add_partition("m25p0", 0x00000, SZ_128K,
DEVFS_PARTITION_FIXED, "xload");
devfs_add_partition("nor0", SZ_128K, SZ_512K,
devfs_add_partition("m25p0", SZ_128K, SZ_512K,
DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_128K + SZ_512K, SZ_128K,
devfs_add_partition("m25p0", SZ_128K + SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env0");
break;
default:
devfs_add_partition("nand0", 0x00000, SZ_128K,
DEVFS_PARTITION_FIXED, "xload_raw");
dev_add_bb_dev("xload_raw", "xload");
devfs_add_partition("nand0", SZ_512K, SZ_512K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K + SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
}
omap_set_barebox_part(&pcm051_barebox_part);
armlinux_set_bootparams((void *)(AM33XX_DRAM_ADDR_SPACE_START + 0x100));
armlinux_set_architecture(MACH_TYPE_PCM051);

10
arch/arm/boards/pcm051/env/boot/nand-ubi vendored Normal file
View File

@ -0,0 +1,10 @@
#!/bin/sh
if [ "$1" = menu ]; then
boot-menu-add-entry "$0" "nand (UBI)"
exit
fi
global.bootm.image="/dev/nand0.kernel.bb"
#global.bootm.oftree="/env/oftree"
bootargs-root-ubi -r root -m nand0.root,2048

2
arch/arm/boards/pcm051/env/boot/sd vendored
View File

@ -6,5 +6,5 @@ if [ "$1" = menu ]; then
fi
global.bootm.image=/boot/uImage
global.bootm.oftree=/boot/oftree
#global.bootm.oftree=/boot/oftree
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"

2
arch/arm/boards/pcm051/env/boot/spi-nor vendored
View File

@ -5,7 +5,7 @@ if [ "$1" = menu ]; then
exit
fi
global.bootm.image="/dev/nor0.kernel"
global.bootm.image="/dev/m25p0.kernel"
# Use rootfs form SD-Card for now as rootfs partition < 4MB
global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"

11
arch/arm/boards/pcm051/env/init/mtdparts-nand vendored Normal file
View File

@ -0,0 +1,11 @@
#!/bin/sh
if [ "$1" = menu ]; then
init-menu-add-entry "$0" "NAND partitions"
exit
fi
mtdparts="128k(nand0.xload),128k(nand0.xload_backup1),128k(nand0.xload_backup2),128k(nand0.xload_backup3),512k(nand0.barebox)ro,128k(nand0.bareboxenv),8M(nand0.kernel),-(nand0.root)"
kernelname="omap2-nand.0"
mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts}

4
arch/arm/boards/pcm051/env/init/mtdparts-nor vendored
View File

@ -5,8 +5,8 @@ if [ "$1" = menu ]; then
exit
fi
mtdparts="128k(nor0.xload),512k(nor0.barebox),128k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)"
mtdparts="128k(m25p0.xload),512k(m25p0.barebox),128k(m25p0.bareboxenv),4M(m25p0.kernel),-(m25p0.root)"
kernelname="spi_flash"
mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts}
mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts}

211
arch/arm/boards/pcm051/lowlevel.c
View File

@ -1,11 +1,220 @@
#include <common.h>
#include <sizes.h>
#include <io.h>
#include <init.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/generic.h>
#include <mach/sdrc.h>
#include <mach/sys_info.h>
#include <mach/syslib.h>
#include <mach/am33xx-mux.h>
#include <mach/wdt.h>
void __naked barebox_arm_reset_vector(void)
/* UART Defines */
#define UART_SYSCFG_OFFSET (0x54)
#define UART_SYSSTS_OFFSET (0x58)
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define CMD_FORCE 0x00 /* common #def */
#define CMD_DELAY 0x00
#define EMIF_READ_LATENCY 0x06
#define EMIF_SDCFG 0x61C04832 /* CL 5, CWL 5 */
#define EMIF_SDREF 0x0000093B
#define EMIF_TIM1 0x0668A39B
#define EMIF_TIM2 0x26337FDA
#define EMIF_TIM3 0x501F830F
#define DLL_LOCK_DIFF 0x0
#define PHY_WR_DATA 0xC1
#define RD_DQS 0x3B
#define WR_DQS 0x85
#define PHY_FIFO_WE 0x100
#define INVERT_CLKOUT 0x1
#define PHY_RANK0_DELAY 0x01
#define DDR_IOCTRL_VALUE 0x18B
#define CTRL_SLAVE_RATIO 0x40
#define PHY_LVL_MODE 0x1
#define DDR_ZQ_CFG 0x50074BE4
static void Cmd_Macro_Config(void)
{
writel(CTRL_SLAVE_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0);
writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0);
writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0);
writel(DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0);
writel(INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0);
writel(CTRL_SLAVE_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0);
writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0);
writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0);
writel(DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0);
writel(INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0);
writel(CTRL_SLAVE_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0);
writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0);
writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0);
writel(DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0);
writel(INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0);
}
static void config_vtp(void)
{
writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE,
AM33XX_VTP0_CTRL_REG);
writel(readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN),
AM33XX_VTP0_CTRL_REG);
writel(readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN,
AM33XX_VTP0_CTRL_REG);
/* Poll for READY */
while ((readl(AM33XX_VTP0_CTRL_REG) &
VTP_CTRL_READY) != VTP_CTRL_READY);
}
static void phy_config_data(void)
{
writel(RD_DQS, AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0);
writel(WR_DQS, AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0);
writel(PHY_FIFO_WE, AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0);
writel(PHY_WR_DATA, AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0);
writel(RD_DQS, AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0);
writel(WR_DQS, AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0);
writel(PHY_FIFO_WE, AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0);
writel(PHY_WR_DATA, AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0);
}
static void config_emif(void)
{
/*Program EMIF0 CFG Registers*/
writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1));
writel(EMIF_READ_LATENCY,
AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW));
writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2));
writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1));
writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW));
writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2));
writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW));
writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3));
writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW));
writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL));
writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW));
writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG));
writel(DDR_ZQ_CFG, AM33XX_EMIF4_0_REG(ZQ_CONFIG));
while ((readl(AM33XX_EMIF4_0_REG(SDRAM_STATUS)) & 0x4) != 0x4);
}
static void pcm051_config_ddr(void)
{
enable_ddr_clocks();
config_vtp();
/* init mode */
writel(PHY_LVL_MODE, AM33XX_DATA0_WRLVL_INIT_MODE_0);
writel(PHY_LVL_MODE, AM33XX_DATA0_GATELVL_INIT_MODE_0);
writel(PHY_LVL_MODE, AM33XX_DATA1_WRLVL_INIT_MODE_0);
writel(PHY_LVL_MODE, AM33XX_DATA1_GATELVL_INIT_MODE_0);
Cmd_Macro_Config();
phy_config_data();
writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0);
writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0);
writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL);
writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL);
writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL);
writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL);
writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL);
writel(readl(AM33XX_DDR_IO_CTRL) &
0xefffffff, AM33XX_DDR_IO_CTRL);
writel(readl(AM33XX_DDR_CKE_CTRL) |
0x00000001, AM33XX_DDR_CKE_CTRL);
config_emif();
}
/*
* early system init of muxing and clocks.
*/
void pcm051_sram_init(void)
{
u32 regVal, uart_base;
/* Setup the PLLs and the clocks for the peripherals */
pll_init(MPUPLL_M_600);
pcm051_config_ddr();
/* UART softreset */
am33xx_enable_uart0_pin_mux();
uart_base = AM33XX_UART0_BASE;
regVal = readl(uart_base + UART_SYSCFG_OFFSET);
regVal |= UART_RESET;
writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
while ((readl(uart_base + UART_SYSSTS_OFFSET) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK);
/* Disable smart idle */
regVal = readl((uart_base + UART_SYSCFG_OFFSET));
regVal |= UART_SMART_IDLE_EN;
writel(regVal, (uart_base + UART_SYSCFG_OFFSET));
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static int pcm051_board_init(void)
{
int in_sdram = running_in_sdram();
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
/* Dont reconfigure SDRAM while running in SDRAM! */
if (!in_sdram)
pcm051_sram_init();
return 0;
}
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
pcm051_board_init();
barebox_arm_entry(0x80000000, SZ_512M, 0);
}

22
arch/arm/boards/pcm051/mux.c
View File

@ -14,7 +14,29 @@ static const struct module_pin_mux mmc0_pin_mux[] = {
{-1},
};
static const struct module_pin_mux user_led_pin_mux[] = {
{OFFSET(gpmc_csn1), MODE(7) | PULLUDEN}, /* USER LED1 */
{OFFSET(gpmc_csn2), MODE(7) | PULLUDEN}, /* USER LED2 */
{-1},
};
static const struct module_pin_mux user_btn_pin_mux[] = {
{OFFSET(emu0), MODE(7) | RXACTIVE | PULLUP_EN},
{OFFSET(emu1), MODE(7) | RXACTIVE | PULLUP_EN},
{-1},
};
void pcm051_enable_mmc0_pin_mux(void)
{
configure_module_pin_mux(mmc0_pin_mux);
}
void pcm051_enable_user_led_pin_mux(void)
{
configure_module_pin_mux(user_led_pin_mux);
}
void pcm051_enable_user_btn_pin_mux(void)
{
configure_module_pin_mux(user_btn_pin_mux);
}

2
arch/arm/boards/pcm051/mux.h
View File

@ -1 +1,3 @@
extern void pcm051_enable_mmc0_pin_mux(void);
extern void pcm051_enable_user_led_pin_mux(void);
extern void pcm051_enable_user_btn_pin_mux(void);

5
arch/arm/boards/phycard-a-l1/lowlevel.c
View File

@ -5,6 +5,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <mach/omap3-mux.h>
#include <mach/generic.h>
#include <mach/sdrc.h>
#include <mach/control.h>
#include <mach/syslib.h>
@ -250,8 +251,10 @@ static int pcaal1_board_init(void)
return 0;
}
void __naked barebox_arm_reset_vector(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
pcaal1_board_init();

6
arch/arm/boards/phycard-a-xl2/lowlevel.c
View File

@ -17,8 +17,10 @@
*
*/
#include <common.h>
#include <init.h>
#include <io.h>
#include <sizes.h>
#include <mach/generic.h>
#include <mach/omap4-mux.h>
#include <mach/omap4-silicon.h>
#include <mach/omap4-clock.h>
@ -86,8 +88,10 @@ static noinline void pcaaxl2_init_lowlevel(void)
sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
}
void barebox_arm_reset_vector(void)
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
omap_save_bootinfo();
arm_cpu_lowlevel_init();
if (get_pc() > 0x80000000)

18
arch/arm/configs/pcm051_defconfig
View File

@ -1,11 +1,15 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
CONFIG_OMAP_BUILD_IFT=y
CONFIG_MACH_PCM051=y
CONFIG_OMAP_UART1=y
CONFIG_AEABI=y
CONFIG_ARM_BOARD_APPEND_ATAG=y
CONFIG_CMD_ARM_MMUINFO=y
CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
CONFIG_ARM_UNWIND=y
CONFIG_TEXT_BASE=0x81000000
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x8f000000
CONFIG_MALLOC_SIZE=0x2000000
CONFIG_PROMPT="barebox@pcm051>"
CONFIG_LONGHELP=y
CONFIG_HUSH_FANCY_PROMPT=y
@ -27,22 +31,27 @@ CONFIG_CMD_PRINTENV=y
CONFIG_CMD_READLINE=y
CONFIG_CMD_MENU=y
CONFIG_CMD_MENU_MANAGEMENT=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TFTP=y
CONFIG_CMD_ECHO_E=y
CONFIG_CMD_LOADB=y
CONFIG_CMD_CRC=y
CONFIG_CMD_CRC_CMP=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_FLASH=y
CONFIG_CMD_UBIFORMAT=y
CONFIG_CMD_BOOTM_SHOW_TYPE=y
CONFIG_CMD_UIMAGE=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_RESET=y
CONFIG_CMD_GO=y
CONFIG_CMD_BAREBOX_UPDATE=y
CONFIG_CMD_TIMEOUT=y
CONFIG_CMD_PARTITION=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_UNCOMPRESS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
CONFIG_NET=y
CONFIG_NET_DHCP=y
CONFIG_NET_NFS=y
@ -56,11 +65,16 @@ CONFIG_I2C_OMAP=y
CONFIG_MTD=y
CONFIG_MTD_M25P80=y
CONFIG_NAND=y
CONFIG_NAND_OMAP_GPMC=y
CONFIG_UBI=y
CONFIG_USB=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
CONFIG_EEPROM_AT24=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FAT_WRITE=y
CONFIG_FS_FAT_LFN=y

33
arch/arm/configs/pcm051_mlo_defconfig Normal file
View File

@ -0,0 +1,33 @@
CONFIG_ARCH_OMAP=y
CONFIG_ARCH_AM33XX=y
CONFIG_OMAP_BUILD_IFT=y
CONFIG_MACH_PCM051=y
CONFIG_OMAP_UART1=y
CONFIG_THUMB2_BAREBOX=y
# CONFIG_CMD_ARM_CPUINFO is not set
# CONFIG_BANNER is not set
# CONFIG_MEMINFO is not set
CONFIG_ENVIRONMENT_VARIABLES=y
CONFIG_MMU=y
CONFIG_TEXT_BASE=0x402F0400
CONFIG_STACK_SIZE=0x1600
CONFIG_MALLOC_SIZE=0x1000000
CONFIG_PROMPT="MLO>"
CONFIG_SHELL_NONE=y
# CONFIG_ERRNO_MESSAGES is not set
# CONFIG_TIMESTAMP is not set
# CONFIG_DEFAULT_ENVIRONMENT is not set
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
CONFIG_DRIVER_SPI_OMAP3=y
CONFIG_MTD=y
CONFIG_MTD_M25P80=y
CONFIG_NAND=y
CONFIG_NAND_OMAP_GPMC=y
CONFIG_MCI=y
CONFIG_MCI_STARTUP=y
CONFIG_MCI_OMAP_HSMMC=y
# CONFIG_FS_RAMFS is not set
# CONFIG_FS_DEVFS is not set
CONFIG_FS_FAT=y
CONFIG_FS_FAT_LFN=y

4
arch/arm/mach-omap/Makefile
View File

@ -15,8 +15,8 @@
# GNU General Public License for more details.
#
#
obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
pbl-$(CONFIG_ARCH_OMAP) += syslib.o
obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o omap_bootinfo.o
pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_bootinfo.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o
obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o

16
arch/arm/mach-omap/am33xx_clock.c
View File

@ -53,6 +53,18 @@ static void interface_clocks_enable(void)
/* GPIO0 */
__raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL);
while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN);
/* GPIO1 */
__raw_writel(PRCM_MOD_EN, CM_PER_GPIO1_CLKCTRL);
while (__raw_readl(CM_PER_GPIO1_CLKCTRL) != PRCM_MOD_EN);
/* GPIO2 */
__raw_writel(PRCM_MOD_EN, CM_PER_GPIO2_CLKCTRL);
while (__raw_readl(CM_PER_GPIO2_CLKCTRL) != PRCM_MOD_EN);
/* GPIO3 */
__raw_writel(PRCM_MOD_EN, CM_PER_GPIO3_CLKCTRL);
while (__raw_readl(CM_PER_GPIO3_CLKCTRL) != PRCM_MOD_EN);
}
static void power_domain_transition_enable(void)
@ -282,9 +294,9 @@ void enable_ddr_clocks(void)
/*
* Configure the PLL/PRCM for necessary peripherals
*/
void pll_init()
void pll_init(int mpupll_M)
{
mpu_pll_config(MPUPLL_M_500);
mpu_pll_config(mpupll_M);
core_pll_config();
per_pll_config();
ddr_pll_config();

47
arch/arm/mach-omap/am33xx_generic.c
View File

@ -25,8 +25,10 @@
#include <net.h>
#include <mach/am33xx-silicon.h>
#include <mach/am33xx-clock.h>
#include <mach/generic.h>
#include <mach/sys_info.h>
#include <mach/am33xx-generic.h>
#include <mach/gpmc.h>
void __noreturn reset_cpu(unsigned long addr)
{
@ -97,7 +99,22 @@ u32 running_in_sdram(void)
static int am33xx_bootsource(void)
{
bootsource_set(BOOTSOURCE_MMC); /* only MMC for now */
enum bootsource src;
switch (omap_bootinfo[2] & 0xFF) {
case 0x05:
src = BOOTSOURCE_NAND;
break;
case 0x08:
src = BOOTSOURCE_MMC;
break;
case 0x0b:
src = BOOTSOURCE_SPI;
break;
default:
src = BOOTSOURCE_UNKNOWN;
}
bootsource_set(src);
bootsource_set_instance(0);
return 0;
}
@ -126,3 +143,31 @@ int am33xx_register_ethaddr(int eth_id, int mac_id)
return -ENODEV;
}
/* GPMC timing for AM33XX nand device */
const struct gpmc_config am33xx_nand_cfg = {
.cfg = {
0x00000800, /* CONF1 */
0x001e1e00, /* CONF2 */
0x001e1e00, /* CONF3 */
0x16051807, /* CONF4 */
0x00151e1e, /* CONF5 */
0x16000f80, /* CONF6 */
},
.base = 0x08000000,
.size = GPMC_SIZE_16M,
};
static int am33xx_gpio_init(void)
{
add_generic_device("omap-gpio", 0, NULL, AM33XX_GPIO0_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 1, NULL, AM33XX_GPIO1_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 2, NULL, AM33XX_GPIO2_BASE,
0xf00, IORESOURCE_MEM, NULL);
add_generic_device("omap-gpio", 3, NULL, AM33XX_GPIO3_BASE,
0xf00, IORESOURCE_MEM, NULL);
return 0;
}
coredevice_initcall(am33xx_gpio_init);

8
arch/arm/mach-omap/am33xx_mux.c
View File

@ -39,8 +39,6 @@ static const __maybe_unused struct module_pin_mux uart3_pin_mux[] = {
{-1},
};
#ifdef CONFIG_NAND
static const __maybe_unused struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
@ -59,7 +57,6 @@ static const __maybe_unused struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
#endif
static const __maybe_unused struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
@ -319,3 +316,8 @@ void am33xx_enable_spi0_pin_mux(void)
{
configure_module_pin_mux(spi0_pin_mux);
}
void am33xx_enable_nand_pin_mux(void)
{
configure_module_pin_mux(nand_pin_mux);
}

2
arch/arm/mach-omap/include/mach/am33xx-clock.h
View File

@ -187,7 +187,7 @@
#define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL
extern void pll_init(void);
extern void pll_init(int mpupll_M);
extern void enable_ddr_clocks(void);
#endif /* endif _AM33XX_CLOCKS_H_ */

1
arch/arm/mach-omap/include/mach/am33xx-mux.h
View File

@ -257,5 +257,6 @@ extern void am33xx_enable_uart0_pin_mux(void);
extern void am33xx_enable_uart2_pin_mux(void);
extern void am33xx_enable_mmc0_pin_mux(void);
extern void am33xx_enable_spi0_pin_mux(void);
extern void am33xx_enable_nand_pin_mux(void);
#endif /*__AM33XX_MUX_H__ */

13
arch/arm/mach-omap/include/mach/am33xx-silicon.h
View File

@ -105,6 +105,7 @@
#define EMIF4_SDRAM_TIM_3_SHADOW 0x2C
#define EMIF0_SDRAM_MGMT_CTRL 0x38
#define EMIF0_SDRAM_MGMT_CTRL_SHD 0x3C
#define EMIF4_ZQ_CONFIG 0xC8
#define EMIF4_DDR_PHY_CTRL_1 0xE4
#define EMIF4_DDR_PHY_CTRL_1_SHADOW 0xE8
#define EMIF4_DDR_PHY_CTRL_2 0xEC
@ -157,9 +158,11 @@
#define AM33XX_DATA0_WRLVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F0)
#define AM33XX_DATA0_WRLVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F4)
#define AM33XX_DATA0_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0F8)
#define AM33XX_DATA0_GATELVL_INIT_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x0FC)
#define AM33XX_DATA0_GATELVL_INIT_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x100)
#define AM33XX_DATA0_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x104)
#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x108)
#define AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 (AM33XX_DDR_PHY_BASE_ADDR + 0x10C)
@ -169,6 +172,16 @@
#define AM33XX_DATA0_DLL_LOCK_DIFF_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x138)
#define AM33XX_DATA0_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x134)
#define AM33XX_DATA1_RD_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x16C)
#define AM33XX_DATA1_WR_DQS_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x180)
#define AM33XX_DATA1_WRLVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x19C)
#define AM33XX_DATA1_GATELVL_INIT_MODE_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1A8)
#define AM33XX_DATA1_FIFO_WE_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1AC)
#define AM33XX_DATA1_WR_DATA_SLAVE_RATIO_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1C4)
#define AM33XX_DATA1_RANK0_DELAYS_0 (AM33XX_DDR_PHY_BASE_ADDR + 0x1D8)
/* Ethernet MAC ID from EFuse */

19
arch/arm/mach-omap/include/mach/generic.h
View File

@ -33,4 +33,23 @@
#define cpu_is_am33xx() (0)
#endif
struct omap_barebox_part {
unsigned int nand_offset;
unsigned int nand_size;
unsigned int nor_offset;
unsigned int nor_size;
};
#ifdef CONFIG_SHELL_NONE
int omap_set_barebox_part(struct omap_barebox_part *part);
#else
static inline int omap_set_barebox_part(struct omap_barebox_part *part)
{
return 0;
}
#endif
extern uint32_t omap_bootinfo[3];
void omap_save_bootinfo(void);
#endif

1
arch/arm/mach-omap/include/mach/gpmc_nand.h
View File

@ -65,5 +65,6 @@ int omap_add_gpmc_nand_device(struct gpmc_nand_platform_data *pdata);
extern struct gpmc_config omap3_nand_cfg;
extern struct gpmc_config omap4_nand_cfg;
extern struct gpmc_config am33xx_nand_cfg;
#endif /* __ASM_OMAP_NAND_GPMC_H */

16
arch/arm/mach-omap/omap3_generic.c
View File

@ -33,6 +33,7 @@
#include <io.h>
#include <mach/omap3-silicon.h>
#include <mach/gpmc.h>
#include <mach/generic.h>
#include <mach/sdrc.h>
#include <mach/control.h>
#include <mach/omap3-smx.h>
@ -468,12 +469,21 @@ void omap3_core_init(void)
static int omap3_bootsource(void)
{
enum bootsource src = BOOTSOURCE_UNKNOWN;
u32 bootsrc = readl(OMAP3_TRACING_VECTOR1);
if (bootsrc & (1 << 2))
switch (omap_bootinfo[1] & 0xFF) {
case 0x02:
src = BOOTSOURCE_NAND;
if (bootsrc & (1 << 6))
break;
case 0x06:
src = BOOTSOURCE_MMC;
break;
case 0x11:
src = BOOTSOURCE_USB;
break;
default:
src = BOOTSOURCE_UNKNOWN;
}
bootsource_set(src);
bootsource_set_instance(0);

18
arch/arm/mach-omap/omap4_generic.c
View File

@ -6,6 +6,7 @@
#include <mach/omap4-silicon.h>
#include <mach/omap4-mux.h>
#include <mach/syslib.h>
#include <mach/generic.h>
#include <mach/gpmc.h>
#include <mach/gpio.h>
#include <mach/omap4_rom_usb.h>
@ -504,14 +505,21 @@ static int omap_vector_init(void)
static int omap4_bootsource(void)
{
enum bootsource src = BOOTSOURCE_UNKNOWN;
u32 bootsrc = readl(OMAP4_TRACING_VECTOR3);
if (bootsrc & (1 << 5))
src = BOOTSOURCE_MMC;
else if (bootsrc & (1 << 3))
switch (omap_bootinfo[2] & 0xFF) {
case 0x03:
src = BOOTSOURCE_NAND;
else if (bootsrc & (1<<20))
break;
case 0x05:
src = BOOTSOURCE_MMC;
break;
case 0x20:
src = BOOTSOURCE_USB;
break;
default:
src = BOOTSOURCE_UNKNOWN;
}
bootsource_set(src);
bootsource_set_instance(0);

25
arch/arm/mach-omap/omap_bootinfo.S Normal file
View File

@ -0,0 +1,25 @@
#include <config.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
.section ".text_bare_init","ax"
.globl omap_bootinfo
omap_bootinfo:
.word 0x0
.word 0x0
.word 0x0
.section ".text_bare_init","ax"
ENTRY(omap_save_bootinfo)
/*
* save data from rom boot loader
*/
adr r2, omap_bootinfo
ldr r1, [r0, #0x00]
str r1, [r2, #0x00]
ldr r1, [r0, #0x04]
str r1, [r2, #0x04]
ldr r1, [r0, #0x08]
str r1, [r2, #0x08]
mov pc, lr
ENDPROC(omap_save_bootinfo)

46
arch/arm/mach-omap/xload.c
View File

@ -9,6 +9,16 @@
#include <fcntl.h>
#include <sizes.h>
#include <filetype.h>
#include <mach/generic.h>
struct omap_barebox_part *barebox_part;
static struct omap_barebox_part default_part = {
.nand_offset = SZ_128K,
.nand_size = SZ_1M,
.nor_offset = SZ_128K,
.nor_size = SZ_1M,
};
static void *read_image_head(const char *name)
{
@ -45,14 +55,15 @@ static unsigned int get_image_size(void *head)
return ret;
}
static void *omap_xload_boot_nand(int offset)
static void *omap_xload_boot_nand(int offset, int part_size)
{
int ret;
int size;
void *to, *header;
struct cdev *cdev;
devfs_add_partition("nand0", offset, SZ_1M, DEVFS_PARTITION_FIXED, "x");
devfs_add_partition("nand0", offset, part_size,
DEVFS_PARTITION_FIXED, "x");
dev_add_bb_dev("x", "bbx");
header = read_image_head("bbx");
@ -104,14 +115,15 @@ static void *omap_xload_boot_mmc(void)
return buf;
}
static void *omap_xload_boot_spi(int offset)
static void *omap_xload_boot_spi(int offset, int part_size)
{
int ret;
int size;
void *to, *header;
struct cdev *cdev;
devfs_add_partition("m25p0", offset, SZ_1M, DEVFS_PARTITION_FIXED, "x");
devfs_add_partition("m25p0", offset, part_size,
DEVFS_PARTITION_FIXED, "x");
header = read_image_head("x");
if (header == NULL)
@ -163,7 +175,11 @@ static void *omap4_xload_boot_usb(void){
*/
static __noreturn int omap_xload(void)
{
int (*func)(void) = NULL;
int (*func)(void *) = NULL;
uint32_t *arg;
if (!barebox_part)
barebox_part = &default_part;
switch (bootsource_get())
{
@ -181,15 +197,18 @@ static __noreturn int omap_xload(void)
}
case BOOTSOURCE_NAND:
printf("booting from NAND\n");
func = omap_xload_boot_nand(SZ_128K);
func = omap_xload_boot_nand(barebox_part->nand_offset,
barebox_part->nand_size);
break;
case BOOTSOURCE_SPI:
printf("booting from SPI\n");
func = omap_xload_boot_spi(SZ_128K);
func = omap_xload_boot_spi(barebox_part->nor_offset,
barebox_part->nor_size);
break;
default:
printf("unknown boot source. Fall back to nand\n");
func = omap_xload_boot_nand(SZ_128K);
func = omap_xload_boot_nand(barebox_part->nand_offset,
barebox_part->nand_size);
break;
}
@ -198,12 +217,21 @@ static __noreturn int omap_xload(void)
while (1);
}
arg = (uint32_t *)&omap_bootinfo;
shutdown_barebox();
func();
func(arg);
while (1);
}
int omap_set_barebox_part(struct omap_barebox_part *part)
{
barebox_part = part;
return 0;
}
static int omap_set_xload(void)
{
barebox_main = omap_xload;