diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts index cecfc5a82..3ea1b5b05 100644 --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts +++ b/arch/arm/dts/imx27-phytec-phycard-s-rdk-bb.dts @@ -2,7 +2,7 @@ * Barebox specific DT overlay for Phytec PCA100 RDK */ -#include "imx27-phytec-phycard-s-rdk.dts" +#include / { chosen { diff --git a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts deleted file mode 100644 index 3c3964a99..000000000 --- a/arch/arm/dts/imx27-phytec-phycard-s-rdk.dts +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright 2012 Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -#include "imx27-phytec-phycard-s-som.dtsi" - -/ { - model = "Phytec pca100 rapid development kit"; - compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27"; - - display: display { - model = "Primeview-PD050VL1"; - native-mode = <&timing0>; - bits-per-pixel = <16>; /* non-standard but required */ - fsl,pcr = <0xf0c88080>; /* non-standard but required */ - display-timings { - timing0: 640x480 { - hactive = <640>; - vactive = <480>; - hback-porch = <112>; - hfront-porch = <36>; - hsync-len = <32>; - vback-porch = <33>; - vfront-porch = <33>; - vsync-len = <2>; - clock-frequency = <25000000>; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&fb { - display = <&display>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - adc@64 { - compatible = "maxim,max1037"; - vcc-supply = <®_3v3>; - reg = <0x64>; - }; -}; - -&iomuxc { - imx27-phycard-s-rdk { - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_owire1: owire1grp { - fsl,pins = < - MX27_PAD_RTCK__OWIRE 0x0 - >; - }; - - pinctrl_sdhc2: sdhc2grp { - fsl,pins = < - MX27_PAD_SD2_CLK__SD2_CLK 0x0 - MX27_PAD_SD2_CMD__SD2_CMD 0x0 - MX27_PAD_SD2_D0__SD2_D0 0x0 - MX27_PAD_SD2_D1__SD2_D1 0x0 - MX27_PAD_SD2_D2__SD2_D2 0x0 - MX27_PAD_SD2_D3__SD2_D3 0x0 - MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX27_PAD_UART1_TXD__UART1_TXD 0x0 - MX27_PAD_UART1_RXD__UART1_RXD 0x0 - MX27_PAD_UART1_CTS__UART1_CTS 0x0 - MX27_PAD_UART1_RTS__UART1_RTS 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX27_PAD_UART2_TXD__UART2_TXD 0x0 - MX27_PAD_UART2_RXD__UART2_RXD 0x0 - MX27_PAD_UART2_CTS__UART2_CTS 0x0 - MX27_PAD_UART2_RTS__UART2_RTS 0x0 - >; - }; - - pinctrl_uart3: uart3grp { - fsl,pins = < - MX27_PAD_UART3_TXD__UART3_TXD 0x0 - MX27_PAD_UART3_RXD__UART3_RXD 0x0 - MX27_PAD_UART3_CTS__UART3_CTS 0x0 - MX27_PAD_UART3_RTS__UART3_RTS 0x0 - >; - }; - }; -}; - -&owire { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_owire1>; - status = "okay"; -}; - -&sdhci2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sdhc2>; - cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart1 { - fsl,uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - fsl,uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - fsl,uart-has-rtscts; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; diff --git a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi deleted file mode 100644 index 1b6248079..000000000 --- a/arch/arm/dts/imx27-phytec-phycard-s-som.dtsi +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar - * and Markus Pargmann, Pengutronix - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "imx27.dtsi" - -/ { - model = "Phytec pca100"; - compatible = "phytec,imx27-pca100", "fsl,imx27"; - - memory { - reg = <0xa0000000 0x08000000>; /* 128MB */ - }; -}; - -&cspi1 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>, - <&gpio4 27 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; - - at24@52 { - compatible = "at,24c32"; - pagesize = <32>; - reg = <0x52>; - }; -}; - -&iomuxc { - imx27-phycard-s-som { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX27_PAD_SD3_CMD__FEC_TXD0 0x0 - MX27_PAD_SD3_CLK__FEC_TXD1 0x0 - MX27_PAD_ATA_DATA0__FEC_TXD2 0x0 - MX27_PAD_ATA_DATA1__FEC_TXD3 0x0 - MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0 - MX27_PAD_ATA_DATA3__FEC_RXD1 0x0 - MX27_PAD_ATA_DATA4__FEC_RXD2 0x0 - MX27_PAD_ATA_DATA5__FEC_RXD3 0x0 - MX27_PAD_ATA_DATA6__FEC_MDIO 0x0 - MX27_PAD_ATA_DATA7__FEC_MDC 0x0 - MX27_PAD_ATA_DATA8__FEC_CRS 0x0 - MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0 - MX27_PAD_ATA_DATA10__FEC_RXD0 0x0 - MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0 - MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0 - MX27_PAD_ATA_DATA13__FEC_COL 0x0 - MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0 - MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX27_PAD_I2C2_SDA__I2C2_SDA 0x0 - MX27_PAD_I2C2_SCL__I2C2_SCL 0x0 - >; - }; - - pinctrl_nfc: nfcgrp { - fsl,pins = < - MX27_PAD_NFRB__NFRB 0x0 - MX27_PAD_NFCLE__NFCLE 0x0 - MX27_PAD_NFWP_B__NFWP_B 0x0 - MX27_PAD_NFCE_B__NFCE_B 0x0 - MX27_PAD_NFALE__NFALE 0x0 - MX27_PAD_NFRE_B__NFRE_B 0x0 - MX27_PAD_NFWE_B__NFWE_B 0x0 - >; - }; - }; -}; - -&nfc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_nfc>; - nand-bus-width = <8>; - nand-ecc-mode = "hw"; - nand-on-flash-bbt; - status = "okay"; -};