dts: update to v4.7-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer
parent
0cf29e11ef
commit
86186c2322
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@ -39,43 +39,41 @@
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};
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&iomuxc {
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imx6qdl-tx6 {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
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MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
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MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
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MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
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MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
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MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
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MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
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MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
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>;
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};
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
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MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
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MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
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MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
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MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
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MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
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>;
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};
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pinctrl_usdhc4: usdhc4grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
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MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
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>;
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};
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pinctrl_usdhc4: usdhc4grp {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
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MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
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>;
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};
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};
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@ -0,0 +1,7 @@
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EZchip NPS Network Processor Platforms Device Tree Bindings
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---------------------------------------------------------------------------
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Appliance main board with NPS400 ASIC.
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Required root node properties:
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- compatible = "ezchip,arc-nps";
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@ -3,6 +3,7 @@ This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
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The ECC Manager counts and corrects single bit errors and counts/handles
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double bit errors which are uncorrectable.
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Cyclone5 and Arria5 ECC Manager
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Required Properties:
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- compatible : Should be "altr,socfpga-ecc-manager"
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- #address-cells: must be 1
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@ -47,3 +48,52 @@ Example:
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interrupts = <0 178 1>, <0 179 1>;
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};
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};
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Arria10 SoCFPGA ECC Manager
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The Arria10 SoC ECC Manager handles the IRQs for each peripheral
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in a shared register instead of individual IRQs like the Cyclone5
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and Arria5. Therefore the device tree is different as well.
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ecc-manager"
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- altr,sysgr-syscon : phandle to Arria10 System Manager Block
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containing the ECC manager registers.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- interrupts : Should be single bit error interrupt, then double bit error
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interrupt. Note the rising edge type.
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- ranges : standard definition, should translate from local addresses
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Subcomponents:
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L2 Cache ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-l2-ecc"
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- reg : Address and size for ECC error interrupt clear registers.
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On-Chip RAM ECC
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Required Properties:
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- compatible : Should be "altr,socfpga-a10-ocram-ecc"
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- reg : Address and size for ECC block registers.
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Example:
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eccmgr: eccmgr@ffd06000 {
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compatible = "altr,socfpga-a10-ecc-manager";
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altr,sysmgr-syscon = <&sysmgr>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 IRQ_TYPE_LEVEL_HIGH>;
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ranges;
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l2-ecc@ffd06010 {
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compatible = "altr,socfpga-a10-l2-ecc";
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reg = <0xffd06010 0x4>;
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};
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ocram-ecc@ff8c3000 {
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compatible = "altr,socfpga-a10-ocram-ecc";
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reg = <0xff8c3000 0x90>;
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};
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};
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@ -25,3 +25,6 @@ Board compatible values:
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- "tronsmart,vega-s95-pro", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-meta", "tronsmart,vega-s95" (Meson gxbb)
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- "tronsmart,vega-s95-telos", "tronsmart,vega-s95" (Meson gxbb)
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- "hardkernel,odroid-c2" (Meson gxbb)
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- "amlogic,p200" (Meson gxbb)
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- "amlogic,p201" (Meson gxbb)
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@ -93,6 +93,14 @@ Required nodes:
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a core-module with regs and the compatible strings
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"arm,core-module-versatile", "syscon"
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Optional nodes:
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- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
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board mounted, this has a separate system controller that is
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defined in this node.
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Required properties:
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compatible = "arm,versatile-ib2-syscon", "syscon"
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ARM RealView Boards
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-------------------
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The RealView boards cover tailored evaluation boards that are used to explore
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@ -41,6 +41,10 @@ compatible: must be one of:
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- "atmel,sama5d43"
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- "atmel,sama5d44"
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Chipid required properties:
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- compatible: Should be "atmel,sama5d2-chipid"
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- reg : Should contain registers location and length
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PIT Timer required properties:
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- compatible: Should be "atmel,at91sam9260-pit"
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- reg: Should contain registers location and length
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@ -147,6 +151,65 @@ Example:
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clocks = <&clk32k>;
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};
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SHDWC SAMA5D2-Compatible Shutdown Controller
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1) shdwc node
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required properties:
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- compatible: should be "atmel,sama5d2-shdwc".
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- reg: should contain registers location and length
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- clocks: phandle to input clock.
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- #address-cells: should be one. The cell is the wake-up input index.
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- #size-cells: should be zero.
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optional properties:
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- debounce-delay-us: minimum wake-up inputs debouncer period in
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microseconds. It's usually a board-related property.
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- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
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The node contains child nodes for each wake-up input that the platform uses.
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2) input nodes
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Wake-up input nodes are usually described in the "board" part of the Device
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Tree. Note also that input 0 is linked to the wake-up pin and is frequently
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used.
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Required properties:
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- reg: should contain the wake-up input index [0 - 15].
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Optional properties:
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- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
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by the child, forces the wake-up of the core power supply on a high level.
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The default is to be active low.
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Example:
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On the SoC side:
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shdwc@f8048010 {
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compatible = "atmel,sama5d2-shdwc";
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reg = <0xf8048010 0x10>;
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clocks = <&clk32k>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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};
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On the board side:
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shdwc@f8048010 {
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debounce-delay-us = <976>;
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input@0 {
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reg = <0>;
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};
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input@1 {
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reg = <1>;
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atmel,wakeup-active-high;
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};
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};
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Special Function Registers (SFR)
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Special Function Registers (SFR) manage specific aspects of the integrated
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@ -155,7 +218,7 @@ elsewhere.
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required properties:
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- compatible: Should be "atmel,<chip>-sfr", "syscon".
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<chip> can be "sama5d3" or "sama5d4".
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<chip> can be "sama5d3", "sama5d4" or "sama5d2".
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- reg: Should contain registers location and length
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sfr@f0038000 {
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@ -100,7 +100,7 @@ specific to ARM.
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"arm,cci-400-pmu,r0"
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"arm,cci-400-pmu,r1"
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"arm,cci-400-pmu" - DEPRECATED, permitted only where OS has
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secure acces to CCI registers
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secure access to CCI registers
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"arm,cci-500-pmu,r0"
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"arm,cci-550-pmu,r0"
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- reg:
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@ -19,6 +19,7 @@ its hardware characteristcs.
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- "arm,coresight-etm3x", "arm,primecell";
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- "arm,coresight-etm4x", "arm,primecell";
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- "qcom,coresight-replicator1x", "arm,primecell";
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- "arm,coresight-stm", "arm,primecell"; [1]
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* reg: physical base address and length of the register
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set(s) of the component.
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@ -36,6 +37,14 @@ its hardware characteristcs.
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layout using the generic DT graph presentation found in
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"bindings/graph.txt".
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* Additional required properties for System Trace Macrocells (STM):
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* reg: along with the physical base address and length of the register
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set as described above, another entry is required to describe the
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mapping of the extended stimulus port area.
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* reg-names: the only acceptable values are "stm-base" and
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"stm-stimulus-base", each corresponding to the areas defined in "reg".
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* Required properties for devices that don't show up on the AMBA bus, such as
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non-configurable replicators:
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@ -202,3 +211,22 @@ Example:
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};
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};
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};
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4. STM
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stm@20100000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0 0x20100000 0 0x1000>,
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<0 0x28000000 0 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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port {
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stm_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port2>;
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};
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};
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};
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[1]. There is currently two version of STM: STM32 and STM500. Both
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have the same HW interface and as such don't need an explicit binding name.
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@ -135,6 +135,10 @@ LS1043A ARMv8 based RDB Board
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Required root node properties:
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- compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
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LS1043A ARMv8 based QDS Board
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Required root node properties:
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- compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
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LS2080A ARMv8 based Simulator model
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Required root node properties:
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- compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
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|
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@ -1,29 +1,33 @@
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Hisilicon Platforms Device Tree Bindings
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----------------------------------------------------
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Hi6220 SoC
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Required root node properties:
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- compatible = "hisilicon,hi6220";
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Hi4511 Board
|
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Required root node properties:
|
||||
- compatible = "hisilicon,hi3620-hi4511";
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HiP04 D01 Board
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Hi6220 SoC
|
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Required root node properties:
|
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- compatible = "hisilicon,hip04-d01";
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HiP01 ca9x2 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip01-ca9x2";
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- compatible = "hisilicon,hi6220";
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HiKey Board
|
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Required root node properties:
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||||
- compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
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||||
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HiP01 ca9x2 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip01-ca9x2";
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||||
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HiP04 D01 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip04-d01";
|
||||
|
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HiP05 D02 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip05-d02";
|
||||
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||||
HiP06 D03 Board
|
||||
Required root node properties:
|
||||
- compatible = "hisilicon,hip06-d03";
|
||||
|
||||
Hisilicon system controller
|
||||
|
||||
Required properties:
|
||||
|
|
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|||
|
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@ -84,6 +84,12 @@ Optional properties:
|
|||
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (retain settings set by
|
||||
firmware)
|
||||
- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
|
||||
disable), <1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
|
||||
<1> (forcibly enable), property absent (OS specific behavior,
|
||||
preferrably retain firmware settings)
|
||||
|
||||
Example:
|
||||
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||||
|
|
|
|||
|
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@ -0,0 +1,35 @@
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|||
Marvell Armada AP806 System Controller
|
||||
======================================
|
||||
|
||||
The AP806 is one of the two core HW blocks of the Marvell Armada 7K/8K
|
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SoCs. It contains a system controller, which provides a number
|
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registers giving access to numerous features: clocks, pin-muxing and
|
||||
many other SoC configuration items. This DT binding allows to describe
|
||||
this system controller.
|
||||
|
||||
The Device Tree node representing the AP806 system controller provides
|
||||
a number of clocks:
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- 0: clock of CPU cluster 0
|
||||
- 1: clock of CPU cluster 1
|
||||
- 2: fixed PLL at 1200 Mhz
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||||
- 3: MSS clock, derived from the fixed PLL
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"marvell,ap806-system-controller", "syscon"
|
||||
- reg: register area of the AP806 system controller
|
||||
- #clock-cells: must be set to 1
|
||||
- clock-output-names: must be defined to:
|
||||
"ap-cpu-cluster-0", "ap-cpu-cluster-1", "ap-fixed", "ap-mss"
|
||||
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||||
Example:
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||||
|
||||
syscon: system-controller@6f4000 {
|
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compatible = "marvell,ap806-system-controller", "syscon";
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#clock-cells = <1>;
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||||
clock-output-names = "ap-cpu-cluster-0", "ap-cpu-cluster-1",
|
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"ap-fixed", "ap-mss";
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reg = <0x6f4000 0x1000>;
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||||
};
|
||||
|
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@ -0,0 +1,83 @@
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Marvell Armada CP110 System Controller 0
|
||||
========================================
|
||||
|
||||
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
|
||||
SoCs. It contains two sets of system control registers, System
|
||||
Controller 0 and System Controller 1. This Device Tree binding allows
|
||||
to describe the first system controller, which provides registers to
|
||||
configure various aspects of the SoC.
|
||||
|
||||
The Device Tree node representing this System Controller 0 provides a
|
||||
number of clocks:
|
||||
|
||||
- a set of core clocks
|
||||
- a set of gatable clocks
|
||||
|
||||
Those clocks can be referenced by other Device Tree nodes using two
|
||||
cells:
|
||||
- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
|
||||
gatable clocks.
|
||||
- The second cell identifies the particular core clock or gatable
|
||||
clocks.
|
||||
|
||||
The following clocks are available:
|
||||
- Core clocks
|
||||
- 0 0 APLL
|
||||
- 0 1 PPv2 core
|
||||
- 0 2 EIP
|
||||
- 0 3 Core
|
||||
- 0 4 NAND core
|
||||
- Gatable clocks
|
||||
- 1 0 Audio
|
||||
- 1 1 Comm Unit
|
||||
- 1 2 NAND
|
||||
- 1 3 PPv2
|
||||
- 1 4 SDIO
|
||||
- 1 5 MG Domain
|
||||
- 1 6 MG Core
|
||||
- 1 7 XOR1
|
||||
- 1 8 XOR0
|
||||
- 1 9 GOP DP
|
||||
- 1 11 PCIe x1 0
|
||||
- 1 12 PCIe x1 1
|
||||
- 1 13 PCIe x4
|
||||
- 1 14 PCIe / XOR
|
||||
- 1 15 SATA
|
||||
- 1 16 SATA USB
|
||||
- 1 17 Main
|
||||
- 1 18 SD/MMC
|
||||
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
|
||||
- 1 22 USB3H0
|
||||
- 1 23 USB3H1
|
||||
- 1 24 USB3 Device
|
||||
- 1 25 EIP150
|
||||
- 1 26 EIP197
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: must be:
|
||||
"marvell,cp110-system-controller0", "syscon";
|
||||
- reg: register area of the CP110 system controller 0
|
||||
- #clock-cells: must be set to 2
|
||||
- core-clock-output-names must be set to:
|
||||
"cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core"
|
||||
- gate-clock-output-names must be set to:
|
||||
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
|
||||
Example:
|
||||
|
||||
cpm_syscon0: system-controller@440000 {
|
||||
compatible = "marvell,cp110-system-controller0", "syscon";
|
||||
reg = <0x440000 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
core-clock-output-names = "cpm-apll", "cpm-ppv2-core", "cpm-eip", "cpm-core", "cpm-nand-core";
|
||||
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
|
||||
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
|
||||
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
|
||||
"cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
|
||||
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
|
||||
};
|
||||
|
|
@ -42,7 +42,8 @@ Examples:
|
|||
Consumer:
|
||||
========
|
||||
See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and
|
||||
Documentation/devicetree/bindings/arm/gic.txt for further details.
|
||||
Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for
|
||||
further details.
|
||||
|
||||
An interrupt consumer on an SoC using crossbar will use:
|
||||
interrupts = <GIC_SPI request_number interrupt_level>
|
||||
|
|
|
|||
|
|
@ -133,6 +133,9 @@ Boards:
|
|||
- AM335X Bone : Low cost community board
|
||||
compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3"
|
||||
|
||||
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
|
||||
compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3"
|
||||
|
||||
- AM335X OrionLXm : Substation Automation Platform
|
||||
compatible = "novatech,am335x-lxm", "ti,am33xx"
|
||||
|
||||
|
|
@ -169,6 +172,9 @@ Boards:
|
|||
- AM57XX SBC-AM57x
|
||||
compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- AM5728 IDK
|
||||
compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
- DRA742 EVM: Software Development Board for DRA742
|
||||
compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
Oxford Semiconductor OXNAS SoCs Family device tree bindings
|
||||
-------------------------------------------
|
||||
|
||||
Boards with the OX810SE SoC shall have the following properties:
|
||||
Required root node property:
|
||||
compatible: "oxsemi,ox810se"
|
||||
|
||||
Board compatible values:
|
||||
- "wd,mbwe" (OX810SE)
|
||||
|
|
@ -22,10 +22,11 @@ Required properties:
|
|||
"arm,arm11mpcore-pmu"
|
||||
"arm,arm1176-pmu"
|
||||
"arm,arm1136-pmu"
|
||||
"brcm,vulcan-pmu"
|
||||
"cavium,thunder-pmu"
|
||||
"qcom,scorpion-pmu"
|
||||
"qcom,scorpion-mp-pmu"
|
||||
"qcom,krait-pmu"
|
||||
"cavium,thunder-pmu"
|
||||
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
|
||||
interrupt (PPI) then 1 interrupt should be specified.
|
||||
|
||||
|
|
|
|||
|
|
@ -39,6 +39,10 @@ Rockchip platforms device tree bindings
|
|||
Required root node properties:
|
||||
- compatible = "netxeon,r89", "rockchip,rk3288";
|
||||
|
||||
- GeekBuying GeekBox:
|
||||
Required root node properties:
|
||||
- compatible = "geekbuying,geekbox", "rockchip,rk3368";
|
||||
|
||||
- Google Brain (dev-board):
|
||||
Required root node properties:
|
||||
- compatible = "google,veyron-brain-rev0", "google,veyron-brain",
|
||||
|
|
@ -87,6 +91,10 @@ Rockchip platforms device tree bindings
|
|||
"google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
|
||||
"google,veyron-speedy", "google,veyron", "rockchip,rk3288";
|
||||
|
||||
- mqmaker MiQi:
|
||||
Required root node properties:
|
||||
- compatible = "mqmaker,miqi", "rockchip,rk3288";
|
||||
|
||||
- Rockchip RK3368 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368";
|
||||
|
|
@ -97,4 +105,8 @@ Rockchip platforms device tree bindings
|
|||
|
||||
- Rockchip RK3228 Evaluation board:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
- Rockchip RK3399 evb:
|
||||
Required root node properties:
|
||||
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
|
||||
|
|
|
|||
|
|
@ -2,6 +2,8 @@
|
|||
|
||||
Required root node properties:
|
||||
- compatible = should be one or more of the following.
|
||||
- "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module.
|
||||
- "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board.
|
||||
- "samsung,monk" - for Exynos3250-based Samsung Simband board.
|
||||
- "samsung,rinato" - for Exynos3250-based Samsung Gear2 board.
|
||||
- "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board.
|
||||
|
|
|
|||
|
|
@ -6,4 +6,4 @@ few properties of different peripheral controllers.
|
|||
misc node required properties:
|
||||
|
||||
- compatible Should be "st,spear1340-misc", "syscon".
|
||||
- reg: Address range of misc space upto 8K
|
||||
- reg: Address range of misc space up to 8K
|
||||
|
|
|
|||
|
|
@ -1,16 +1,20 @@
|
|||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
== Power Management Controller Node ==
|
||||
|
||||
The PMC block interacts with an external Power Management Unit. The PMC
|
||||
mostly controls the entry and exit of the system from different sleep
|
||||
modes. It provides power-gating controllers for SoC and CPU power-islands.
|
||||
|
||||
Required properties:
|
||||
- name : Should be pmc
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-pmc". For Tegra30,
|
||||
must contain "nvidia,tegra30-pmc". For Tegra114, must contain
|
||||
"nvidia,tegra114-pmc". For Tegra124, must contain "nvidia,tegra124-pmc".
|
||||
Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the
|
||||
above, where <chip> is tegra132.
|
||||
- compatible : Should contain one of the following:
|
||||
For Tegra20 must contain "nvidia,tegra20-pmc".
|
||||
For Tegra30 must contain "nvidia,tegra30-pmc".
|
||||
For Tegra114 must contain "nvidia,tegra114-pmc"
|
||||
For Tegra124 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra132 must contain "nvidia,tegra124-pmc"
|
||||
For Tegra210 must contain "nvidia,tegra210-pmc"
|
||||
- reg : Offset and length of the register set for the device
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
|
|
@ -68,6 +72,11 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
|
|||
Defaults to 0. Valid values are described in section 12.5.2
|
||||
"Pinmux Support" of the Tegra4 Technical Reference Manual.
|
||||
|
||||
Optional nodes:
|
||||
- powergates : This node contains a hierarchy of power domain nodes, which
|
||||
should match the powergates on the Tegra SoC. See "Powergate
|
||||
Nodes" below.
|
||||
|
||||
Example:
|
||||
|
||||
/ SoC dts including file
|
||||
|
|
@ -113,3 +122,76 @@ pmc@7000f400 {
|
|||
};
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
== Powergate Nodes ==
|
||||
|
||||
Each of the powergate nodes represents a power-domain on the Tegra SoC
|
||||
that can be power-gated by the Tegra PMC. The name of the powergate node
|
||||
should be one of the below. Note that not every powergate is applicable
|
||||
to all Tegra devices and the following list shows which powergates are
|
||||
applicable to which devices. Please refer to the Tegra TRM for more
|
||||
details on the various powergates.
|
||||
|
||||
Name Description Devices Applicable
|
||||
3d 3D Graphics Tegra20/114/124/210
|
||||
3d0 3D Graphics 0 Tegra30
|
||||
3d1 3D Graphics 1 Tegra30
|
||||
aud Audio Tegra210
|
||||
dfd Debug Tegra210
|
||||
dis Display A Tegra114/124/210
|
||||
disb Display B Tegra114/124/210
|
||||
heg 2D Graphics Tegra30/114/124/210
|
||||
iram Internal RAM Tegra124/210
|
||||
mpe MPEG Encode All
|
||||
nvdec NVIDIA Video Decode Engine Tegra210
|
||||
nvjpg NVIDIA JPEG Engine Tegra210
|
||||
pcie PCIE Tegra20/30/124/210
|
||||
sata SATA Tegra30/124/210
|
||||
sor Display interfaces Tegra124/210
|
||||
ve2 Video Encode Engine 2 Tegra210
|
||||
venc Video Encode Engine All
|
||||
vdec Video Decode Engine Tegra20/30/114/124
|
||||
vic Video Imaging Compositor Tegra124/210
|
||||
xusba USB Partition A Tegra114/124/210
|
||||
xusbb USB Partition B Tegra114/124/210
|
||||
xusbc USB Partition C Tegra114/124/210
|
||||
|
||||
Required properties:
|
||||
- clocks: Must contain an entry for each clock required by the PMC for
|
||||
controlling a power-gate. See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each reset required by the PMC for
|
||||
controlling a power-gate. See ../reset/reset.txt for details.
|
||||
- #power-domain-cells: Must be 0.
|
||||
|
||||
Example:
|
||||
|
||||
pmc: pmc@7000e400 {
|
||||
compatible = "nvidia,tegra210-pmc";
|
||||
reg = <0x0 0x7000e400 0x0 0x400>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
|
||||
clock-names = "pclk", "clk32k_in";
|
||||
|
||||
powergates {
|
||||
pd_audio: aud {
|
||||
clocks = <&tegra_car TEGRA210_CLK_APE>,
|
||||
<&tegra_car TEGRA210_CLK_APB2APE>;
|
||||
resets = <&tegra_car 198>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
== Powergate Clients ==
|
||||
|
||||
Hardware blocks belonging to a power domain should contain a "power-domains"
|
||||
property that is a phandle pointing to the corresponding powergate node.
|
||||
|
||||
Example:
|
||||
|
||||
adma: adma@702e2000 {
|
||||
...
|
||||
power-domains = <&pd_audio>;
|
||||
...
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ scu:
|
|||
see binding for arm/scu.txt
|
||||
|
||||
interrupt-controller:
|
||||
see binding for arm/gic.txt
|
||||
see binding for interrupt-controller/arm,gic.txt
|
||||
|
||||
timer:
|
||||
see binding for arm/twd.txt
|
||||
|
|
|
|||
|
|
@ -1,29 +0,0 @@
|
|||
btmrvl
|
||||
------
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : must be "btmrvl,cfgdata"
|
||||
|
||||
Optional properties:
|
||||
|
||||
- btmrvl,cal-data : Calibration data downloaded to the device during
|
||||
initialization. This is an array of 28 values(u8).
|
||||
|
||||
- btmrvl,gpio-gap : gpio and gap (in msecs) combination to be
|
||||
configured.
|
||||
|
||||
Example:
|
||||
|
||||
GPIO pin 13 is configured as a wakeup source and GAP is set to 100 msecs
|
||||
in below example.
|
||||
|
||||
btmrvl {
|
||||
compatible = "btmrvl,cfgdata";
|
||||
|
||||
btmrvl,cal-data = /bits/ 8 <
|
||||
0x37 0x01 0x1c 0x00 0xff 0xff 0xff 0xff 0x01 0x7f 0x04 0x02
|
||||
0x00 0x00 0xba 0xce 0xc0 0xc6 0x2d 0x00 0x00 0x00 0x00 0x00
|
||||
0x00 0x00 0xf0 0x00>;
|
||||
btmrvl,gpio-gap = <0x0d64>;
|
||||
};
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
* Clock bindings for Axis ARTPEC-6 chip
|
||||
|
||||
The bindings are based on the clock provider binding in
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are two external inputs to the main clock controller which should be
|
||||
provided using the common clock bindings.
|
||||
- "sys_refclk": External 50 Mhz oscillator (required)
|
||||
- "i2s_refclk": Alternate audio reference clock (optional).
|
||||
|
||||
Main clock controller
|
||||
---------------------
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
|
||||
- compatible: Should be "axis,artpec6-clkctrl"
|
||||
- reg: Must contain the base address and length of the system controller
|
||||
- clocks: Must contain a phandle entry for each clock in clock-names
|
||||
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
|
||||
ones are the audio reference clock ("i2s_refclk") and the audio fractional
|
||||
dividers ("frac_clk0" and "frac_clk1").
|
||||
|
||||
Examples:
|
||||
|
||||
ext_clk: ext_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl@f8000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "axis,artpec6-clkctrl";
|
||||
reg = <0xf8000000 0x48>;
|
||||
clocks = <&ext_clk>;
|
||||
clock-names = "sys_refclk";
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
Binding for the AXS10X I2S PLL clock
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "snps,axs10x-i2s-pll-clock"
|
||||
- reg : address and length of the I2S PLL register set.
|
||||
- clocks: shall be the input parent clock phandle for the PLL.
|
||||
- #clock-cells: from common clock binding; Should always be set to 0.
|
||||
|
||||
Example:
|
||||
pll_clock: pll_clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
i2s_clock@100a0 {
|
||||
compatible = "snps,axs10x-i2s-pll-clock";
|
||||
reg = <0x100a0 0x10>;
|
||||
clocks = <&pll_clock>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
* Hisilicon Hi3519 Clock and Reset Generator(CRG)
|
||||
|
||||
The Hi3519 CRG module provides clock and reset signals to various
|
||||
controllers within the SoC.
|
||||
|
||||
This binding uses the following bindings:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following.
|
||||
- "hisilicon,hi3519-crg" - controller compatible with Hi3519 SoC.
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All these identifier could be found in <dt-bindings/clock/hi3519-clock.h>.
|
||||
|
||||
- #reset-cells: should be 2.
|
||||
|
||||
A reset signal can be controlled by writing a bit register in the CRG module.
|
||||
The reset specifier consists of two cells. The first cell represents the
|
||||
register offset relative to the base address. The second cell represents the
|
||||
bit index in the register.
|
||||
|
||||
Example: CRG nodes
|
||||
CRG: clock-reset-controller@12010000 {
|
||||
compatible = "hisilicon,hi3519-crg";
|
||||
reg = <0x12010000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
Example: consumer nodes
|
||||
i2c0: i2c@12110000 {
|
||||
compatible = "hisilicon,hi3519-i2c";
|
||||
reg = <0x12110000 0x1000>;
|
||||
clocks = <&CRG HI3519_I2C0_RST>;
|
||||
resets = <&CRG 0xe4 0>;
|
||||
};
|
||||
|
|
@ -94,6 +94,7 @@ clocks and IDs.
|
|||
csi_sel 79
|
||||
iim_gate 80
|
||||
gpu2d_gate 81
|
||||
ckli_gate 82
|
||||
|
||||
Examples:
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
Microchip PIC32 Clock Controller Binding
|
||||
----------------------------------------
|
||||
Microchip clock controller is consists of few oscillators, PLL, multiplexer
|
||||
and few divider modules.
|
||||
|
||||
This binding uses common clock bindings.
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be "microchip,pic32mzda-clk".
|
||||
- reg: shall contain base address and length of clock registers.
|
||||
- #clock-cells: shall be 1.
|
||||
|
||||
Optional properties:
|
||||
- microchip,pic32mzda-sosc: shall be added only if platform has
|
||||
secondary oscillator connected.
|
||||
|
||||
Example:
|
||||
rootclk: clock-controller@1f801200 {
|
||||
compatible = "microchip,pic32mzda-clk";
|
||||
reg = <0x1f801200 0x200>;
|
||||
#clock-cells = <1>;
|
||||
/* optional */
|
||||
microchip,pic32mzda-sosc;
|
||||
};
|
||||
|
||||
|
||||
The clock consumer shall specify the desired clock-output of the clock
|
||||
controller (as defined in [2]) by specifying output-id in its "clock"
|
||||
phandle cell.
|
||||
[2] include/dt-bindings/clock/microchip,pic32-clock.h
|
||||
|
||||
For example for UART2:
|
||||
uart2: serial@2 {
|
||||
compatible = "microchip,pic32mzda-uart";
|
||||
reg = <>;
|
||||
interrupts = <>;
|
||||
clocks = <&rootclk PB2CLK>;
|
||||
};
|
||||
|
|
@ -50,7 +50,7 @@ Required properties for I2C mode:
|
|||
|
||||
Example:
|
||||
|
||||
clock@0,70110000 {
|
||||
clock@70110000 {
|
||||
compatible = "nvidia,tegra124-dfll";
|
||||
reg = <0 0x70110000 0 0x100>, /* DFLL control */
|
||||
<0 0x70110000 0 0x100>, /* I2C output control */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
Oxford Semiconductor OXNAS SoC Family Standard Clocks
|
||||
================================================
|
||||
|
||||
Please also refer to clock-bindings.txt in this directory for common clock
|
||||
bindings usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "oxsemi,ox810se-stdclk"
|
||||
- #clock-cells: 1, see below
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"
|
||||
|
||||
For OX810SE, the clock indices are :
|
||||
- 0: LEON
|
||||
- 1: DMA_SGDMA
|
||||
- 2: CIPHER
|
||||
- 3: SATA
|
||||
- 4: AUDIO
|
||||
- 5: USBMPH
|
||||
- 6: ETHA
|
||||
- 7: PCIA
|
||||
- 8: NAND
|
||||
|
||||
example:
|
||||
|
||||
sys: sys-ctrl@000000 {
|
||||
compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
|
||||
reg = <0x000000 0x100000>;
|
||||
|
||||
stdclk: stdclk {
|
||||
compatible = "oxsemi,ox810se-stdclk";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -16,7 +16,7 @@ Required Properties:
|
|||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ Required Properties:
|
|||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changable, due to the missing pll lock status.
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
* Rockchip RK3399 Clock and Reset Unit
|
||||
|
||||
The RK3399 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: PMU for CRU should be "rockchip,rk3399-pmucru"
|
||||
- compatible: CRU should be "rockchip,rk3399-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "xin32k" - rtc clock - optional,
|
||||
- "clkin_gmac" - external GMAC clock - optional,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "pclkin_cif" - external ISP clock - optional,
|
||||
- "clk_usbphy0_480m" - output clock of the pll in the usbphy0
|
||||
- "clk_usbphy1_480m" - output clock of the pll in the usbphy1
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
pmucru: pmu-clock-controller@ff750000 {
|
||||
compatible = "rockchip,rk3399-pmucru";
|
||||
reg = <0x0 0xff750000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
cru: clock-controller@ff760000 {
|
||||
compatible = "rockchip,rk3399-cru";
|
||||
reg = <0x0 0xff760000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff1a0000 {
|
||||
compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xff180000 0x0 0x100>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
|
@ -40,7 +40,7 @@ address is common of all subnode.
|
|||
};
|
||||
|
||||
This binding uses the common clock binding[1].
|
||||
Each subnode should use the binding discribe in [2]..[7]
|
||||
Each subnode should use the binding described in [2]..[7]
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/st,clkgen-divmux.txt
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ Required properties:
|
|||
"allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
|
||||
"allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
|
||||
"allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
|
||||
"allwinner,sun4i-a10-pll3-clk" - for the video PLL clock on A10
|
||||
"allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
|
||||
"allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
|
||||
"allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
|
||||
|
|
@ -63,7 +64,9 @@ Required properties:
|
|||
"allwinner,sun8i-a83t-bus-gates-clk" - for the bus gates on A83T
|
||||
"allwinner,sun8i-h3-bus-gates-clk" - for the bus gates on H3
|
||||
"allwinner,sun9i-a80-apbs-gates-clk" - for the APBS gates on A80
|
||||
"allwinner,sun4i-a10-display-clk" - for the display clocks on the A10
|
||||
"allwinner,sun4i-a10-dram-gates-clk" - for the DRAM gates on A10
|
||||
"allwinner,sun5i-a13-dram-gates-clk" - for the DRAM gates on A13
|
||||
"allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
|
||||
"allwinner,sun4i-a10-mmc-clk" - for the MMC clock
|
||||
"allwinner,sun9i-a80-mmc-clk" - for mmc module clocks on A80
|
||||
|
|
@ -73,6 +76,8 @@ Required properties:
|
|||
"allwinner,sun8i-a23-mbus-clk" - for the MBUS clock on A23
|
||||
"allwinner,sun7i-a20-out-clk" - for the external output clocks
|
||||
"allwinner,sun7i-a20-gmac-clk" - for the GMAC clock module on A20/A31
|
||||
"allwinner,sun4i-a10-tcon-ch0-clk" - for the TCON channel 0 clock on the A10
|
||||
"allwinner,sun4i-a10-tcon-ch1-clk" - for the TCON channel 1 clock on the A10
|
||||
"allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20
|
||||
"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
|
||||
"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
|
||||
|
|
@ -81,6 +86,7 @@ Required properties:
|
|||
"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
|
||||
"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
|
||||
"allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
|
||||
"allwinner,sun6i-a31-display-clk" - for the display clocks
|
||||
|
||||
Required properties for all clocks:
|
||||
- reg : shall be the control register address for the clock.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
Freescale Security Controller (SCC)
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,imx25-scc".
|
||||
- reg : Should contain register location and length.
|
||||
- interrupts : Should contain interrupt numbers for SCM IRQ and SMN IRQ.
|
||||
- interrupt-names : Should specify the names "scm" and "smn" for the
|
||||
SCM IRQ and SMN IRQ.
|
||||
- clocks: Should contain the clock driving the SCC core.
|
||||
- clock-names: Should be set to "ipg".
|
||||
|
||||
Example:
|
||||
|
||||
scc: crypto@53fac000 {
|
||||
compatible = "fsl,imx25-scc";
|
||||
reg = <0x53fac000 0x4000>;
|
||||
clocks = <&clks 111>;
|
||||
clock-names = "ipg";
|
||||
interrupts = <49>, <50>;
|
||||
interrupt-names = "scm", "smn";
|
||||
};
|
||||
|
|
@ -23,10 +23,8 @@ Required properties:
|
|||
- "samsung,exynos4210-secss" for Exynos4210, Exynos4212, Exynos4412, Exynos5250,
|
||||
Exynos5260 and Exynos5420 SoCs.
|
||||
- reg : Offset and length of the register set for the module
|
||||
- interrupts : interrupt specifiers of SSS module interrupts, should contain
|
||||
following entries:
|
||||
- first : feed control interrupt (required for all variants),
|
||||
- second : hash interrupt (required only for samsung,s5pv210-secss).
|
||||
- interrupts : interrupt specifiers of SSS module interrupts (one feed
|
||||
control interrupt).
|
||||
|
||||
- clocks : list of clock phandle and specifier pairs for all clocks listed in
|
||||
clock-names property.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,26 @@
|
|||
|
||||
* Samsung Exynos NoC (Network on Chip) Probe device
|
||||
|
||||
The Samsung Exynos542x SoC has NoC (Network on Chip) Probe for NoC bus.
|
||||
NoC provides the primitive values to get the performance data. The packets
|
||||
that the Network on Chip (NoC) probes detects are transported over
|
||||
the network infrastructure to observer units. You can configure probes to
|
||||
capture packets with header or data on the data request response network,
|
||||
or as traffic debug or statistic collectors. Exynos542x bus has multiple
|
||||
NoC probes to provide bandwidth information about behavior of the SoC
|
||||
that you can use while analyzing system performance.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "samsung,exynos5420-nocp"
|
||||
- reg: physical base address of each NoC Probe and length of memory mapped region.
|
||||
|
||||
Optional properties:
|
||||
- clock-names : the name of clock used by the NoC Probe, "nocp"
|
||||
- clocks : phandles for clock specified in "clock-names" property
|
||||
|
||||
Example : NoC Probe nodes in Device Tree are listed below.
|
||||
|
||||
nocp_mem0_0: nocp@10CA1000 {
|
||||
compatible = "samsung,exynos5420-nocp";
|
||||
reg = <0x10CA1000 0x200>;
|
||||
};
|
||||
|
|
@ -0,0 +1,409 @@
|
|||
* Generic Exynos Bus frequency device
|
||||
|
||||
The Samsung Exynos SoC has many buses for data transfer between DRAM
|
||||
and sub-blocks in SoC. Most Exynos SoCs share the common architecture
|
||||
for buses. Generally, each bus of Exynos SoC includes a source clock
|
||||
and a power line, which are able to change the clock frequency
|
||||
of the bus in runtime. To monitor the usage of each bus in runtime,
|
||||
the driver uses the PPMU (Platform Performance Monitoring Unit), which
|
||||
is able to measure the current load of sub-blocks.
|
||||
|
||||
The Exynos SoC includes the various sub-blocks which have the each AXI bus.
|
||||
The each AXI bus has the owned source clock but, has not the only owned
|
||||
power line. The power line might be shared among one more sub-blocks.
|
||||
So, we can divide into two type of device as the role of each sub-block.
|
||||
There are two type of bus devices as following:
|
||||
- parent bus device
|
||||
- passive bus device
|
||||
|
||||
Basically, parent and passive bus device share the same power line.
|
||||
The parent bus device can only change the voltage of shared power line
|
||||
and the rest bus devices (passive bus device) depend on the decision of
|
||||
the parent bus device. If there are three blocks which share the VDD_xxx
|
||||
power line, Only one block should be parent device and then the rest blocks
|
||||
should depend on the parent device as passive device.
|
||||
|
||||
VDD_xxx |--- A block (parent)
|
||||
|--- B block (passive)
|
||||
|--- C block (passive)
|
||||
|
||||
There are a little different composition among Exynos SoC because each Exynos
|
||||
SoC has different sub-blocks. Therefore, such difference should be specified
|
||||
in devicetree file instead of each device driver. In result, this driver
|
||||
is able to support the bus frequency for all Exynos SoCs.
|
||||
|
||||
Required properties for all bus devices:
|
||||
- compatible: Should be "samsung,exynos-bus".
|
||||
- clock-names : the name of clock used by the bus, "bus".
|
||||
- clocks : phandles for clock specified in "clock-names" property.
|
||||
- operating-points-v2: the OPP table including frequency/voltage information
|
||||
to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
|
||||
|
||||
Required properties only for parent bus device:
|
||||
- vdd-supply: the regulator to provide the buses with the voltage.
|
||||
- devfreq-events: the devfreq-event device to monitor the current utilization
|
||||
of buses.
|
||||
|
||||
Required properties only for passive bus device:
|
||||
- devfreq: the parent bus device.
|
||||
|
||||
Optional properties only for parent bus device:
|
||||
- exynos,saturation-ratio: the percentage value which is used to calibrate
|
||||
the performance count against total cycle count.
|
||||
- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
|
||||
which is used to calculate the max voltage.
|
||||
|
||||
Detailed correlation between sub-blocks and power line according to Exynos SoC:
|
||||
- In case of Exynos3250, there are two power line as following:
|
||||
VDD_MIF |--- DMC
|
||||
|
||||
VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC
|
||||
|--- G3D
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- FSYS
|
||||
|--- LCD0
|
||||
|--- PERIR
|
||||
|--- ISP
|
||||
|--- CAM
|
||||
|
||||
- In case of Exynos4210, there is one power line as following:
|
||||
VDD_INT |--- DMC (parent device)
|
||||
|--- LEFTBUS
|
||||
|--- PERIL
|
||||
|--- MFC(L)
|
||||
|--- G3D
|
||||
|--- TV
|
||||
|--- LCD0
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- MFC(R)
|
||||
|--- CAM
|
||||
|--- FSYS
|
||||
|--- GPS
|
||||
|--- LCD0
|
||||
|--- LCD1
|
||||
|
||||
- In case of Exynos4x12, there are two power line as following:
|
||||
VDD_MIF |--- DMC
|
||||
|
||||
VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC(L)
|
||||
|--- G3D
|
||||
|--- TV
|
||||
|--- IMAGE
|
||||
|--- RIGHTBUS
|
||||
|--- PERIR
|
||||
|--- MFC(R)
|
||||
|--- CAM
|
||||
|--- FSYS
|
||||
|--- GPS
|
||||
|--- LCD0
|
||||
|--- ISP
|
||||
|
||||
- In case of Exynos5422, there are two power line as following:
|
||||
VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
|
||||
|--- DREX 1
|
||||
|
||||
VDD_INT |--- NoC_Core (parent device)
|
||||
|--- G2D
|
||||
|--- G3D
|
||||
|--- DISP1
|
||||
|--- NoC_WCORE
|
||||
|--- GSCL
|
||||
|--- MSCL
|
||||
|--- ISP
|
||||
|--- MFC
|
||||
|--- GEN
|
||||
|--- PERIS
|
||||
|--- PERIC
|
||||
|--- FSYS
|
||||
|--- FSYS2
|
||||
|
||||
Example1:
|
||||
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
|
||||
power line (regulator). The MIF (Memory Interface) AXI bus is used to
|
||||
transfer data between DRAM and CPU and uses the VDD_MIF regulator.
|
||||
|
||||
- MIF (Memory Interface) block
|
||||
: VDD_MIF |--- DMC (Dynamic Memory Controller)
|
||||
|
||||
- INT (Internal) block
|
||||
: VDD_INT |--- LEFTBUS (parent device)
|
||||
|--- PERIL
|
||||
|--- MFC
|
||||
|--- G3D
|
||||
|--- RIGHTBUS
|
||||
|--- FSYS
|
||||
|--- LCD0
|
||||
|--- PERIR
|
||||
|--- ISP
|
||||
|--- CAM
|
||||
|
||||
- MIF bus's frequency/voltage table
|
||||
-----------------------
|
||||
|Lv| Freq | Voltage |
|
||||
-----------------------
|
||||
|L1| 50000 |800000 |
|
||||
|L2| 100000 |800000 |
|
||||
|L3| 134000 |800000 |
|
||||
|L4| 200000 |825000 |
|
||||
|L5| 400000 |875000 |
|
||||
-----------------------
|
||||
|
||||
- INT bus's frequency/voltage table
|
||||
----------------------------------------------------------
|
||||
|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
|
||||
| name| |LCD0 | | | || |
|
||||
| | |FSYS | | | || |
|
||||
| | |MFC | | | || |
|
||||
----------------------------------------------------------
|
||||
|Mode |*parent|passive |passive|passive|passive|| |
|
||||
----------------------------------------------------------
|
||||
|Lv |Frequency ||Voltage |
|
||||
----------------------------------------------------------
|
||||
|L1 |50000 |50000 |50000 |50000 |50000 ||900000 |
|
||||
|L2 |80000 |80000 |80000 |80000 |80000 ||900000 |
|
||||
|L3 |100000 |100000 |100000 |100000 |100000 ||1000000 |
|
||||
|L4 |134000 |134000 |200000 |200000 | ||1000000 |
|
||||
|L5 |200000 |200000 |400000 |300000 | ||1000000 |
|
||||
----------------------------------------------------------
|
||||
|
||||
Example2 :
|
||||
The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
|
||||
is listed below:
|
||||
|
||||
bus_dmc: bus_dmc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu_dmc CLK_DIV_DMC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_dmc_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_dmc_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <825000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
opp-microvolt = <875000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_leftbus: bus_leftbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_GDL>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_rightbus: bus_rightbus {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_GDR>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_lcd0: bus_lcd0 {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_160>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_fsys: bus_fsys {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_200>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mcuisp: bus_mcuisp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_mcuisp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_isp: bus_isp {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_266>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_isp_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_peril: bus_peril {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_DIV_ACLK_100>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_peril_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_mfc: bus_mfc {
|
||||
compatible = "samsung,exynos-bus";
|
||||
clocks = <&cmu CLK_SCLK_MFC>;
|
||||
clock-names = "bus";
|
||||
operating-points-v2 = <&bus_leftbus_opp_table>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
bus_leftbus_opp_table: opp_table1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
opp-microvolt = <900000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
opp@134000000 {
|
||||
opp-hz = /bits/ 64 <134000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
opp-microvolt = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_mcuisp_opp_table: opp_table2 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp@400000000 {
|
||||
opp-hz = /bits/ 64 <400000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_isp_opp_table: opp_table3 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
opp@200000000 {
|
||||
opp-hz = /bits/ 64 <200000000>;
|
||||
};
|
||||
opp@300000000 {
|
||||
opp-hz = /bits/ 64 <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
bus_peril_opp_table: opp_table4 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp@50000000 {
|
||||
opp-hz = /bits/ 64 <50000000>;
|
||||
};
|
||||
opp@80000000 {
|
||||
opp-hz = /bits/ 64 <80000000>;
|
||||
};
|
||||
opp@100000000 {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Usage case to handle the frequency and voltage of bus on runtime
|
||||
in exynos3250-rinato.dts is listed below:
|
||||
|
||||
&bus_dmc {
|
||||
devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
|
||||
vdd-supply = <&buck1_reg>; /* VDD_MIF */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_leftbus {
|
||||
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
|
||||
vdd-supply = <&buck3_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_rightbus {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_lcd0 {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_fsys {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mcuisp {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_isp {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_peril {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bus_mfc {
|
||||
devfreq = <&bus_leftbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -35,12 +35,22 @@ Optional properties for HDMI:
|
|||
as an interrupt/status bit in the HDMI controller
|
||||
itself). See bindings/pinctrl/brcm,bcm2835-gpio.txt
|
||||
|
||||
Required properties for DPI:
|
||||
- compatible: Should be "brcm,bcm2835-dpi"
|
||||
- reg: Physical base address and length of the registers
|
||||
- clocks: a) core: The core clock the unit runs on
|
||||
b) pixel: The pixel clock that feeds the pixelvalve
|
||||
- port: Port node with a single endpoint connecting to the panel
|
||||
device, as defined in [1]
|
||||
|
||||
Required properties for V3D:
|
||||
- compatible: Should be "brcm,bcm2835-v3d"
|
||||
- reg: Physical base address and length of the V3D's registers
|
||||
- interrupts: The interrupt number
|
||||
See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
|
||||
|
||||
[1] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
Example:
|
||||
pixelvalve@7e807000 {
|
||||
compatible = "brcm,bcm2835-pixelvalve2";
|
||||
|
|
@ -66,6 +76,22 @@ hdmi: hdmi@7e902000 {
|
|||
clock-names = "pixel", "hdmi";
|
||||
};
|
||||
|
||||
dpi: dpi@7e208000 {
|
||||
compatible = "brcm,bcm2835-dpi";
|
||||
reg = <0x7e208000 0x8c>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>,
|
||||
<&clocks BCM2835_CLOCK_DPI>;
|
||||
clock-names = "core", "pixel";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
v3d: v3d@7ec00000 {
|
||||
compatible = "brcm,bcm2835-v3d";
|
||||
reg = <0x7ec00000 0x1000>;
|
||||
|
|
@ -75,3 +101,13 @@ v3d: v3d@7ec00000 {
|
|||
vc4: gpu {
|
||||
compatible = "brcm,bcm2835-vc4";
|
||||
};
|
||||
|
||||
panel: panel {
|
||||
compatible = "ontat,yx700wv03", "simple-panel";
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,52 @@
|
|||
Analogix Display Port bridge bindings
|
||||
|
||||
Required properties for dp-controller:
|
||||
-compatible:
|
||||
platform specific such as:
|
||||
* "samsung,exynos5-dp"
|
||||
* "rockchip,rk3288-dp"
|
||||
-reg:
|
||||
physical base address of the controller and length
|
||||
of memory mapped region.
|
||||
-interrupts:
|
||||
interrupt combiner values.
|
||||
-clocks:
|
||||
from common clock binding: handle to dp clock.
|
||||
-clock-names:
|
||||
from common clock binding: Shall be "dp".
|
||||
-interrupt-parent:
|
||||
phandle to Interrupt combiner node.
|
||||
-phys:
|
||||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-force-hpd:
|
||||
Indicate driver need force hpd when hpd detect failed, this
|
||||
is used for some eDP screen which don't have hpd signal.
|
||||
-hpd-gpios:
|
||||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug detection
|
||||
-port@[X]: SoC specific port nodes with endpoint definitions as defined
|
||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
please refer to the SoC specific binding document:
|
||||
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
|
||||
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
dp-controller {
|
||||
compatible = "samsung,exynos5-dp";
|
||||
reg = <0x145b0000 0x10000>;
|
||||
interrupts = <10 3>;
|
||||
interrupt-parent = <&combiner>;
|
||||
clocks = <&clock 342>;
|
||||
clock-names = "dp";
|
||||
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
};
|
||||
|
|
@ -5,7 +5,8 @@ Exynos series of SoCs which transfers the image data from a video memory
|
|||
buffer to an external LCD interface.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "samsung,exynos5433-decon";
|
||||
- compatible: value should be one of:
|
||||
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
|
||||
- reg: physical base address and length of the DECON registers set.
|
||||
- interrupts: should contain a list of all DECON IP block interrupts in the
|
||||
order: VSYNC, LCD_SYSTEM. The interrupt specifier format
|
||||
|
|
@ -16,7 +17,7 @@ Required properties:
|
|||
- clocks: must include clock specifiers corresponding to entries in the
|
||||
clock-names property.
|
||||
- clock-names: list of clock names sorted in the same order as the clocks
|
||||
property. Must contain "aclk_decon", "aclk_smmu_decon0x",
|
||||
property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
|
||||
"aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
|
||||
"sclk_decon_eclk"
|
||||
- ports: contains a port which is connected to mic node. address-cells and
|
||||
|
|
|
|||
|
|
@ -1,20 +1,3 @@
|
|||
Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
|
||||
|
||||
DisplayPort is industry standard to accommodate the growing board adoption
|
||||
of digital display technology within the PC and CE industries.
|
||||
It consolidates the internal and external connection methods to reduce device
|
||||
complexity and cost. It also supports necessary features for important cross
|
||||
industry applications and provides performance scalability to enable the next
|
||||
generation of displays that feature higher color depths, refresh rates, and
|
||||
display resolutions.
|
||||
|
||||
eDP (embedded display port) device is compliant with Embedded DisplayPort
|
||||
standard as follows,
|
||||
- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
|
||||
- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
|
||||
|
||||
eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
|
||||
|
||||
The Exynos display port interface should be configured based on
|
||||
the type of panel connected to it.
|
||||
|
||||
|
|
@ -48,26 +31,6 @@ Required properties for dp-controller:
|
|||
from general PHY binding: the phandle for the PHY device.
|
||||
-phy-names:
|
||||
from general PHY binding: Should be "dp".
|
||||
-samsung,color-space:
|
||||
input video data format.
|
||||
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
|
||||
-samsung,dynamic-range:
|
||||
dynamic range for input video data.
|
||||
VESA = 0, CEA = 1
|
||||
-samsung,ycbcr-coeff:
|
||||
YCbCr co-efficients for input video.
|
||||
COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
|
||||
-samsung,color-depth:
|
||||
number of bits per colour component.
|
||||
COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
|
||||
-samsung,link-rate:
|
||||
link rate supported by the panel.
|
||||
LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
|
||||
-samsung,lane-count:
|
||||
number of lanes supported by the panel.
|
||||
LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/display-timing.txt
|
||||
|
||||
Optional properties for dp-controller:
|
||||
-interlaced:
|
||||
|
|
@ -83,17 +46,31 @@ Optional properties for dp-controller:
|
|||
Hotplug detect GPIO.
|
||||
Indicates which GPIO should be used for hotplug
|
||||
detection
|
||||
Video interfaces:
|
||||
Device node can contain video interface port nodes according to [1].
|
||||
The following are properties specific to those nodes:
|
||||
-video interfaces: Device node can contain video interface port
|
||||
nodes according to [1].
|
||||
- display-timings: timings for the connected panel as described by
|
||||
Documentation/devicetree/bindings/display/panel/display-timing.txt
|
||||
|
||||
endpoint node connected to bridge or panel node:
|
||||
- remote-endpoint: specifies the endpoint in panel or bridge node.
|
||||
This node is required in all kinds of exynos dp
|
||||
to represent the connection between dp and bridge
|
||||
or dp and panel.
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
|
||||
-phys (required)
|
||||
-phy-names (required)
|
||||
-hpd-gpios (optional)
|
||||
force-hpd (optional)
|
||||
|
||||
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
Deprecated properties for DisplayPort:
|
||||
-interlaced: deprecated prop that can parsed from drm_display_mode.
|
||||
-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
|
||||
-samsung,color-space: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
|
||||
-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
|
||||
-samsung,hpd-gpio: deprecated name for hpd-gpios.
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -112,13 +89,6 @@ SOC specific portion:
|
|||
|
||||
Board Specific portion:
|
||||
dp-controller {
|
||||
samsung,color-space = <0>;
|
||||
samsung,dynamic-range = <0>;
|
||||
samsung,ycbcr-coeff = <0>;
|
||||
samsung,color-depth = <1>;
|
||||
samsung,link-rate = <0x0a>;
|
||||
samsung,lane-count = <4>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&lcd_timing>;
|
||||
lcd_timing: 1366x768 {
|
||||
|
|
@ -135,18 +105,9 @@ Board Specific portion:
|
|||
};
|
||||
|
||||
ports {
|
||||
port {
|
||||
port@0 {
|
||||
dp_out: endpoint {
|
||||
remote-endpoint = <&dp_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
panel {
|
||||
...
|
||||
port {
|
||||
dp_in: endpoint {
|
||||
remote-endpoint = <&dp_out>;
|
||||
remote-endpoint = <&bridge_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ Video interfaces:
|
|||
endpoint node connected from mic node (reg = 0):
|
||||
- remote-endpoint: specifies the endpoint in mic node. This node is required
|
||||
for Exynos5433 mipi dsi. So mic can access to panel node
|
||||
thoughout this dsi node.
|
||||
throughout this dsi node.
|
||||
endpoint node connected to panel node (reg = 1):
|
||||
- remote-endpoint: specifies the endpoint in panel node. This node is
|
||||
required in all kinds of exynos mipi dsi to represent
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ Required properties:
|
|||
1) "samsung,exynos4210-hdmi"
|
||||
2) "samsung,exynos4212-hdmi"
|
||||
3) "samsung,exynos5420-hdmi"
|
||||
4) "samsung,exynos5433-hdmi"
|
||||
- reg: physical base address of the hdmi and length of memory mapped
|
||||
region.
|
||||
- interrupts: interrupt number to the cpu.
|
||||
|
|
@ -12,6 +13,11 @@ Required properties:
|
|||
a) phandle of the gpio controller node.
|
||||
b) pin number within the gpio controller.
|
||||
c) optional flags and pull up/down.
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 4210, 4212, 5420 and 5433:
|
||||
- clocks: list of clock IDs from SoC clock driver.
|
||||
a) hdmi: Gate of HDMI IP bus clock.
|
||||
b) sclk_hdmi: Gate of HDMI special clock.
|
||||
|
|
@ -25,9 +31,24 @@ Required properties:
|
|||
sclk_pixel.
|
||||
- clock-names: aliases as per driver requirements for above clock IDs:
|
||||
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
|
||||
- ddc: phandle to the hdmi ddc node
|
||||
- phy: phandle to the hdmi phy node
|
||||
- samsung,syscon-phandle: phandle for system controller node for PMU.
|
||||
|
||||
Required properties for Exynos 5433:
|
||||
- clocks: list of clock specifiers according to common clock bindings.
|
||||
a) hdmi_pclk: Gate of HDMI IP APB bus.
|
||||
b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
|
||||
d) i_tmds_clk: Gate of HDMI TMDS clock.
|
||||
e) i_pixel_clk: Gate of HDMI pixel clock.
|
||||
f) i_spdif_clk: Gate of HDMI SPDIF clock.
|
||||
g) oscclk: Oscillator clock, used as parent of following *_user clocks
|
||||
in case HDMI-PHY is not operational.
|
||||
h) tmds_clko: TMDS clock generated by HDMI-PHY.
|
||||
i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
j) pixel_clko: Pixel clock generated by HDMI-PHY.
|
||||
k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
|
||||
respectively if HDMI-PHY is off and operational.
|
||||
- clock-names: aliases for above clock specfiers.
|
||||
- samsung,sysreg: handle to syscon used to control the system registers.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -6,17 +6,24 @@ Required properties:
|
|||
* "fsl,vf610-dcu".
|
||||
|
||||
- reg: Address and length of the register set for dcu.
|
||||
- clocks: From common clock binding: handle to dcu clock.
|
||||
- clock-names: From common clock binding: Shall be "dcu".
|
||||
- clocks: Handle to "dcu" and "pix" clock (in the order below)
|
||||
This can be the same clock (e.g. LS1021a)
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Should be "dcu" and "pix"
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- big-endian Boolean property, LS1021A DCU registers are big-endian.
|
||||
- fsl,panel: The phandle to panel node.
|
||||
|
||||
Optional properties:
|
||||
- fsl,tcon: The phandle to the timing controller node.
|
||||
|
||||
Examples:
|
||||
dcu: dcu@2ce0000 {
|
||||
compatible = "fsl,ls1021a-dcu";
|
||||
reg = <0x0 0x2ce0000 0x0 0x10000>;
|
||||
clocks = <&platform_clk 0>;
|
||||
clock-names = "dcu";
|
||||
clocks = <&platform_clk 0>, <&platform_clk 0>;
|
||||
clock-names = "dcu", "pix";
|
||||
big-endian;
|
||||
fsl,panel = <&panel>;
|
||||
fsl,tcon = <&tcon>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,18 @@
|
|||
Device Tree bindings for Freescale TCON Driver
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of
|
||||
* "fsl,vf610-tcon".
|
||||
|
||||
- reg: Address and length of the register set for tcon.
|
||||
- clocks: From common clock binding: handle to tcon ipg clock.
|
||||
- clock-names: From common clock binding: Shall be "ipg".
|
||||
|
||||
Examples:
|
||||
timing-controller@4003d000 {
|
||||
compatible = "fsl,vf610-tcon";
|
||||
reg = <0x4003d000 0x1000>;
|
||||
clocks = <&clks VF610_CLK_TCON0>;
|
||||
clock-names = "ipg";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
|
||||
|
||||
A DSI Host Controller resides in the middle of display controller and external
|
||||
HDMI converter or panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-dsi".
|
||||
- reg: physical base address and length of dsi controller's registers.
|
||||
- clocks: contains APB clock phandle + clock-specifier pair.
|
||||
- clock-names: should be "pclk".
|
||||
- ports: contains DSI controller input and output sub port.
|
||||
The input port connects to ADE output port with the reg value "0".
|
||||
The output port with the reg value "1", it could connect to panel or
|
||||
any other bridge endpoints.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
A example of HiKey board hi6220 SoC and board specific DT entry:
|
||||
Example:
|
||||
|
||||
SoC specific:
|
||||
dsi: dsi@f4107800 {
|
||||
compatible = "hisilicon,hi6220-dsi";
|
||||
reg = <0x0 0xf4107800 0x0 0x100>;
|
||||
clocks = <&media_ctrl HI6220_DSI_PCLK>;
|
||||
clock-names = "pclk";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 0 for input port */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi_in: endpoint {
|
||||
remote-endpoint = <&ade_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Board specific:
|
||||
&dsi {
|
||||
status = "ok";
|
||||
|
||||
ports {
|
||||
/* 1 for output port */
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
dsi_out0: endpoint@0 {
|
||||
remote-endpoint = <&adv7533_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
...
|
||||
|
||||
adv7533: adv7533@39 {
|
||||
...
|
||||
|
||||
port {
|
||||
adv7533_in: endpoint {
|
||||
remote-endpoint = <&dsi_out0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
Device-Tree bindings for hisilicon ADE display controller driver
|
||||
|
||||
ADE (Advanced Display Engine) is the display controller which grab image
|
||||
data from memory, do composition, do post image processing, generate RGB
|
||||
timing stream and transfer to DSI.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "hisilicon,hi6220-ade".
|
||||
- reg: physical base address and length of the ADE controller's registers.
|
||||
- hisilicon,noc-syscon: ADE NOC QoS syscon.
|
||||
- resets: The ADE reset controller node.
|
||||
- interrupt: the ldi vblank interrupt number used.
|
||||
- clocks: a list of phandle + clock-specifier pairs, one for each entry
|
||||
in clock-names.
|
||||
- clock-names: should contain:
|
||||
"clk_ade_core" for the ADE core clock.
|
||||
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
|
||||
jpeg codec.
|
||||
"clk_ade_pix" for the ADE pixel clok.
|
||||
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
|
||||
phandle + clock-specifier pairs.
|
||||
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
|
||||
The rate of "clk_ade_core" could be "360000000" or "180000000";
|
||||
The rate of "clk_codec_jpeg" could be or less than "1440000000".
|
||||
These rate values could be configured according to performance and power
|
||||
consumption.
|
||||
- port: the output port. This contains one endpoint subnode, with its
|
||||
remote-endpoint set to the phandle of the connected DSI input endpoint.
|
||||
See Documentation/devicetree/bindings/graph.txt for more device graph info.
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: Present if dma operations are coherent.
|
||||
|
||||
|
||||
A example of HiKey board hi6220 SoC specific DT entry:
|
||||
Example:
|
||||
|
||||
ade: ade@f4100000 {
|
||||
compatible = "hisilicon,hi6220-ade";
|
||||
reg = <0x0 0xf4100000 0x0 0x7800>;
|
||||
reg-names = "ade_base";
|
||||
hisilicon,noc-syscon = <&medianoc_ade>;
|
||||
resets = <&media_ctrl MEDIA_ADE>;
|
||||
interrupts = <0 115 4>; /* ldi interrupt */
|
||||
|
||||
clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>,
|
||||
<&media_ctrl HI6220_ADE_PIX_SRC>;
|
||||
/*clock name*/
|
||||
clock-names = "clk_ade_core",
|
||||
"clk_codec_jpeg",
|
||||
"clk_ade_pix";
|
||||
|
||||
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
|
||||
<&media_ctrl HI6220_CODEC_JPEG>;
|
||||
assigned-clock-rates = <360000000>, <288000000>;
|
||||
dma-coherent;
|
||||
|
||||
port {
|
||||
ade_out: endpoint {
|
||||
remote-endpoint = <&dsi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
Mediatek display subsystem
|
||||
==========================
|
||||
|
||||
The Mediatek display subsystem consists of various DISP function blocks in the
|
||||
MMSYS register space. The connections between them can be configured by output
|
||||
and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
|
||||
of frame signal are distributed to the other function blocks by a DISP_MUTEX
|
||||
function block.
|
||||
|
||||
All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
|
||||
For a description of the MMSYS_CONFIG binding, see
|
||||
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
|
||||
|
||||
DISP function blocks
|
||||
====================
|
||||
|
||||
A display stream starts at a source function block that reads pixel data from
|
||||
memory and ends with a sink function block that drives pixels on a display
|
||||
interface, or writes pixels back to memory. All DISP function blocks have
|
||||
their own register space, interrupt, and clock gate. The blocks that can
|
||||
access memory additionally have to list the IOMMU and local arbiter they are
|
||||
connected to.
|
||||
|
||||
For a description of the display interface sink function blocks, see
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
|
||||
Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
|
||||
|
||||
Required properties (all function blocks):
|
||||
- compatible: "mediatek,<chip>-disp-<function>", one of
|
||||
"mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
|
||||
"mediatek,<chip>-disp-rdma" - read DMA / line buffer
|
||||
"mediatek,<chip>-disp-wdma" - write DMA
|
||||
"mediatek,<chip>-disp-color" - color processor
|
||||
"mediatek,<chip>-disp-aal" - adaptive ambient light controller
|
||||
"mediatek,<chip>-disp-gamma" - gamma correction
|
||||
"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
|
||||
"mediatek,<chip>-disp-split" - split stream to two encoders
|
||||
"mediatek,<chip>-disp-ufoe" - data compression engine
|
||||
"mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
|
||||
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
|
||||
"mediatek,<chip>-disp-mutex" - display mutex
|
||||
"mediatek,<chip>-disp-od" - overdrive
|
||||
- reg: Physical base address and length of the function block register space
|
||||
- interrupts: The interrupt signal from the function block (required, except for
|
||||
merge and split function blocks).
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
For most function blocks this is just a single clock input. Only the DSI and
|
||||
DPI controller nodes have multiple clock inputs. These are documented in
|
||||
mediatek,dsi.txt and mediatek,dpi.txt, respectively.
|
||||
|
||||
Required properties (DMA function blocks):
|
||||
- compatible: Should be one of
|
||||
"mediatek,<chip>-disp-ovl"
|
||||
"mediatek,<chip>-disp-rdma"
|
||||
"mediatek,<chip>-disp-wdma"
|
||||
- larb: Should contain a phandle pointing to the local arbiter device as defined
|
||||
in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt
|
||||
- iommus: Should point to the respective IOMMU block with master port as
|
||||
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
|
||||
for details.
|
||||
|
||||
Examples:
|
||||
|
||||
mmsys: clock-controller@14000000 {
|
||||
compatible = "mediatek,mt8173-mmsys", "syscon";
|
||||
reg = <0 0x14000000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
ovl0: ovl@1400c000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
ovl1: ovl@1400d000 {
|
||||
compatible = "mediatek,mt8173-disp-ovl";
|
||||
reg = <0 0x1400d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OVL1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_OVL1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma0: rdma@1400e000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400e000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
rdma1: rdma@1400f000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x1400f000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
rdma2: rdma@14010000 {
|
||||
compatible = "mediatek,mt8173-disp-rdma";
|
||||
reg = <0 0x14010000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_RDMA2>;
|
||||
iommus = <&iommu M4U_PORT_DISP_RDMA2>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
wdma0: wdma@14011000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14011000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA0>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA0>;
|
||||
mediatek,larb = <&larb0>;
|
||||
};
|
||||
|
||||
wdma1: wdma@14012000 {
|
||||
compatible = "mediatek,mt8173-disp-wdma";
|
||||
reg = <0 0x14012000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_WDMA1>;
|
||||
iommus = <&iommu M4U_PORT_DISP_WDMA1>;
|
||||
mediatek,larb = <&larb4>;
|
||||
};
|
||||
|
||||
color0: color@14013000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14013000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
||||
};
|
||||
|
||||
color1: color@14014000 {
|
||||
compatible = "mediatek,mt8173-disp-color";
|
||||
reg = <0 0x14014000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_COLOR1>;
|
||||
};
|
||||
|
||||
aal@14015000 {
|
||||
compatible = "mediatek,mt8173-disp-aal";
|
||||
reg = <0 0x14015000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_AAL>;
|
||||
};
|
||||
|
||||
gamma@14016000 {
|
||||
compatible = "mediatek,mt8173-disp-gamma";
|
||||
reg = <0 0x14016000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_GAMMA>;
|
||||
};
|
||||
|
||||
ufoe@1401a000 {
|
||||
compatible = "mediatek,mt8173-disp-ufoe";
|
||||
reg = <0 0x1401a000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_UFOE>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
/* See mediatek,dsi.txt for details */
|
||||
};
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
/* See mediatek,dpi.txt for details */
|
||||
};
|
||||
|
||||
mutex: mutex@14020000 {
|
||||
compatible = "mediatek,mt8173-disp-mutex";
|
||||
reg = <0 0x14020000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_MUTEX_32K>;
|
||||
};
|
||||
|
||||
od@14023000 {
|
||||
compatible = "mediatek,mt8173-disp-od";
|
||||
reg = <0 0x14023000 0 0x1000>;
|
||||
power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
|
||||
clocks = <&mmsys CLK_MM_DISP_OD>;
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
Mediatek DPI Device
|
||||
===================
|
||||
|
||||
The Mediatek DPI function block is a sink of the display subsystem and
|
||||
provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
|
||||
output bus.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dpi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "pixel", "engine", and "pll"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached HDMI or LVDS encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
dpi0: dpi@1401d000 {
|
||||
compatible = "mediatek,mt8173-dpi";
|
||||
reg = <0 0x1401d000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
|
||||
<&mmsys CLK_MM_DPI_ENGINE>,
|
||||
<&apmixedsys CLK_APMIXED_TVDPLL>;
|
||||
clock-names = "pixel", "engine", "pll";
|
||||
|
||||
port {
|
||||
dpi0_out: endpoint {
|
||||
remote-endpoint = <&hdmi0_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
Mediatek DSI Device
|
||||
===================
|
||||
|
||||
The Mediatek DSI function block is a sink of the display subsystem and can
|
||||
drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
|
||||
channel output.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-dsi"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- interrupts: The interrupt signal from the function block.
|
||||
- clocks: device clocks
|
||||
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
|
||||
- clock-names: must contain "engine", "digital", and "hs"
|
||||
- phys: phandle link to the MIPI D-PHY controller.
|
||||
- phy-names: must contain "dphy"
|
||||
- port: Output port node with endpoint definitions as described in
|
||||
Documentation/devicetree/bindings/graph.txt. This port should be connected
|
||||
to the input port of an attached DSI panel or DSI-to-eDP encoder chip.
|
||||
|
||||
MIPI TX Configuration Module
|
||||
============================
|
||||
|
||||
The MIPI TX configuration module controls the MIPI D-PHY.
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,<chip>-mipi-tx"
|
||||
- reg: Physical base address and length of the controller's registers
|
||||
- clocks: PLL reference clock
|
||||
- clock-output-names: name of the output clock line to the DSI encoder
|
||||
- #clock-cells: must be <0>;
|
||||
- #phy-cells: must be <0>.
|
||||
|
||||
Example:
|
||||
|
||||
mipi_tx0: mipi-dphy@10215000 {
|
||||
compatible = "mediatek,mt8173-mipi-tx";
|
||||
reg = <0 0x10215000 0 0x1000>;
|
||||
clocks = <&clk26m>;
|
||||
clock-output-names = "mipi_tx0_pll";
|
||||
#clock-cells = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
dsi0: dsi@1401b000 {
|
||||
compatible = "mediatek,mt8173-dsi";
|
||||
reg = <0 0x1401b000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,
|
||||
<&mipi_tx0>;
|
||||
clock-names = "engine", "digital", "hs";
|
||||
phys = <&mipi_tx0>;
|
||||
phy-names = "dphy";
|
||||
|
||||
port {
|
||||
dsi0_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Innolux AT070TN92 7.0" WQVGA TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "innolux,at070tn92"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
Olimex 4.3" TFT LCD panel
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "olimex,lcd-olinuxino-43-ts"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
On Tat Industrial Company 7" DPI TFT panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "ontat,yx700wv03"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
TPK U.S.A. LLC Fusion 7" integrated projected capacitive touch display with,
|
||||
800 x 480 (WVGA) LCD panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tpk,f07a-0102"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
TPK U.S.A. LLC Fusion 10.1" integrated projected capacitive touch display with,
|
||||
1024 x 600 (WSVGA) LCD panel.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "tpk,f10a-0102"
|
||||
|
||||
This binding is compatible with the simple-panel binding, which is specified
|
||||
in simple-panel.txt in this directory.
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
Rockchip RK3288 specific extensions to the Analogix Display Port
|
||||
================================
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-edp";
|
||||
|
||||
- reg: physical base address of the controller and length
|
||||
|
||||
- clocks: from common clock binding: handle to dp clock.
|
||||
of memory mapped region.
|
||||
|
||||
- clock-names: from common clock binding:
|
||||
Required elements: "dp" "pclk"
|
||||
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
|
||||
- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
|
||||
- pinctrl-0: pin-control mode. should be <&edp_hpd>
|
||||
|
||||
- reset-names: Must include the name "dp"
|
||||
|
||||
- rockchip,grf: this soc should set GRF regs, so need get grf here.
|
||||
|
||||
- ports: there are 2 port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt.
|
||||
Port 0: contained 2 endpoints, connecting to the output of vop.
|
||||
Port 1: contained 1 endpoint, connecting to the input of panel.
|
||||
|
||||
For the below properties, please refer to Analogix DP binding document:
|
||||
* Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
|
||||
- phys (required)
|
||||
- phy-names (required)
|
||||
- hpd-gpios (optional)
|
||||
- force-hpd (optional)
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
Example:
|
||||
dp-controller: dp@ff970000 {
|
||||
compatible = "rockchip,rk3288-dp";
|
||||
reg = <0xff970000 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
|
||||
clock-names = "dp", "pclk";
|
||||
phys = <&dp_phy>;
|
||||
phy-names = "dp";
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
resets = <&cru 111>;
|
||||
reset-names = "dp";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edp_hpd>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_in: port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_in_vopb: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&vopb_out_edp>;
|
||||
};
|
||||
edp_in_vopl: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&vopl_out_edp>;
|
||||
};
|
||||
};
|
||||
|
||||
edp_out: port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
edp_out_panel: endpoint {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_in_edp>
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
edp {
|
||||
edp_hpd: edp-hpd {
|
||||
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
ARC PGU
|
||||
|
||||
This is a display controller found on several development boards produced
|
||||
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
|
||||
framebuffer and sends it to a single digital encoder (usually HDMI).
|
||||
|
||||
Required properties:
|
||||
- compatible: "snps,arcpgu"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: A list of phandle + clock-specifier pairs, one for each
|
||||
entry in 'clock-names'.
|
||||
- clock-names: A list of clock names. For ARC PGU it should contain:
|
||||
- "pxlclk" for the clock feeding the output PLL of the controller.
|
||||
|
||||
Required sub-nodes:
|
||||
- port: The PGU connection to an encoder chip.
|
||||
|
||||
Example:
|
||||
|
||||
/ {
|
||||
...
|
||||
|
||||
pgu@XXXXXXXX {
|
||||
compatible = "snps,arcpgu";
|
||||
reg = <0xXXXXXXXX 0x400>;
|
||||
clocks = <&clock_node>;
|
||||
clock-names = "pxlclk";
|
||||
|
||||
port {
|
||||
pgu_output: endpoint {
|
||||
remote-endpoint = <&hdmi_enc_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
Allwinner A10 Display Pipeline
|
||||
==============================
|
||||
|
||||
The Allwinner A10 Display pipeline is composed of several components
|
||||
that are going to be documented below:
|
||||
|
||||
TV Encoder
|
||||
----------
|
||||
|
||||
The TV Encoder supports the composite and VGA output. It is one end of
|
||||
the pipeline.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "allwinner,sun4i-a10-tv-encoder".
|
||||
- reg: base address and size of memory-mapped region
|
||||
- clocks: the clocks driving the TV encoder
|
||||
- resets: phandle to the reset controller driving the encoder
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint.
|
||||
|
||||
TCON
|
||||
----
|
||||
|
||||
The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
|
||||
|
||||
Required properties:
|
||||
- compatible: value should be "allwinner,sun5i-a13-tcon".
|
||||
- reg: base address and size of memory-mapped region
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the TCON. Three are needed:
|
||||
- 'ahb': the interface clocks
|
||||
- 'tcon-ch0': The clock driving the TCON channel 0
|
||||
- 'tcon-ch1': The clock driving the TCON channel 1
|
||||
- resets: phandles to the reset controllers driving the encoder
|
||||
- "lcd": the reset line for the TCON channel 0
|
||||
|
||||
- clock-names: the clock names mentioned above
|
||||
- reset-names: the reset names mentioned above
|
||||
- clock-output-names: Name of the pixel clock created
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoint, the second one the output
|
||||
|
||||
The output should have two endpoints. The first is the block
|
||||
connected to the TCON channel 0 (usually a panel or a bridge), the
|
||||
second the block connected to the TCON channel 1 (usually the TV
|
||||
encoder)
|
||||
|
||||
|
||||
Display Engine Backend
|
||||
----------------------
|
||||
|
||||
The display engine backend exposes layers and sprites to the
|
||||
system.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-backend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- clocks: phandles to the clocks feeding the frontend and backend
|
||||
* ahb: the backend interface clock
|
||||
* mod: the backend module clock
|
||||
* ram: the backend DRAM clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandles to the reset controllers driving the backend
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the output
|
||||
|
||||
Display Engine Frontend
|
||||
-----------------------
|
||||
|
||||
The display engine frontend does formats conversion, scaling,
|
||||
deinterlacing and color space conversion.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-frontend
|
||||
- reg: base address and size of the memory-mapped region.
|
||||
- interrupts: interrupt associated to this IP
|
||||
- clocks: phandles to the clocks feeding the frontend and backend
|
||||
* ahb: the backend interface clock
|
||||
* mod: the backend module clock
|
||||
* ram: the backend DRAM clock
|
||||
- clock-names: the clock names mentioned above
|
||||
- resets: phandles to the reset controllers driving the backend
|
||||
|
||||
- ports: A ports node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. The
|
||||
first port should be the input endpoints, the second one the outputs
|
||||
|
||||
|
||||
Display Engine Pipeline
|
||||
-----------------------
|
||||
|
||||
The display engine pipeline (and its entry point, since it can be
|
||||
either directly the backend or the frontend) is represented as an
|
||||
extra node.
|
||||
|
||||
Required properties:
|
||||
- compatible: value must be one of:
|
||||
* allwinner,sun5i-a13-display-engine
|
||||
|
||||
- allwinner,pipelines: list of phandle to the display engine
|
||||
frontends available.
|
||||
|
||||
Example:
|
||||
|
||||
panel: panel {
|
||||
compatible = "olimex,lcd-olinuxino-43-ts";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
panel_input: endpoint {
|
||||
remote-endpoint = <&tcon0_out_panel>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tve0: tv-encoder@01c0a000 {
|
||||
compatible = "allwinner,sun4i-a10-tv-encoder";
|
||||
reg = <0x01c0a000 0x1000>;
|
||||
clocks = <&ahb_gates 34>;
|
||||
resets = <&tcon_ch0_clk 0>;
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tve0_in_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_out_tve0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tcon0: lcd-controller@1c0c000 {
|
||||
compatible = "allwinner,sun5i-a13-tcon";
|
||||
reg = <0x01c0c000 0x1000>;
|
||||
interrupts = <44>;
|
||||
resets = <&tcon_ch0_clk 1>;
|
||||
reset-names = "lcd";
|
||||
clocks = <&ahb_gates 36>,
|
||||
<&tcon_ch0_clk>,
|
||||
<&tcon_ch1_clk>;
|
||||
clock-names = "ahb",
|
||||
"tcon-ch0",
|
||||
"tcon-ch1";
|
||||
clock-output-names = "tcon-pixel-clock";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
tcon0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
tcon0_in_be0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&be0_out_tcon0>;
|
||||
};
|
||||
};
|
||||
|
||||
tcon0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
tcon0_out_panel: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&panel_input>;
|
||||
};
|
||||
|
||||
tcon0_out_tve0: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&tve0_in_tcon0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fe0: display-frontend@1e00000 {
|
||||
compatible = "allwinner,sun5i-a13-display-frontend";
|
||||
reg = <0x01e00000 0x20000>;
|
||||
interrupts = <47>;
|
||||
clocks = <&ahb_gates 46>, <&de_fe_clk>,
|
||||
<&dram_gates 25>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&de_fe_clk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
fe0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
fe0_out_be0: endpoint {
|
||||
remote-endpoint = <&be0_in_fe0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
be0: display-backend@1e60000 {
|
||||
compatible = "allwinner,sun5i-a13-display-backend";
|
||||
reg = <0x01e60000 0x10000>;
|
||||
clocks = <&ahb_gates 44>, <&de_be_clk>,
|
||||
<&dram_gates 26>;
|
||||
clock-names = "ahb", "mod",
|
||||
"ram";
|
||||
resets = <&de_be_clk>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
be0_in: port@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
be0_in_fe0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&fe0_out_be0>;
|
||||
};
|
||||
};
|
||||
|
||||
be0_out: port@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
be0_out_tcon0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&tcon0_in_be0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
display-engine {
|
||||
compatible = "allwinner,sun5i-a13-display-engine";
|
||||
allwinner,pipelines = <&fe0>;
|
||||
};
|
||||
|
|
@ -12,6 +12,10 @@ Required properties:
|
|||
- reg: Should contain DMA registers location and length.
|
||||
- interrupts: Should contain the DMA interrupts associated
|
||||
to the DMA channels in ascending order.
|
||||
- interrupt-names: Should contain the names of the interrupt
|
||||
in the form "dmaXX".
|
||||
Use "dma-shared-all" for the common interrupt line
|
||||
that is shared by all dma channels.
|
||||
- #dma-cells: Must be <1>, the cell in the dmas property of the
|
||||
client device represents the DREQ number.
|
||||
- brcm,dma-channel-mask: Bit mask representing the channels
|
||||
|
|
@ -34,13 +38,35 @@ dma: dma@7e007000 {
|
|||
<1 24>,
|
||||
<1 25>,
|
||||
<1 26>,
|
||||
/* dma channel 11-14 share one irq */
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
<1 27>,
|
||||
/* unused shared irq for all channels */
|
||||
<1 28>;
|
||||
interrupt-names = "dma0",
|
||||
"dma1",
|
||||
"dma2",
|
||||
"dma3",
|
||||
"dma4",
|
||||
"dma5",
|
||||
"dma6",
|
||||
"dma7",
|
||||
"dma8",
|
||||
"dma9",
|
||||
"dma10",
|
||||
"dma11",
|
||||
"dma12",
|
||||
"dma13",
|
||||
"dma14",
|
||||
"dma-shared-all";
|
||||
|
||||
#dma-cells = <1>;
|
||||
brcm,dma-channel-mask = <0x7f35>;
|
||||
};
|
||||
|
||||
|
||||
DMA clients connected to the BCM2835 DMA controller must use the format
|
||||
described in the dma.txt file, using a two-cell specifier for each channel.
|
||||
|
||||
|
|
|
|||
|
|
@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below.
|
|||
1 Medium
|
||||
2 Low
|
||||
|
||||
Optional properties:
|
||||
|
||||
- gpr : The phandle to the General Purpose Register (GPR) node.
|
||||
- fsl,sdma-event-remap : Register bits of sdma event remap, the format is
|
||||
<reg shift val>.
|
||||
reg is the GPR register offset.
|
||||
shift is the bit position inside the GPR register.
|
||||
val is the value of the bit (0 or 1).
|
||||
|
||||
Examples:
|
||||
|
||||
sdma@83fb0000 {
|
||||
|
|
@ -83,3 +92,21 @@ ssi2: ssi@70014000 {
|
|||
dma-names = "rx", "tx";
|
||||
fsl,fifo-depth = <15>;
|
||||
};
|
||||
|
||||
Using the fsl,sdma-event-remap property:
|
||||
|
||||
If we want to use SDMA on the SAI1 port on a MX6SX:
|
||||
|
||||
&sdma {
|
||||
gpr = <&gpr>;
|
||||
/* SDMA events remap for SAI1_RX and SAI1_TX */
|
||||
fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
|
||||
};
|
||||
|
||||
The fsl,sdma-event-remap property in this case has two values:
|
||||
- <0 15 1> means that the offset is 0, so GPR0 is the register of the
|
||||
SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
|
||||
Setting bit 15 to 1 selects SAI1_RX.
|
||||
- <0 16 1> means that the offset is 0, so GPR0 is the register of the
|
||||
SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
|
||||
Setting bit 16 to 1 selects SAI1_TX.
|
||||
|
|
|
|||
|
|
@ -1,7 +1,10 @@
|
|||
* Marvell XOR engines
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"
|
||||
- compatible: Should be one of the following:
|
||||
- "marvell,orion-xor"
|
||||
- "marvell,armada-380-xor"
|
||||
- "marvell,armada-3700-xor".
|
||||
- reg: Should contain registers location and length (two sets)
|
||||
the first set is the low registers, the second set the high
|
||||
registers for the XOR engine.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,55 @@
|
|||
* NVIDIA Tegra Audio DMA (ADMA) controller
|
||||
|
||||
The Tegra Audio DMA controller that is used for transferring data
|
||||
between system memory and the Audio Processing Engine (APE).
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "nvidia,tegra210-adma".
|
||||
- reg: Should contain DMA registers location and length. This should be
|
||||
a single entry that includes all of the per-channel registers in one
|
||||
contiguous bank.
|
||||
- interrupt-parent: Phandle to the interrupt parent controller.
|
||||
- interrupts: Should contain all of the per-channel DMA interrupts in
|
||||
ascending order with respect to the DMA channel index.
|
||||
- clocks: Must contain one entry for the ADMA module clock
|
||||
(TEGRA210_CLK_D_AUDIO).
|
||||
- clock-names: Must contain the name "d_audio" for the corresponding
|
||||
'clocks' entry.
|
||||
- #dma-cells : Must be 1. The first cell denotes the receive/transmit
|
||||
request number and should be between 1 and the maximum number of
|
||||
requests supported. This value corresponds to the RX/TX_REQUEST_SELECT
|
||||
fields in the ADMA_CHn_CTRL register.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
adma: dma@702e2000 {
|
||||
compatible = "nvidia,tegra210-adma";
|
||||
reg = <0x0 0x702e2000 0x0 0x2000>;
|
||||
interrupt-parent = <&tegra_agic>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
|
||||
clock-names = "d_audio";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
|
@ -13,6 +13,8 @@ Required properties:
|
|||
- clock-names: must contain "bam_clk" entry
|
||||
- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
|
||||
the secure world.
|
||||
- qcom,controlled-remotely : optional, indicates that the bam is controlled by
|
||||
remote proccessor i.e. execution environment.
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -13,6 +13,11 @@ Required properties:
|
|||
- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
|
||||
increase from chan n->0
|
||||
- block_size: Maximum block size supported by the controller
|
||||
- data-width: Maximum data width supported by hardware per AHB master
|
||||
(in bytes, power of 2)
|
||||
|
||||
|
||||
Deprecated properties:
|
||||
- data_width: Maximum data width supported by hardware per AHB master
|
||||
(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
|
||||
|
||||
|
|
@ -38,7 +43,7 @@ Example:
|
|||
chan_allocation_order = <1>;
|
||||
chan_priority = <1>;
|
||||
block_size = <0xfff>;
|
||||
data_width = <3 3>;
|
||||
data-width = <8 8>;
|
||||
};
|
||||
|
||||
DMA clients connected to the Designware DMA controller must use the format
|
||||
|
|
@ -47,8 +52,8 @@ The four cells in order are:
|
|||
|
||||
1. A phandle pointing to the DMA controller
|
||||
2. The DMA request line number
|
||||
3. Source master for transfers on allocated channel
|
||||
4. Destination master for transfers on allocated channel
|
||||
3. Memory master for transfers on allocated channel
|
||||
4. Peripheral master for transfers on allocated channel
|
||||
|
||||
Example:
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ Required properties:
|
|||
- compatible: Should be "xlnx,axi-dma-1.00.a"
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain DMA registers location and length.
|
||||
- dma-channel child node: Should have atleast one channel and can have upto
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
|
||||
|
|
|
|||
|
|
@ -3,18 +3,44 @@ It can be configured to have one channel or two channels. If configured
|
|||
as two channels, one is to transmit to the video device and another is
|
||||
to receive from the video device.
|
||||
|
||||
Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
|
||||
target devices. It can be configured to have one channel or two channels.
|
||||
If configured as two channels, one is to transmit to the device and another
|
||||
is to receive from the device.
|
||||
|
||||
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
|
||||
address and a memory-mapped destination address.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a"
|
||||
- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
|
||||
"xlnx,axi-cdma-1.00.a""
|
||||
- #dma-cells: Should be <1>, see "dmas" property below
|
||||
- reg: Should contain VDMA registers location and length.
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
|
||||
- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
|
||||
- dma-channel child node: Should have at least one channel and can have up to
|
||||
two channels per device. This node specifies the properties of each
|
||||
DMA channel (see child node properties below).
|
||||
- clocks: Input clock specifier. Refer to common clock bindings.
|
||||
- clock-names: List of input clocks
|
||||
For VDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
|
||||
For CDMA:
|
||||
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
|
||||
FOR AXIDMA:
|
||||
Required elements: "s_axi_lite_aclk"
|
||||
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axi_sg_aclk"
|
||||
|
||||
Required properties for VDMA:
|
||||
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
|
||||
|
||||
Optional properties:
|
||||
- xlnx,include-sg: Tells configured for Scatter-mode in
|
||||
the hardware.
|
||||
Optional properties for VDMA:
|
||||
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
|
||||
It takes following values:
|
||||
{1}, flush both channels
|
||||
|
|
@ -31,6 +57,7 @@ Required child node properties:
|
|||
Optional child node properties:
|
||||
- xlnx,include-dre: Tells hardware is configured for Data
|
||||
Realignment Engine.
|
||||
Optional child node properties for VDMA:
|
||||
- xlnx,genlock-mode: Tells Genlock synchronization is
|
||||
enabled/disabled in hardware.
|
||||
|
||||
|
|
@ -41,8 +68,13 @@ axi_vdma_0: axivdma@40030000 {
|
|||
compatible = "xlnx,axi-vdma-1.00.a";
|
||||
#dma_cells = <1>;
|
||||
reg = < 0x40030000 0x10000 >;
|
||||
dma-ranges = <0x00000000 0x00000000 0x40000000>;
|
||||
xlnx,num-fstores = <0x8>;
|
||||
xlnx,flush-fsync = <0x1>;
|
||||
xlnx,addrwidth = <0x20>;
|
||||
clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
|
||||
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
|
||||
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
|
||||
dma-channel@40030000 {
|
||||
compatible = "xlnx,axi-vdma-mm2s-channel";
|
||||
interrupts = < 0 54 4 >;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,9 @@
|
|||
* Generic 8-bits shift register GPIO driver
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fairchild,74hc595"
|
||||
- compatible: Should contain one of the following:
|
||||
"fairchild,74hc595"
|
||||
"nxp,74lvc594"
|
||||
- reg : chip select number
|
||||
- gpio-controller : Marks the device node as a gpio controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
|
|
|
|||
|
|
@ -1,9 +1,10 @@
|
|||
* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
|
||||
* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller
|
||||
|
||||
Required properties:
|
||||
- compatible : Should be "fsl,<soc>-gpio"
|
||||
The following <soc>s are known to be supported:
|
||||
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
|
||||
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
|
||||
ls1021a, ls1043a, ls2080a.
|
||||
- reg : Address and length of the register set for the device
|
||||
- interrupts : Should be the port interrupt shared by all 32 pins.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and
|
||||
|
|
@ -15,7 +16,7 @@ Optional properties:
|
|||
- little-endian : GPIO registers are used as little endian. If not
|
||||
present registers are used as big endian by default.
|
||||
|
||||
Example:
|
||||
Example of gpio-controller node for a mpc5125 SoC:
|
||||
|
||||
gpio0: gpio@1100 {
|
||||
compatible = "fsl,mpc5125-gpio";
|
||||
|
|
@ -24,3 +25,16 @@ gpio0: gpio@1100 {
|
|||
interrupts = <78 0x8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
Example of gpio-controller node for a ls2080a SoC:
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 36 0x4>; /* Level high type */
|
||||
gpio-controller;
|
||||
little-endian;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -3,6 +3,8 @@ Netlogic XLP Family GPIO
|
|||
|
||||
This GPIO driver is used for following Netlogic XLP SoCs:
|
||||
XLP832, XLP316, XLP208, XLP980, XLP532
|
||||
This GPIO driver is also compatible with GPIO controller found on
|
||||
Broadcom Vulcan ARM64.
|
||||
|
||||
Required properties:
|
||||
-------------------
|
||||
|
|
@ -13,6 +15,7 @@ Required properties:
|
|||
- "netlogic,xlp208-gpio": For Netlogic XLP208
|
||||
- "netlogic,xlp980-gpio": For Netlogic XLP980
|
||||
- "netlogic,xlp532-gpio": For Netlogic XLP532
|
||||
- "brcm,vulcan-gpio": For Broadcom Vulcan ARM64
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- #gpio-cells: Should be two. The first cell is the pin number and the second
|
||||
cell is used to specify optional parameters (currently unused).
|
||||
|
|
|
|||
|
|
@ -131,6 +131,13 @@ Every GPIO controller node must contain both an empty "gpio-controller"
|
|||
property, and a #gpio-cells integer property, which indicates the number of
|
||||
cells in a gpio-specifier.
|
||||
|
||||
Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
|
||||
instance of a hardware IP core on a silicon die, usually exposed to the
|
||||
programmer as a coherent range of I/O addresses. Usually each such bank is
|
||||
exposed in the device tree as an individual gpio-controller node, reflecting
|
||||
the fact that the hardware was synthesized by reusing the same IP block a
|
||||
few times over.
|
||||
|
||||
Optionally, a GPIO controller may have a "ngpios" property. This property
|
||||
indicates the number of in-use slots of available slots for GPIOs. The
|
||||
typical example is something like this: the hardware register is 32 bits
|
||||
|
|
@ -145,6 +152,21 @@ additional bitmask is needed to specify which GPIOs are actually in use,
|
|||
and which are dummies. The bindings for this case has not yet been
|
||||
specified, but should be specified if/when such hardware appears.
|
||||
|
||||
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
|
||||
an array of strings defining the names of the GPIO lines going out of the
|
||||
GPIO controller. This name should be the most meaningful producer name
|
||||
for the system, such as a rail name indicating the usage. Package names
|
||||
such as pin name are discouraged: such lines have opaque names (since they
|
||||
are by definition generic purpose) and such names are usually not very
|
||||
helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
|
||||
reasonable line names as they describe what the line is used for. "GPIO0"
|
||||
is not a good name to give to a GPIO line. Placeholders are discouraged:
|
||||
rather use the "" (blank string) if the use of the GPIO line is undefined
|
||||
in your design. The names are assigned starting from line offset 0 from
|
||||
left to right from the passed array. An incomplete array (where the number
|
||||
of passed named are less than ngpios) will still be used up until the last
|
||||
provided valid line index.
|
||||
|
||||
Example:
|
||||
|
||||
gpio-controller@00000000 {
|
||||
|
|
@ -153,6 +175,10 @@ gpio-controller@00000000 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <18>;
|
||||
gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
|
||||
"LED G", "LED B", "Col A", "Col B", "Col C", "Col D",
|
||||
"Row A", "Row B", "Row C", "Row D", "NMI button",
|
||||
"poweroff", "reset";
|
||||
}
|
||||
|
||||
The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
|
||||
|
|
|
|||
|
|
@ -0,0 +1,24 @@
|
|||
* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs
|
||||
|
||||
All GPIOs are pin-shared with other functions. DCRs control whether a
|
||||
particular pin that has GPIO capabilities acts as a GPIO or is used for
|
||||
another purpose. GPIO outputs are separately programmable to emulate
|
||||
an open-drain driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "ibm,ppc4xx-gpio"
|
||||
- reg: address and length of the register set for the device
|
||||
- #gpio-cells: must be set to 2. The first cell is the pin number
|
||||
and the second cell is used to specify the gpio polarity:
|
||||
0 = active high
|
||||
1 = active low
|
||||
- gpio-controller: marks the device node as a gpio controller.
|
||||
|
||||
Example:
|
||||
|
||||
GPIO0: gpio@ef600b00 {
|
||||
compatible = "ibm,ppc4xx-gpio";
|
||||
reg = <0xef600b00 0x00000048>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
|
@ -33,7 +33,7 @@ gpio0: gpio0@1f860000 {
|
|||
gpio-controller;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&PBCLK4>;
|
||||
clocks = <&rootclk PB4CLK>;
|
||||
microchip,gpio-bank = <0>;
|
||||
gpio-ranges = <&pic32_pinctrl 0 0 16>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,161 @@
|
|||
NVIDIA Tegra186 GPIO controllers
|
||||
|
||||
Tegra186 contains two GPIO controllers; a main controller and an "AON"
|
||||
controller. This binding document applies to both controllers. The register
|
||||
layouts for the controllers share many similarities, but also some significant
|
||||
differences. Hence, this document describes closely related but different
|
||||
bindings and compatible values.
|
||||
|
||||
The Tegra186 GPIO controller allows software to set the IO direction of, and
|
||||
read/write the value of, numerous GPIO signals. Routing of GPIO signals to
|
||||
package balls is under the control of a separate pin controller HW block. Two
|
||||
major sets of registers exist:
|
||||
|
||||
a) Security registers, which allow configuration of allowed access to the GPIO
|
||||
register set. These registers exist in a single contiguous block of physical
|
||||
address space. The size of this block, and the security features available,
|
||||
varies between the different GPIO controllers.
|
||||
|
||||
Access to this set of registers is not necessary in all circumstances. Code
|
||||
that wishes to configure access to the GPIO registers needs access to these
|
||||
registers to do so. Code which simply wishes to read or write GPIO data does not
|
||||
need access to these registers.
|
||||
|
||||
b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
|
||||
controllers, these registers are exposed via multiple "physical aliases" in
|
||||
address space, each of which access the same underlying state. See the hardware
|
||||
documentation for rationale. Any particular GPIO client is expected to access
|
||||
just one of these physical aliases.
|
||||
|
||||
Tegra HW documentation describes a unified naming convention for all GPIOs
|
||||
implemented by the SoC. Each GPIO is assigned to a port, and a port may control
|
||||
a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
|
||||
name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
|
||||
or GPIO_PCC3.
|
||||
|
||||
The number of ports implemented by each GPIO controller varies. The number of
|
||||
implemented GPIOs within each port varies. GPIO registers within a controller
|
||||
are grouped and laid out according to the port they affect.
|
||||
|
||||
The mapping from port name to the GPIO controller that implements that port, and
|
||||
the mapping from port name to register offset within a controller, are both
|
||||
extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
|
||||
describes the port-level mapping. In that file, the naming convention for ports
|
||||
matches the HW documentation. The values chosen for the names are alphabetically
|
||||
sorted within a particular controller. Drivers need to map between the DT GPIO
|
||||
IDs and HW register offsets using a lookup table.
|
||||
|
||||
Each GPIO controller can generate a number of interrupt signals. Each signal
|
||||
represents the aggregate status for all GPIOs within a set of ports. Thus, the
|
||||
number of interrupt signals generated by a controller varies as a rough function
|
||||
of the number of ports it implements. Note that the HW documentation refers to
|
||||
both the overall controller HW module and the sets-of-ports as "controllers".
|
||||
|
||||
Each GPIO controller in fact generates multiple interrupts signals for each set
|
||||
of ports. Each GPIO may be configured to feed into a specific one of the
|
||||
interrupt signals generated by a set-of-ports. The intent is for each generated
|
||||
signal to be routed to a different CPU, thus allowing different CPUs to each
|
||||
handle subsets of the interrupts within a port. The status of each of these
|
||||
per-port-set signals is reported via a separate register. Thus, a driver needs
|
||||
to know which status register to observe. This binding currently defines no
|
||||
configuration mechanism for this. By default, drivers should use register
|
||||
GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
|
||||
define a property to configure this.
|
||||
|
||||
Required properties:
|
||||
- compatible
|
||||
Array of strings.
|
||||
One of:
|
||||
- "nvidia,tegra186-gpio".
|
||||
- "nvidia,tegra186-gpio-aon".
|
||||
- reg-names
|
||||
Array of strings.
|
||||
Contains a list of names for the register spaces described by the reg
|
||||
property. May contain the following entries, in any order:
|
||||
- "gpio": Mandatory. GPIO control registers. This may cover either:
|
||||
a) The single physical alias that this OS should use.
|
||||
b) All physical aliases that exist in the controller. This is
|
||||
appropriate when the OS is responsible for managing assignment of
|
||||
the physical aliases.
|
||||
- "security": Optional. Security configuration registers.
|
||||
Users of this binding MUST look up entries in the reg property by name,
|
||||
using this reg-names property to do so.
|
||||
- reg
|
||||
Array of (physical base address, length) tuples.
|
||||
Must contain one entry per entry in the reg-names property, in a matching
|
||||
order.
|
||||
- interrupts
|
||||
Array of interrupt specifiers.
|
||||
The interrupt outputs from the HW block, one per set of ports, in the
|
||||
order the HW manual describes them. The number of entries required varies
|
||||
depending on compatible value:
|
||||
- "nvidia,tegra186-gpio": 6 entries.
|
||||
- "nvidia,tegra186-gpio-aon": 1 entry.
|
||||
- gpio-controller
|
||||
Boolean.
|
||||
Marks the device node as a GPIO controller/provider.
|
||||
- #gpio-cells
|
||||
Single-cell integer.
|
||||
Must be <2>.
|
||||
Indicates how many cells are used in a consumer's GPIO specifier.
|
||||
In the specifier:
|
||||
- The first cell is the pin number.
|
||||
See <dt-bindings/gpio/tegra186-gpio.h>.
|
||||
- The second cell contains flags:
|
||||
- Bit 0 specifies polarity
|
||||
- 0: Active-high (normal).
|
||||
- 1: Active-low (inverted).
|
||||
- interrupt-controller
|
||||
Boolean.
|
||||
Marks the device node as an interrupt controller/provider.
|
||||
- #interrupt-cells
|
||||
Single-cell integer.
|
||||
Must be <2>.
|
||||
Indicates how many cells are used in a consumer's interrupt specifier.
|
||||
In the specifier:
|
||||
- The first cell is the GPIO number.
|
||||
See <dt-bindings/gpio/tegra186-gpio.h>.
|
||||
- The second cell is contains flags:
|
||||
- Bits [3:0] indicate trigger type and level:
|
||||
- 1: Low-to-high edge triggered.
|
||||
- 2: High-to-low edge triggered.
|
||||
- 4: Active high level-sensitive.
|
||||
- 8: Active low level-sensitive.
|
||||
Valid combinations are 1, 2, 3, 4, 8.
|
||||
|
||||
Example:
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
gpio@2200000 {
|
||||
compatible = "nvidia,tegra186-gpio";
|
||||
reg-names = "security", "gpio";
|
||||
reg =
|
||||
<0x0 0x2200000 0x0 0x10000>,
|
||||
<0x0 0x2210000 0x0 0x10000>;
|
||||
interrupts =
|
||||
<0 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 56 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio@c2f0000 {
|
||||
compatible = "nvidia,tegra186-gpio-aon";
|
||||
reg-names = "security", "gpio";
|
||||
reg =
|
||||
<0x0 0xc2f0000 0x0 0x1000>,
|
||||
<0x0 0xc2f1000 0x0 0x1000>;
|
||||
interrupts =
|
||||
<0 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
Bindings for the Western Digital's MyBook Live memory-mapped GPIO controllers.
|
||||
|
||||
The Western Digital MyBook Live has two memory-mapped GPIO controllers.
|
||||
Both GPIO controller only have a single 8-bit data register, where GPIO
|
||||
state can be read and/or written.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "wd,mbl-gpio"
|
||||
- reg-names: must contain
|
||||
"dat" - data register
|
||||
- reg: address + size pairs describing the GPIO register sets;
|
||||
order must correspond with the order of entries in reg-names
|
||||
- #gpio-cells: must be set to 2. The first cell is the pin number and
|
||||
the second cell is used to specify the gpio polarity:
|
||||
0 = active high
|
||||
1 = active low
|
||||
- gpio-controller: Marks the device node as a gpio controller.
|
||||
|
||||
Optional properties:
|
||||
- no-output: GPIOs are read-only.
|
||||
|
||||
Examples:
|
||||
gpio0: gpio0@e0000000 {
|
||||
compatible = "wd,mbl-gpio";
|
||||
reg-names = "dat";
|
||||
reg = <0xe0000000 0x1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
gpio1: gpio1@e0100000 {
|
||||
compatible = "wd,mbl-gpio";
|
||||
reg-names = "dat";
|
||||
reg = <0xe0100000 0x1>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
no-output;
|
||||
};
|
||||
|
|
@ -1,9 +1,10 @@
|
|||
NVIDIA GK20A Graphics Processing Unit
|
||||
NVIDIA Tegra Graphics Processing Units
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,<chip>-<gpu>"
|
||||
- compatible: "nvidia,<gpu>"
|
||||
Currently recognized values:
|
||||
- nvidia,tegra124-gk20a
|
||||
- nvidia,gk20a
|
||||
- nvidia,gm20b
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
Must contain two entries:
|
||||
- first entry for bar0
|
||||
|
|
@ -19,14 +20,20 @@ Required properties:
|
|||
- clock-names: Must include the following entries:
|
||||
- gpu
|
||||
- pwr
|
||||
If the compatible string is "nvidia,gm20b", then the following clock
|
||||
is also required:
|
||||
- ref
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- gpu
|
||||
|
||||
Example:
|
||||
Optional properties:
|
||||
- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
|
||||
|
||||
gpu@0,57000000 {
|
||||
Example for GK20A:
|
||||
|
||||
gpu@57000000 {
|
||||
compatible = "nvidia,gk20a";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
|
|
@ -39,5 +46,25 @@ Example:
|
|||
clock-names = "gpu", "pwr";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
iommus = <&mc TEGRA_SWGROUP_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
Example for GM20B:
|
||||
|
||||
gpu@57000000 {
|
||||
compatible = "nvidia,gm20b";
|
||||
reg = <0x0 0x57000000 0x0 0x01000000>,
|
||||
<0x0 0x58000000 0x0 0x01000000>;
|
||||
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&tegra_car TEGRA210_CLK_GPU>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_G_REF>;
|
||||
clock-names = "gpu", "pwr", "ref";
|
||||
resets = <&tegra_car 184>;
|
||||
reset-names = "gpu";
|
||||
iommus = <&mc TEGRA_SWGROUP_GPU>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ Required properties:
|
|||
* "lltc,ltc3886"
|
||||
* "lltc,ltc3887"
|
||||
* "lltc,ltm2987"
|
||||
* "lltc,ltm4675"
|
||||
* "lltc,ltm4676"
|
||||
- reg: I2C slave address
|
||||
|
||||
|
|
|
|||
|
|
@ -4,6 +4,12 @@
|
|||
|
||||
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
|
||||
|
||||
or
|
||||
|
||||
compatible: "cavium,octeon-7890-twsi"
|
||||
|
||||
Compatibility with cn78XX SOCs.
|
||||
|
||||
- reg: The base address of the TWSI/I2C bus controller register bank.
|
||||
|
||||
- #address-cells: Must be <1>.
|
||||
|
|
|
|||
|
|
@ -19,6 +19,9 @@ Optional properties:
|
|||
- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
|
||||
property indicates the default frequency 100 kHz.
|
||||
- clocks: clock specifier.
|
||||
- dmas: Must contain a list of two references to DMA specifiers, one for
|
||||
transmission, and one for reception.
|
||||
- dma-names: Must contain a list of two DMA names, "tx" and "rx".
|
||||
|
||||
- i2c-scl-falling-time-ns: see i2c.txt
|
||||
- i2c-scl-internal-delay-ns: see i2c.txt
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC or MMA8653FC
|
||||
Freescale MMA8451Q, MMA8452Q, MMA8453Q, MMA8652FC, MMA8653FC or FXLS8471Q
|
||||
triaxial accelerometer
|
||||
|
||||
Required properties:
|
||||
|
|
@ -9,6 +9,7 @@ Required properties:
|
|||
* "fsl,mma8453"
|
||||
* "fsl,mma8652"
|
||||
* "fsl,mma8653"
|
||||
* "fsl,fxls8471"
|
||||
|
||||
- reg: the I2C address of the chip
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
NXP LPC1850 ADC bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "nxp,lpc1850-adc"
|
||||
- reg: Offset and length of the register set for the ADC device
|
||||
- interrupts: The interrupt number for the ADC device
|
||||
- clocks: The root clock of the ADC controller
|
||||
- vref-supply: The regulator supply ADC reference voltage
|
||||
- resets: phandle to reset controller and line specifier
|
||||
|
||||
Example:
|
||||
|
||||
adc0: adc@400e3000 {
|
||||
compatible = "nxp,lpc1850-adc";
|
||||
reg = <0x400e3000 0x1000>;
|
||||
interrupts = <17>;
|
||||
clocks = <&ccu1 CLK_APB3_ADC0>;
|
||||
vref-supply = <®_vdda>;
|
||||
resets = <&rgu 40>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,7 +1,11 @@
|
|||
Rockchip Successive Approximation Register (SAR) A/D Converter bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "rockchip,saradc" or "rockchip,rk3066-tsadc"
|
||||
- compatible: should be "rockchip,<name>-saradc" or "rockchip,rk3066-tsadc"
|
||||
- "rockchip,saradc": for rk3188, rk3288
|
||||
- "rockchip,rk3066-tsadc": for rk3036
|
||||
- "rockchip,rk3399-saradc": for rk3399
|
||||
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- interrupts: The interrupt number to the cpu. The interrupt specifier format
|
||||
|
|
|
|||
|
|
@ -0,0 +1,155 @@
|
|||
Analog Devices AD5592R/AD5593R DAC/ADC device driver
|
||||
|
||||
Required properties for the AD5592R:
|
||||
- compatible: Must be "adi,ad5592r"
|
||||
- reg: SPI chip select number for the device
|
||||
- spi-max-frequency: Max SPI frequency to use (< 30000000)
|
||||
- spi-cpol: The AD5592R requires inverse clock polarity (CPOL) mode
|
||||
|
||||
Required properties for the AD5593R:
|
||||
- compatible: Must be "adi,ad5593r"
|
||||
- reg: I2C address of the device
|
||||
|
||||
Required properties for all supported chips:
|
||||
- #address-cells: Should be 1.
|
||||
- #size-cells: Should be 0.
|
||||
- channel nodes:
|
||||
Each child node represents one channel and has the following
|
||||
Required properties:
|
||||
* reg: Pin on which this channel is connected to.
|
||||
* adi,mode: Mode or function of this channel.
|
||||
Macros specifying the valid values
|
||||
can be found in <dt-bindings/iio/adi,ad5592r.h>.
|
||||
|
||||
The following values are currently supported:
|
||||
* CH_MODE_UNUSED (the pin is unused)
|
||||
* CH_MODE_ADC (the pin is ADC input)
|
||||
* CH_MODE_DAC (the pin is DAC output)
|
||||
* CH_MODE_DAC_AND_ADC (the pin is DAC output
|
||||
but can be monitored by an ADC, since
|
||||
there is no disadvantage this
|
||||
this should be considered as the
|
||||
preferred DAC mode)
|
||||
* CH_MODE_GPIO (the pin is registered
|
||||
with GPIOLIB)
|
||||
Optional properties:
|
||||
* adi,off-state: State of this channel when unused or the
|
||||
device gets removed. Macros specifying the
|
||||
valid values can be found in
|
||||
<dt-bindings/iio/adi,ad5592r.h>.
|
||||
|
||||
* CH_OFFSTATE_PULLDOWN (the pin is pulled down)
|
||||
* CH_OFFSTATE_OUT_LOW (the pin is output low)
|
||||
* CH_OFFSTATE_OUT_HIGH (the pin is output high)
|
||||
* CH_OFFSTATE_OUT_TRISTATE (the pin is
|
||||
tristated output)
|
||||
|
||||
|
||||
Optional properties:
|
||||
- vref-supply: Phandle to the external reference voltage supply. This should
|
||||
only be set if there is an external reference voltage connected to the VREF
|
||||
pin. If the property is not set the internal 2.5V reference is used.
|
||||
- reset-gpios : GPIO spec for the RESET pin. If specified, it will be
|
||||
asserted during driver probe.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells: Should be 2. The first cell is the GPIO number and the second
|
||||
cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>.
|
||||
|
||||
AD5592R Example:
|
||||
|
||||
#include <dt-bindings/iio/adi,ad5592r.h>
|
||||
|
||||
vref: regulator-vref {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vref-ad559x";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ad5592r@0 {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#gpio-cells = <2>;
|
||||
compatible = "adi,ad5592r";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <1000000>;
|
||||
spi-cpol;
|
||||
|
||||
vref-supply = <&vref>; /* optional */
|
||||
reset-gpios = <&gpio0 86 0>; /* optional */
|
||||
gpio-controller;
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
adi,mode = <CH_MODE_DAC>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
adi,mode = <CH_MODE_ADC>;
|
||||
};
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
adi,mode = <CH_MODE_DAC_AND_ADC>;
|
||||
};
|
||||
channel@3 {
|
||||
reg = <3>;
|
||||
adi,mode = <CH_MODE_DAC_AND_ADC>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@4 {
|
||||
reg = <4>;
|
||||
adi,mode = <CH_MODE_UNUSED>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@5 {
|
||||
reg = <5>;
|
||||
adi,mode = <CH_MODE_GPIO>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
adi,mode = <CH_MODE_GPIO>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@7 {
|
||||
reg = <7>;
|
||||
adi,mode = <CH_MODE_GPIO>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
};
|
||||
|
||||
AD5593R Example:
|
||||
|
||||
#include <dt-bindings/iio/adi,ad5592r.h>
|
||||
|
||||
ad5593r@10 {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
#gpio-cells = <2>;
|
||||
compatible = "adi,ad5593r";
|
||||
reg = <0x10>;
|
||||
gpio-controller;
|
||||
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
adi,mode = <CH_MODE_DAC>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@1 {
|
||||
reg = <1>;
|
||||
adi,mode = <CH_MODE_ADC>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@2 {
|
||||
reg = <2>;
|
||||
adi,mode = <CH_MODE_DAC_AND_ADC>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
channel@6 {
|
||||
reg = <6>;
|
||||
adi,mode = <CH_MODE_GPIO>;
|
||||
adi,off-state = <CH_OFFSTATE_PULLDOWN>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
NXP LPC1850 DAC bindings
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "nxp,lpc1850-dac"
|
||||
- reg: Offset and length of the register set for the ADC device
|
||||
- interrupts: The interrupt number for the ADC device
|
||||
- clocks: The root clock of the ADC controller
|
||||
- vref-supply: The regulator supply ADC reference voltage
|
||||
- resets: phandle to reset controller and line specifier
|
||||
|
||||
Example:
|
||||
dac: dac@400e1000 {
|
||||
compatible = "nxp,lpc1850-dac";
|
||||
reg = <0x400e1000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&ccu1 CLK_APB3_DAC>;
|
||||
vref-supply = <®_vdda>;
|
||||
resets = <&rgu 42>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -8,10 +8,23 @@ Required properties:
|
|||
- interrupt-parent : should be the phandle for the interrupt controller
|
||||
- interrupts : interrupt mapping for GPIO IRQ
|
||||
|
||||
Optional properties:
|
||||
- mount-matrix: an optional 3x3 mounting rotation matrix
|
||||
|
||||
|
||||
Example:
|
||||
mpu6050@68 {
|
||||
compatible = "invensense,mpu6050";
|
||||
reg = <0x68>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <18 1>;
|
||||
mount-matrix = "-0.984807753012208", /* x0 */
|
||||
"0", /* y0 */
|
||||
"-0.173648177666930", /* z0 */
|
||||
"0", /* x1 */
|
||||
"-1", /* y1 */
|
||||
"0", /* z1 */
|
||||
"-0.173648177666930", /* x2 */
|
||||
"0", /* y2 */
|
||||
"0.984807753012208"; /* z2 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -8,6 +8,8 @@ Required properties:
|
|||
Optional properties:
|
||||
|
||||
- gpios : should be device tree identifier of the magnetometer DRDY pin
|
||||
- vdd-supply: an optional regulator that needs to be on to provide VDD
|
||||
- mount-matrix: an optional 3x3 mounting rotation matrix
|
||||
|
||||
Example:
|
||||
|
||||
|
|
@ -15,4 +17,14 @@ ak8975@0c {
|
|||
compatible = "asahi-kasei,ak8975";
|
||||
reg = <0x0c>;
|
||||
gpios = <&gpj0 7 0>;
|
||||
vdd-supply = <&ldo_3v3_gnss>;
|
||||
mount-matrix = "-0.984807753012208", /* x0 */
|
||||
"0", /* y0 */
|
||||
"-0.173648177666930", /* z0 */
|
||||
"0", /* x1 */
|
||||
"-1", /* y1 */
|
||||
"0", /* z1 */
|
||||
"-0.173648177666930", /* x2 */
|
||||
"0", /* y2 */
|
||||
"0.984807753012208"; /* z2 */
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,21 @@
|
|||
* Maxim Integrated DS1803 digital potentiometer driver
|
||||
|
||||
The node for this driver must be a child node of a I2C controller, hence
|
||||
all mandatory properties for your controller must be specified. See directory:
|
||||
|
||||
Documentation/devicetree/bindings/i2c
|
||||
|
||||
for more details.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of the following, depending on the
|
||||
model:
|
||||
"maxim,ds1803-010",
|
||||
"maxim,ds1803-050",
|
||||
"maxim,ds1803-100"
|
||||
|
||||
Example:
|
||||
ds1803: ds1803@1 {
|
||||
reg = <0x28>;
|
||||
compatible = "maxim,ds1803-010";
|
||||
};
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
* Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X Digital Potentiometer
|
||||
driver
|
||||
|
||||
The node for this driver must be a child node of a SPI controller, hence
|
||||
all mandatory properties described in
|
||||
|
||||
Documentation/devicetree/bindings/spi/spi-bus.txt
|
||||
|
||||
must be specified.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be one of the following, depending on the
|
||||
model:
|
||||
"microchip,mcp4131-502"
|
||||
"microchip,mcp4131-103"
|
||||
"microchip,mcp4131-503"
|
||||
"microchip,mcp4131-104"
|
||||
"microchip,mcp4132-502"
|
||||
"microchip,mcp4132-103"
|
||||
"microchip,mcp4132-503"
|
||||
"microchip,mcp4132-104"
|
||||
"microchip,mcp4141-502"
|
||||
"microchip,mcp4141-103"
|
||||
"microchip,mcp4141-503"
|
||||
"microchip,mcp4141-104"
|
||||
"microchip,mcp4142-502"
|
||||
"microchip,mcp4142-103"
|
||||
"microchip,mcp4142-503"
|
||||
"microchip,mcp4142-104"
|
||||
"microchip,mcp4151-502"
|
||||
"microchip,mcp4151-103"
|
||||
"microchip,mcp4151-503"
|
||||
"microchip,mcp4151-104"
|
||||
"microchip,mcp4152-502"
|
||||
"microchip,mcp4152-103"
|
||||
"microchip,mcp4152-503"
|
||||
"microchip,mcp4152-104"
|
||||
"microchip,mcp4161-502"
|
||||
"microchip,mcp4161-103"
|
||||
"microchip,mcp4161-503"
|
||||
"microchip,mcp4161-104"
|
||||
"microchip,mcp4162-502"
|
||||
"microchip,mcp4162-103"
|
||||
"microchip,mcp4162-503"
|
||||
"microchip,mcp4162-104"
|
||||
"microchip,mcp4231-502"
|
||||
"microchip,mcp4231-103"
|
||||
"microchip,mcp4231-503"
|
||||
"microchip,mcp4231-104"
|
||||
"microchip,mcp4232-502"
|
||||
"microchip,mcp4232-103"
|
||||
"microchip,mcp4232-503"
|
||||
"microchip,mcp4232-104"
|
||||
"microchip,mcp4241-502"
|
||||
"microchip,mcp4241-103"
|
||||
"microchip,mcp4241-503"
|
||||
"microchip,mcp4241-104"
|
||||
"microchip,mcp4242-502"
|
||||
"microchip,mcp4242-103"
|
||||
"microchip,mcp4242-503"
|
||||
"microchip,mcp4242-104"
|
||||
"microchip,mcp4251-502"
|
||||
"microchip,mcp4251-103"
|
||||
"microchip,mcp4251-503"
|
||||
"microchip,mcp4251-104"
|
||||
"microchip,mcp4252-502"
|
||||
"microchip,mcp4252-103"
|
||||
"microchip,mcp4252-503"
|
||||
"microchip,mcp4252-104"
|
||||
"microchip,mcp4261-502"
|
||||
"microchip,mcp4261-103"
|
||||
"microchip,mcp4261-503"
|
||||
"microchip,mcp4261-104"
|
||||
"microchip,mcp4262-502"
|
||||
"microchip,mcp4262-103"
|
||||
"microchip,mcp4262-503"
|
||||
"microchip,mcp4262-104"
|
||||
|
||||
Example:
|
||||
mcp4131: mcp4131@0 {
|
||||
compatible = "mcp4131-502";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <500000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
HopeRF HP03 digital pressure/temperature sensors
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "hoperf,hp03"
|
||||
- xclr-gpio: must be device tree identifier of the XCLR pin.
|
||||
The XCLR pin is a reset of the ADC in the chip,
|
||||
it must be pulled HI before the conversion and
|
||||
readout of the value from the ADC registers and
|
||||
pulled LO afterward.
|
||||
|
||||
Example:
|
||||
|
||||
hp03@0x77 {
|
||||
compatible = "hoperf,hp03";
|
||||
reg = <0x77>;
|
||||
xclr-gpio = <&portc 0 0x0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
MEAS ms5611 family pressure sensors
|
||||
|
||||
Pressure sensors from MEAS Switzerland with SPI and I2C bus interfaces.
|
||||
|
||||
Required properties:
|
||||
- compatible: "meas,ms5611" or "meas,ms5607"
|
||||
- reg: the I2C address or SPI chip select the device will respond to
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: an optional regulator that needs to be on to provide VDD
|
||||
power to the sensor.
|
||||
|
||||
Example:
|
||||
|
||||
ms5607@77 {
|
||||
compatible = "meas,ms5607";
|
||||
reg = <0x77>;
|
||||
vdd-supply = <&ldo_3v3_gnss>;
|
||||
};
|
||||
|
|
@ -16,6 +16,10 @@ Optional properties:
|
|||
- st,drdy-int-pin: the pin on the package that will be used to signal
|
||||
"data ready" (valid values: 1 or 2). This property is not configurable
|
||||
on all sensors.
|
||||
- drive-open-drain: the interrupt/data ready line will be configured
|
||||
as open drain, which is useful if several sensors share the same
|
||||
interrupt line. (This binding is taken from pinctrl/pinctrl-bindings.txt)
|
||||
This is a boolean property.
|
||||
|
||||
Sensors may also have applicable pin control settings, those use the
|
||||
standard bindings from pinctrl/pinctrl-bindings.txt.
|
||||
|
|
@ -37,6 +41,7 @@ Accelerometers:
|
|||
- st,lsm330-accel
|
||||
- st,lsm303agr-accel
|
||||
- st,lis2dh12-accel
|
||||
- st,h3lis331dl-accel
|
||||
|
||||
Gyroscopes:
|
||||
- st,l3g4200d-gyro
|
||||
|
|
@ -46,6 +51,7 @@ Gyroscopes:
|
|||
- st,l3gd20-gyro
|
||||
- st,l3g4is-gyro
|
||||
- st,lsm330-gyro
|
||||
- st,lsm9ds0-gyro
|
||||
|
||||
Magnetometers:
|
||||
- st,lsm303agr-magn
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ Optional properties:
|
|||
ti,vref-delay-usecs vref supply delay in usecs, 0 for
|
||||
external vref (u16).
|
||||
ti,vref-mv The VREF voltage, in millivolts (u16).
|
||||
Set to 0 to use internal refernce
|
||||
Set to 0 to use internal references
|
||||
(ADS7846).
|
||||
ti,keep-vref-on set to keep vref on for differential
|
||||
measurements as well
|
||||
|
|
|
|||
|
|
@ -32,17 +32,17 @@ Optional subnode-properties:
|
|||
|
||||
Example nodes:
|
||||
|
||||
gpio_keys {
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
button@21 {
|
||||
|
||||
up {
|
||||
label = "GPIO Key UP";
|
||||
linux,code = <103>;
|
||||
gpios = <&gpio1 0 1>;
|
||||
};
|
||||
button@22 {
|
||||
|
||||
down {
|
||||
label = "GPIO Key DOWN";
|
||||
linux,code = <108>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
|
|
|
|||
|
|
@ -2,11 +2,17 @@
|
|||
|
||||
Required properties:
|
||||
- compatible: must be "brcm,iproc-touchscreen"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- ts_syscon: handler of syscon node defining physical base
|
||||
address of the controller and length of memory mapped region.
|
||||
If this property is selected please make sure MFD_SYSCON config
|
||||
is enabled in the defconfig file.
|
||||
- clocks: The clock provided by the SOC to driver the tsc
|
||||
- clock-name: name for the clock
|
||||
- clock-names: name for the clock
|
||||
- interrupts: The touchscreen controller's interrupt
|
||||
- address-cells: Specify the number of u32 entries needed in child nodes.
|
||||
Should set to 1.
|
||||
- size-cells: Specify number of u32 entries needed to specify child nodes size
|
||||
in reg property. Should set to 1.
|
||||
|
||||
Optional properties:
|
||||
- scanning_period: Time between scans. Each step is 1024 us. Valid 1-256.
|
||||
|
|
@ -53,13 +59,18 @@ Optional properties:
|
|||
- touchscreen-inverted-x: X axis is inverted (boolean)
|
||||
- touchscreen-inverted-y: Y axis is inverted (boolean)
|
||||
|
||||
Example:
|
||||
Example: An example of touchscreen node
|
||||
|
||||
touchscreen: tsc@0x180A6000 {
|
||||
ts_adc_syscon: ts_adc_syscon@180a6000 {
|
||||
compatible = "brcm,iproc-ts-adc-syscon","syscon";
|
||||
reg = <0x180a6000 0xc30>;
|
||||
};
|
||||
|
||||
touchscreen: touchscreen@180A6000 {
|
||||
compatible = "brcm,iproc-touchscreen";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x180A6000 0x40>;
|
||||
ts_syscon = <&ts_adc_syscon>;
|
||||
clocks = <&adc_clk>;
|
||||
clock-names = "tsc_clk";
|
||||
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@ Optional properties:
|
|||
- fsl,pen-debounce-ns: Pen debounce time in nanoseconds.
|
||||
- fsl,pen-threshold: Pen-down threshold for the touchscreen. This is a value
|
||||
between 1 and 4096. It is the ratio between the internal reference voltage
|
||||
and the measured voltage after the plate was precharged. Resistence between
|
||||
and the measured voltage after the plate was precharged. Resistance between
|
||||
plates and therefore the voltage decreases with pressure so that a smaller
|
||||
value is equivalent to a higher pressure.
|
||||
- fsl,settling-time-ns: Settling time in nanoseconds. The settling time is before
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue