Merge branch 'for-next/net'
This commit is contained in:
commit
874b8ac790
|
@ -73,6 +73,20 @@ config DRIVER_NET_DM9K
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depends on HAS_DM9000
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select PHYLIB
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config DRIVER_NET_ENC28J60
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bool "ENC28J60 support"
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depends on SPI
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select PHYLIB
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---help---
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Support for the Microchip EN28J60 ethernet chip.
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config DRIVER_NET_ENC28J60_WRITEVERIFY
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bool "Enable write verify"
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depends on DRIVER_NET_ENC28J60
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---help---
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Enable the verify after the buffer write useful for debugging purpose.
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If unsure, say N.
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config DRIVER_NET_EP93XX
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bool "EP93xx Ethernet driver"
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depends on ARCH_EP93XX
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@ -10,6 +10,7 @@ obj-$(CONFIG_DRIVER_NET_CPSW) += cpsw.o
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obj-$(CONFIG_DRIVER_NET_DAVINCI_EMAC) += davinci_emac.o
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obj-$(CONFIG_DRIVER_NET_DESIGNWARE) += designware.o
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obj-$(CONFIG_DRIVER_NET_DM9K) += dm9k.o
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obj-$(CONFIG_DRIVER_NET_ENC28J60) += enc28j60.o
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obj-$(CONFIG_DRIVER_NET_EP93XX) += ep93xx.o
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obj-$(CONFIG_DRIVER_NET_ETHOC) += ethoc.o
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obj-$(CONFIG_DRIVER_NET_FEC_IMX) += fec_imx.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,307 @@
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/*
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* enc28j60_hw.h: EDTP FrameThrower style enc28j60 registers
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*/
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#ifndef _ENC28J60_HW_H
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#define _ENC28J60_HW_H
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/*
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* ENC28J60 Control Registers
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* Control register definitions are a combination of address,
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* bank number, and Ethernet/MAC/PHY indicator bits.
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* - Register address (bits 0-4)
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* - Bank number (bits 5-6)
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* - MAC/MII indicator (bit 7)
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*/
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#define ADDR_MASK 0x1F
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#define BANK_MASK 0x60
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#define SPRD_MASK 0x80
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/* All-bank registers */
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#define EIE 0x1B
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#define EIR 0x1C
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#define ESTAT 0x1D
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#define ECON2 0x1E
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#define ECON1 0x1F
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/* Bank 0 registers */
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#define ERDPTL (0x00|0x00)
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#define ERDPTH (0x01|0x00)
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#define EWRPTL (0x02|0x00)
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#define EWRPTH (0x03|0x00)
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#define ETXSTL (0x04|0x00)
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#define ETXSTH (0x05|0x00)
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#define ETXNDL (0x06|0x00)
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#define ETXNDH (0x07|0x00)
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#define ERXSTL (0x08|0x00)
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#define ERXSTH (0x09|0x00)
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#define ERXNDL (0x0A|0x00)
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#define ERXNDH (0x0B|0x00)
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#define ERXRDPTL (0x0C|0x00)
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#define ERXRDPTH (0x0D|0x00)
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#define ERXWRPTL (0x0E|0x00)
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#define ERXWRPTH (0x0F|0x00)
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#define EDMASTL (0x10|0x00)
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#define EDMASTH (0x11|0x00)
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#define EDMANDL (0x12|0x00)
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#define EDMANDH (0x13|0x00)
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#define EDMADSTL (0x14|0x00)
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#define EDMADSTH (0x15|0x00)
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#define EDMACSL (0x16|0x00)
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#define EDMACSH (0x17|0x00)
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/* Bank 1 registers */
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#define EHT0 (0x00|0x20)
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#define EHT1 (0x01|0x20)
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#define EHT2 (0x02|0x20)
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#define EHT3 (0x03|0x20)
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#define EHT4 (0x04|0x20)
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#define EHT5 (0x05|0x20)
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#define EHT6 (0x06|0x20)
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#define EHT7 (0x07|0x20)
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#define EPMM0 (0x08|0x20)
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#define EPMM1 (0x09|0x20)
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#define EPMM2 (0x0A|0x20)
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#define EPMM3 (0x0B|0x20)
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#define EPMM4 (0x0C|0x20)
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#define EPMM5 (0x0D|0x20)
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#define EPMM6 (0x0E|0x20)
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#define EPMM7 (0x0F|0x20)
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#define EPMCSL (0x10|0x20)
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#define EPMCSH (0x11|0x20)
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#define EPMOL (0x14|0x20)
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#define EPMOH (0x15|0x20)
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#define EWOLIE (0x16|0x20)
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#define EWOLIR (0x17|0x20)
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#define ERXFCON (0x18|0x20)
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#define EPKTCNT (0x19|0x20)
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/* Bank 2 registers */
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#define MACON1 (0x00|0x40|SPRD_MASK)
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/* #define MACON2 (0x01|0x40|SPRD_MASK) */
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#define MACON3 (0x02|0x40|SPRD_MASK)
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#define MACON4 (0x03|0x40|SPRD_MASK)
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#define MABBIPG (0x04|0x40|SPRD_MASK)
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#define MAIPGL (0x06|0x40|SPRD_MASK)
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#define MAIPGH (0x07|0x40|SPRD_MASK)
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#define MACLCON1 (0x08|0x40|SPRD_MASK)
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#define MACLCON2 (0x09|0x40|SPRD_MASK)
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#define MAMXFLL (0x0A|0x40|SPRD_MASK)
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#define MAMXFLH (0x0B|0x40|SPRD_MASK)
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#define MAPHSUP (0x0D|0x40|SPRD_MASK)
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#define MICON (0x11|0x40|SPRD_MASK)
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#define MICMD (0x12|0x40|SPRD_MASK)
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#define MIREGADR (0x14|0x40|SPRD_MASK)
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#define MIWRL (0x16|0x40|SPRD_MASK)
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#define MIWRH (0x17|0x40|SPRD_MASK)
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#define MIRDL (0x18|0x40|SPRD_MASK)
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#define MIRDH (0x19|0x40|SPRD_MASK)
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/* Bank 3 registers */
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#define MAADR1 (0x00|0x60|SPRD_MASK)
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#define MAADR0 (0x01|0x60|SPRD_MASK)
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#define MAADR3 (0x02|0x60|SPRD_MASK)
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#define MAADR2 (0x03|0x60|SPRD_MASK)
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#define MAADR5 (0x04|0x60|SPRD_MASK)
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#define MAADR4 (0x05|0x60|SPRD_MASK)
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#define EBSTSD (0x06|0x60)
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#define EBSTCON (0x07|0x60)
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#define EBSTCSL (0x08|0x60)
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#define EBSTCSH (0x09|0x60)
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#define MISTAT (0x0A|0x60|SPRD_MASK)
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#define EREVID (0x12|0x60)
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#define ECOCON (0x15|0x60)
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#define EFLOCON (0x17|0x60)
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#define EPAUSL (0x18|0x60)
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#define EPAUSH (0x19|0x60)
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/* PHY registers */
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#define PHCON1 0x00
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#define PHSTAT1 0x01
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#define PHHID1 0x02
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#define PHHID2 0x03
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#define PHCON2 0x10
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#define PHSTAT2 0x11
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#define PHIE 0x12
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#define PHIR 0x13
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#define PHLCON 0x14
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/* ENC28J60 EIE Register Bit Definitions */
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#define EIE_INTIE 0x80
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#define EIE_PKTIE 0x40
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#define EIE_DMAIE 0x20
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#define EIE_LINKIE 0x10
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#define EIE_TXIE 0x08
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/* #define EIE_WOLIE 0x04 (reserved) */
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#define EIE_TXERIE 0x02
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#define EIE_RXERIE 0x01
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/* ENC28J60 EIR Register Bit Definitions */
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#define EIR_PKTIF 0x40
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#define EIR_DMAIF 0x20
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#define EIR_LINKIF 0x10
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#define EIR_TXIF 0x08
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/* #define EIR_WOLIF 0x04 (reserved) */
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#define EIR_TXERIF 0x02
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#define EIR_RXERIF 0x01
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/* ENC28J60 ESTAT Register Bit Definitions */
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#define ESTAT_INT 0x80
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#define ESTAT_LATECOL 0x10
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#define ESTAT_RXBUSY 0x04
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#define ESTAT_TXABRT 0x02
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#define ESTAT_CLKRDY 0x01
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/* ENC28J60 ECON2 Register Bit Definitions */
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#define ECON2_AUTOINC 0x80
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#define ECON2_PKTDEC 0x40
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#define ECON2_PWRSV 0x20
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#define ECON2_VRPS 0x08
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/* ENC28J60 ECON1 Register Bit Definitions */
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#define ECON1_TXRST 0x80
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#define ECON1_RXRST 0x40
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#define ECON1_DMAST 0x20
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#define ECON1_CSUMEN 0x10
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#define ECON1_TXRTS 0x08
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#define ECON1_RXEN 0x04
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#define ECON1_BSEL1 0x02
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#define ECON1_BSEL0 0x01
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/* ENC28J60 MACON1 Register Bit Definitions */
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#define MACON1_LOOPBK 0x10
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#define MACON1_TXPAUS 0x08
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#define MACON1_RXPAUS 0x04
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#define MACON1_PASSALL 0x02
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#define MACON1_MARXEN 0x01
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/* ENC28J60 MACON2 Register Bit Definitions */
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#define MACON2_MARST 0x80
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#define MACON2_RNDRST 0x40
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#define MACON2_MARXRST 0x08
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#define MACON2_RFUNRST 0x04
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#define MACON2_MATXRST 0x02
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#define MACON2_TFUNRST 0x01
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/* ENC28J60 MACON3 Register Bit Definitions */
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#define MACON3_PADCFG2 0x80
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#define MACON3_PADCFG1 0x40
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#define MACON3_PADCFG0 0x20
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#define MACON3_TXCRCEN 0x10
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#define MACON3_PHDRLEN 0x08
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#define MACON3_HFRMLEN 0x04
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#define MACON3_FRMLNEN 0x02
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#define MACON3_FULDPX 0x01
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/* ENC28J60 MICMD Register Bit Definitions */
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#define MICMD_MIISCAN 0x02
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#define MICMD_MIIRD 0x01
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/* ENC28J60 MISTAT Register Bit Definitions */
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#define MISTAT_NVALID 0x04
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#define MISTAT_SCAN 0x02
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#define MISTAT_BUSY 0x01
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/* ENC28J60 ERXFCON Register Bit Definitions */
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#define ERXFCON_UCEN 0x80
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#define ERXFCON_ANDOR 0x40
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#define ERXFCON_CRCEN 0x20
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#define ERXFCON_PMEN 0x10
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#define ERXFCON_MPEN 0x08
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#define ERXFCON_HTEN 0x04
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#define ERXFCON_MCEN 0x02
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#define ERXFCON_BCEN 0x01
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/* ENC28J60 PHY PHCON1 Register Bit Definitions */
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#define PHCON1_PRST 0x8000
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#define PHCON1_PLOOPBK 0x4000
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#define PHCON1_PPWRSV 0x0800
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#define PHCON1_PDPXMD 0x0100
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/* ENC28J60 PHY PHSTAT1 Register Bit Definitions */
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#define PHSTAT1_PFDPX 0x1000
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#define PHSTAT1_PHDPX 0x0800
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#define PHSTAT1_LLSTAT 0x0004
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#define PHSTAT1_JBSTAT 0x0002
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/* ENC28J60 PHY PHSTAT2 Register Bit Definitions */
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#define PHSTAT2_TXSTAT (1 << 13)
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#define PHSTAT2_RXSTAT (1 << 12)
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#define PHSTAT2_COLSTAT (1 << 11)
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#define PHSTAT2_LSTAT (1 << 10)
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#define PHSTAT2_DPXSTAT (1 << 9)
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#define PHSTAT2_PLRITY (1 << 5)
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||||
/* ENC28J60 PHY PHCON2 Register Bit Definitions */
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#define PHCON2_FRCLINK 0x4000
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#define PHCON2_TXDIS 0x2000
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||||
#define PHCON2_JABBER 0x0400
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#define PHCON2_HDLDIS 0x0100
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/* ENC28J60 PHY PHIE Register Bit Definitions */
|
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#define PHIE_PLNKIE (1 << 4)
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||||
#define PHIE_PGEIE (1 << 1)
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||||
/* ENC28J60 PHY PHIR Register Bit Definitions */
|
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#define PHIR_PLNKIF (1 << 4)
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#define PHIR_PGEIF (1 << 1)
|
||||
|
||||
/* ENC28J60 Packet Control Byte Bit Definitions */
|
||||
#define PKTCTRL_PHUGEEN 0x08
|
||||
#define PKTCTRL_PPADEN 0x04
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||||
#define PKTCTRL_PCRCEN 0x02
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||||
#define PKTCTRL_POVERRIDE 0x01
|
||||
|
||||
/* ENC28J60 Transmit Status Vector */
|
||||
#define TSV_TXBYTECNT 0
|
||||
#define TSV_TXCOLLISIONCNT 16
|
||||
#define TSV_TXCRCERROR 20
|
||||
#define TSV_TXLENCHKERROR 21
|
||||
#define TSV_TXLENOUTOFRANGE 22
|
||||
#define TSV_TXDONE 23
|
||||
#define TSV_TXMULTICAST 24
|
||||
#define TSV_TXBROADCAST 25
|
||||
#define TSV_TXPACKETDEFER 26
|
||||
#define TSV_TXEXDEFER 27
|
||||
#define TSV_TXEXCOLLISION 28
|
||||
#define TSV_TXLATECOLLISION 29
|
||||
#define TSV_TXGIANT 30
|
||||
#define TSV_TXUNDERRUN 31
|
||||
#define TSV_TOTBYTETXONWIRE 32
|
||||
#define TSV_TXCONTROLFRAME 48
|
||||
#define TSV_TXPAUSEFRAME 49
|
||||
#define TSV_BACKPRESSUREAPP 50
|
||||
#define TSV_TXVLANTAGFRAME 51
|
||||
|
||||
#define TSV_SIZE 7
|
||||
#define TSV_BYTEOF(x) ((x) / 8)
|
||||
#define TSV_BITMASK(x) (1 << ((x) % 8))
|
||||
#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
|
||||
|
||||
/* ENC28J60 Receive Status Vector */
|
||||
#define RSV_RXLONGEVDROPEV 16
|
||||
#define RSV_CARRIEREV 18
|
||||
#define RSV_CRCERROR 20
|
||||
#define RSV_LENCHECKERR 21
|
||||
#define RSV_LENOUTOFRANGE 22
|
||||
#define RSV_RXOK 23
|
||||
#define RSV_RXMULTICAST 24
|
||||
#define RSV_RXBROADCAST 25
|
||||
#define RSV_DRIBBLENIBBLE 26
|
||||
#define RSV_RXCONTROLFRAME 27
|
||||
#define RSV_RXPAUSEFRAME 28
|
||||
#define RSV_RXUNKNOWNOPCODE 29
|
||||
#define RSV_RXTYPEVLAN 30
|
||||
|
||||
#define RSV_SIZE 6
|
||||
#define RSV_BITMASK(x) (1 << ((x) - 16))
|
||||
#define RSV_GETBIT(x, y) (((x) & RSV_BITMASK(y)) ? 1 : 0)
|
||||
|
||||
|
||||
/* SPI operation codes */
|
||||
#define ENC28J60_READ_CTRL_REG 0x00
|
||||
#define ENC28J60_READ_BUF_MEM 0x3A
|
||||
#define ENC28J60_WRITE_CTRL_REG 0x40
|
||||
#define ENC28J60_WRITE_BUF_MEM 0x7A
|
||||
#define ENC28J60_BIT_FIELD_SET 0x80
|
||||
#define ENC28J60_BIT_FIELD_CLR 0xA0
|
||||
#define ENC28J60_SOFT_RESET 0xFF
|
||||
|
||||
|
||||
/* buffer boundaries applied to internal 8K ram
|
||||
* entire available packet buffer space is allocated.
|
||||
* Give TX buffer space for one full ethernet frame (~1500 bytes)
|
||||
* receive buffer gets the rest */
|
||||
#define TXSTART_INIT 0x1A00
|
||||
#define TXEND_INIT 0x1FFF
|
||||
|
||||
/* Put RX buffer at 0 as suggested by the Errata datasheet */
|
||||
#define RXSTART_INIT 0x0000
|
||||
#define RXEND_INIT 0x19FF
|
||||
|
||||
/* maximum ethernet frame length */
|
||||
#define MAX_FRAMELEN 1518
|
||||
|
||||
/* Preferred half duplex: LEDA: Link status LEDB: Rx/Tx activity */
|
||||
#define ENC28J60_LAMPS_MODE 0x3476
|
||||
|
||||
#endif
|
|
@ -399,6 +399,7 @@ static int port_open(struct eth_device *edev)
|
|||
|
||||
static int port_probe(struct device_d *parent, struct port_priv *port)
|
||||
{
|
||||
struct orion_gbe *gbe = parent->priv;
|
||||
struct device_d *dev = &port->dev;
|
||||
u32 reg;
|
||||
int ret;
|
||||
|
@ -446,11 +447,14 @@ static int port_probe(struct device_d *parent, struct port_priv *port)
|
|||
|
||||
reg = SC1_RESERVED;
|
||||
reg |= DEFAULT_COL_LIMIT | COL_ON_BACKPRESS | INBAND_ANEG_BYPASS;
|
||||
if (port->intf == PHY_INTERFACE_MODE_RGMII)
|
||||
if (port->intf == PHY_INTERFACE_MODE_RGMII ||
|
||||
port->intf == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
port->intf == PHY_INTERFACE_MODE_RGMII_RXID ||
|
||||
port->intf == PHY_INTERFACE_MODE_RGMII_TXID)
|
||||
reg |= RGMII_ENABLE;
|
||||
writel(reg, port->regs + PORT_SC1);
|
||||
|
||||
sprintf(dev->name, "orion-gbe-port");
|
||||
snprintf(dev->name, MAX_DRIVER_NAME, "%08x.ethernet-port", (u32)gbe->regs);
|
||||
dev->id = port->portno;
|
||||
dev->parent = parent;
|
||||
dev->device_node = port->np;
|
||||
|
|
|
@ -18,6 +18,11 @@ config LXT_PHY
|
|||
---help---
|
||||
Currently supports the lxt971 PHY.
|
||||
|
||||
config MARVELL_PHY
|
||||
tristate "Drivers for Marvell PHYs"
|
||||
---help---
|
||||
Add support for various Marvell PHYs (e.g. 88E1121R).
|
||||
|
||||
config MICREL_PHY
|
||||
bool "Driver for Micrel PHYs"
|
||||
---help---
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
obj-y += phy.o mdio_bus.o
|
||||
obj-$(CONFIG_AT803X_PHY) += at803x.o
|
||||
obj-$(CONFIG_LXT_PHY) += lxt.o
|
||||
obj-$(CONFIG_MARVELL_PHY) += marvell.o
|
||||
obj-$(CONFIG_MICREL_PHY) += micrel.o
|
||||
obj-$(CONFIG_NATIONAL_PHY) += national.o
|
||||
obj-$(CONFIG_SMSC_PHY) += smsc.o
|
||||
|
|
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* drivers/net/phy/marvell.c
|
||||
*
|
||||
* Driver for Marvell PHYs based on Linux driver
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <linux/mii.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/smscphy.h>
|
||||
|
||||
/* Known PHY IDs */
|
||||
#define MARVELL_PHY_ID_88E1101 0x01410c60
|
||||
#define MARVELL_PHY_ID_88E1112 0x01410c90
|
||||
#define MARVELL_PHY_ID_88E1111 0x01410cc0
|
||||
#define MARVELL_PHY_ID_88E1118 0x01410e10
|
||||
#define MARVELL_PHY_ID_88E1121R 0x01410cb0
|
||||
#define MARVELL_PHY_ID_88E1145 0x01410cd0
|
||||
#define MARVELL_PHY_ID_88E1149R 0x01410e50
|
||||
#define MARVELL_PHY_ID_88E1240 0x01410e30
|
||||
#define MARVELL_PHY_ID_88E1318S 0x01410e90
|
||||
#define MARVELL_PHY_ID_88E1116R 0x01410e40
|
||||
#define MARVELL_PHY_ID_88E1510 0x01410dd0
|
||||
|
||||
/* Mask used for ID comparisons */
|
||||
#define MARVELL_PHY_ID_MASK 0xfffffff0
|
||||
|
||||
/* Marvell Register Page register */
|
||||
#define MII_MARVELL_PHY_PAGE 22
|
||||
#define MII_MARVELL_PHY_DEFAULT_PAGE 0
|
||||
|
||||
#define MII_M1011_PHY_SCR 0x10
|
||||
#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
|
||||
|
||||
#define MII_M1011_PHY_STATUS 0x11
|
||||
#define MII_M1011_PHY_STATUS_1000 BIT(15)
|
||||
#define MII_M1011_PHY_STATUS_100 BIT(14)
|
||||
#define MII_M1011_PHY_STATUS_SPD_MASK \
|
||||
(MII_M1011_PHY_STATUS_1000 | MII_M1011_PHY_STATUS_100)
|
||||
#define MII_M1011_PHY_STATUS_FULLDUPLEX BIT(13)
|
||||
#define MII_M1011_PHY_STATUS_RESOLVED BIT(11)
|
||||
#define MII_M1011_PHY_STATUS_LINK BIT(10)
|
||||
|
||||
#define MII_88E1121_PHY_MSCR_PAGE 2
|
||||
#define MII_88E1121_PHY_MSCR 0x15
|
||||
#define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
|
||||
#define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
|
||||
#define MII_88E1121_PHY_MSCR_DELAY_MASK \
|
||||
(MII_88E1121_PHY_MSCR_RX_DELAY | MII_88E1121_PHY_MSCR_TX_DELAY)
|
||||
|
||||
/*
|
||||
* marvell_read_status
|
||||
*
|
||||
* Generic status code does not detect Fiber correctly!
|
||||
* Description:
|
||||
* Check the link, then figure out the current state
|
||||
* by comparing what we advertise with what the link partner
|
||||
* advertises. Start by checking the gigabit possibilities,
|
||||
* then move on to 10/100.
|
||||
*/
|
||||
static int marvell_read_status(struct phy_device *phydev)
|
||||
{
|
||||
int adv;
|
||||
int err;
|
||||
int lpa;
|
||||
int status = 0;
|
||||
|
||||
/* Update the link, but return if there
|
||||
* was an error */
|
||||
err = genphy_update_link(phydev);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (AUTONEG_ENABLE == phydev->autoneg) {
|
||||
status = phy_read(phydev, MII_M1011_PHY_STATUS);
|
||||
if (status < 0)
|
||||
return status;
|
||||
|
||||
lpa = phy_read(phydev, MII_LPA);
|
||||
if (lpa < 0)
|
||||
return lpa;
|
||||
|
||||
adv = phy_read(phydev, MII_ADVERTISE);
|
||||
if (adv < 0)
|
||||
return adv;
|
||||
|
||||
lpa &= adv;
|
||||
|
||||
if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
|
||||
phydev->duplex = DUPLEX_FULL;
|
||||
else
|
||||
phydev->duplex = DUPLEX_HALF;
|
||||
|
||||
status = status & MII_M1011_PHY_STATUS_SPD_MASK;
|
||||
phydev->pause = phydev->asym_pause = 0;
|
||||
|
||||
switch (status) {
|
||||
case MII_M1011_PHY_STATUS_1000:
|
||||
phydev->speed = SPEED_1000;
|
||||
break;
|
||||
|
||||
case MII_M1011_PHY_STATUS_100:
|
||||
phydev->speed = SPEED_100;
|
||||
break;
|
||||
|
||||
default:
|
||||
phydev->speed = SPEED_10;
|
||||
break;
|
||||
}
|
||||
|
||||
if (phydev->duplex == DUPLEX_FULL) {
|
||||
phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
|
||||
phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
|
||||
}
|
||||
} else {
|
||||
int bmcr = phy_read(phydev, MII_BMCR);
|
||||
|
||||
if (bmcr < 0)
|
||||
return bmcr;
|
||||
|
||||
if (bmcr & BMCR_FULLDPLX)
|
||||
phydev->duplex = DUPLEX_FULL;
|
||||
else
|
||||
phydev->duplex = DUPLEX_HALF;
|
||||
|
||||
if (bmcr & BMCR_SPEED1000)
|
||||
phydev->speed = SPEED_1000;
|
||||
else if (bmcr & BMCR_SPEED100)
|
||||
phydev->speed = SPEED_100;
|
||||
else
|
||||
phydev->speed = SPEED_10;
|
||||
|
||||
phydev->pause = phydev->asym_pause = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int m88e1121_config_init(struct phy_device *phydev)
|
||||
{
|
||||
u16 reg;
|
||||
int ret;
|
||||
|
||||
ret = phy_write(phydev, MII_MARVELL_PHY_PAGE,
|
||||
MII_88E1121_PHY_MSCR_PAGE);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Setup RGMII TX/RX delay */
|
||||
reg = phy_read(phydev, MII_88E1121_PHY_MSCR) &
|
||||
~MII_88E1121_PHY_MSCR_DELAY_MASK;
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
|
||||
reg |= MII_88E1121_PHY_MSCR_RX_DELAY;
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
|
||||
reg |= MII_88E1121_PHY_MSCR_TX_DELAY;
|
||||
ret = phy_write(phydev, MII_88E1121_PHY_MSCR, reg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_MARVELL_PHY_DEFAULT_PAGE);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Enable auto-crossover */
|
||||
ret = phy_write(phydev, MII_M1011_PHY_SCR,
|
||||
MII_M1011_PHY_SCR_AUTO_CROSS);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Reset PHY */
|
||||
ret = phy_write(phydev, MII_BMCR,
|
||||
phy_read(phydev, MII_BMCR) | BMCR_RESET);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_driver marvell_phys[] = {
|
||||
{
|
||||
.phy_id = MARVELL_PHY_ID_88E1121R,
|
||||
.phy_id_mask = MARVELL_PHY_ID_MASK,
|
||||
.drv.name = "Marvell 88E1121R",
|
||||
.features = PHY_GBIT_FEATURES,
|
||||
.config_init = m88e1121_config_init,
|
||||
.config_aneg = genphy_config_aneg,
|
||||
.read_status = marvell_read_status,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init marvell_phy_init(void)
|
||||
{
|
||||
return phy_drivers_register(marvell_phys, ARRAY_SIZE(marvell_phys));
|
||||
}
|
||||
fs_initcall(marvell_phy_init);
|
|
@ -43,6 +43,8 @@ int of_get_phy_mode(struct device_node *np)
|
|||
int err, i;
|
||||
|
||||
err = of_property_read_string(np, "phy-mode", &pm);
|
||||
if (err < 0)
|
||||
err = of_property_read_string(np, "phy-connection-type", &pm);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
|
@ -369,6 +369,8 @@ static inline int is_broadcast_ether_addr(const u8 *addr)
|
|||
return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff;
|
||||
}
|
||||
|
||||
#define ETH_ALEN 6
|
||||
|
||||
/**
|
||||
* random_ether_addr - Generate software assigned random Ethernet address
|
||||
* @addr: Pointer to a six-byte array containing the Ethernet address
|
||||
|
@ -379,9 +381,9 @@ static inline int is_broadcast_ether_addr(const u8 *addr)
|
|||
static inline void random_ether_addr(u8 *addr)
|
||||
{
|
||||
srand(get_time_ns());
|
||||
get_random_bytes(addr, 6);
|
||||
addr [0] &= 0xfe; /* clear multicast bit */
|
||||
addr [0] |= 0x02; /* set local assignment bit (IEEE802) */
|
||||
get_random_bytes(addr, ETH_ALEN);
|
||||
addr[0] &= 0xfe; /* clear multicast bit */
|
||||
addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in New Issue